2024-02-10 01:08:30 +03:00
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/* $NetBSD: makphy.c,v 1.73 2024/02/09 22:08:35 andvar Exp $ */
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2001-07-12 21:30:45 +04:00
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/*-
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* Copyright (c) 1998, 1999, 2000, 2001 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1997 Manuel Bouyer. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2019-01-16 08:11:06 +03:00
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/*
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* Driver for the Marvell 88E1000 ``Alaska'' 10/100/1000 PHY.
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*/
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2001-11-13 10:38:28 +03:00
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#include <sys/cdefs.h>
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2024-02-10 01:08:30 +03:00
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__KERNEL_RCSID(0, "$NetBSD: makphy.c,v 1.73 2024/02/09 22:08:35 andvar Exp $");
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2001-11-13 10:38:28 +03:00
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2001-07-12 21:30:45 +04:00
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/device.h>
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#include <sys/socket.h>
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#include <sys/errno.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mii/miidevs.h>
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2018-12-28 09:20:32 +03:00
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#include <dev/mii/makphyreg.h>
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2019-03-25 08:39:51 +03:00
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#include <dev/mii/makphyvar.h>
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2001-07-12 21:30:45 +04:00
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2008-05-04 21:06:09 +04:00
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static int makphymatch(device_t, cfdata_t, void *);
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static void makphyattach(device_t, device_t, void *);
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2001-07-12 21:30:45 +04:00
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2019-03-25 08:39:51 +03:00
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CFATTACH_DECL_NEW(makphy, sizeof(struct makphy_softc),
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2002-10-02 20:33:28 +04:00
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makphymatch, makphyattach, mii_phy_detach, mii_phy_activate);
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2001-07-12 21:30:45 +04:00
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2004-08-23 10:16:06 +04:00
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static int makphy_service(struct mii_softc *, struct mii_data *, int);
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static void makphy_status(struct mii_softc *);
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2007-02-23 06:03:10 +03:00
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static void makphy_reset(struct mii_softc *);
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2001-07-12 21:30:45 +04:00
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2018-12-28 09:20:32 +03:00
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static const struct mii_phy_funcs makphy_funcs = {
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2007-02-23 06:03:10 +03:00
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makphy_service, makphy_status, makphy_reset,
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2001-07-12 21:30:45 +04:00
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};
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2018-12-28 09:20:32 +03:00
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static const struct mii_phydesc makphys[] = {
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2019-02-24 20:22:21 +03:00
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MII_PHY_DESC(MARVELL, E1000_0),
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MII_PHY_DESC(MARVELL, E1000_3),
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MII_PHY_DESC(MARVELL, E1000_5),
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MII_PHY_DESC(MARVELL, E1000_6),
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MII_PHY_DESC(xxMARVELL, E1000_3),
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MII_PHY_DESC(xxMARVELL, E1000_5),
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MII_PHY_DESC(xxMARVELL, E1000S),
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MII_PHY_DESC(xxMARVELL, E1011),
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MII_PHY_DESC(xxMARVELL, E1101),
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MII_PHY_DESC(xxMARVELL, E1111),
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MII_PHY_DESC(xxMARVELL, E1112),
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MII_PHY_DESC(xxMARVELL, E1116),
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MII_PHY_DESC(xxMARVELL, E1116R),
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MII_PHY_DESC(xxMARVELL, E1118),
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MII_PHY_DESC(xxMARVELL, E1145),
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MII_PHY_DESC(xxMARVELL, E1149),
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MII_PHY_DESC(xxMARVELL, E1149R),
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MII_PHY_DESC(xxMARVELL, E1240),
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MII_PHY_DESC(xxMARVELL, E1318S),
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MII_PHY_DESC(xxMARVELL, E1512),
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MII_PHY_DESC(xxMARVELL, E1543),
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MII_PHY_DESC(xxMARVELL, E3016),
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MII_PHY_DESC(xxMARVELL, E3082),
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MII_PHY_DESC(xxMARVELL, PHYG65G),
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2020-10-20 11:53:34 +03:00
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MII_PHY_DESC(xxMARVELL, I347),
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2019-02-24 20:22:21 +03:00
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MII_PHY_END,
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2001-07-12 21:30:45 +04:00
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};
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2018-12-30 09:33:30 +03:00
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#define MAKARG_PDOWN true /* Power DOWN */
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#define MAKARG_PUP false /* Power UP */
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2019-02-19 08:47:08 +03:00
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static bool
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makphy_isi210(device_t parent, struct mii_attach_args *ma)
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{
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/* I21[01]'s model number is 0 */
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if ((MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_xxMARVELL)
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2019-02-27 21:21:04 +03:00
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&& (MII_MODEL(ma->mii_id2) == MII_MODEL_xxMARVELL_I210)
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2019-02-19 08:47:08 +03:00
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&& (device_is_a(parent, "wm")))
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return true;
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return false;
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}
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2004-08-23 10:16:06 +04:00
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static int
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2008-05-04 21:06:09 +04:00
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makphymatch(device_t parent, cfdata_t match, void *aux)
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2001-07-12 21:30:45 +04:00
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{
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struct mii_attach_args *ma = aux;
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2018-12-28 09:20:32 +03:00
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if (mii_phy_match(ma, makphys) != NULL)
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2019-02-19 08:47:08 +03:00
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return 10;
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2001-07-12 21:30:45 +04:00
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2019-02-19 08:47:08 +03:00
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if (makphy_isi210(parent, ma))
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return 10;
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2019-03-25 10:34:13 +03:00
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2019-02-19 08:47:08 +03:00
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return 0;
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2001-07-12 21:30:45 +04:00
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}
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2004-08-23 10:16:06 +04:00
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static void
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2008-05-04 21:06:09 +04:00
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makphyattach(device_t parent, device_t self, void *aux)
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2001-07-12 21:30:45 +04:00
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{
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2006-03-29 10:51:47 +04:00
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struct mii_softc *sc = device_private(self);
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2001-07-12 21:30:45 +04:00
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struct mii_attach_args *ma = aux;
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struct mii_data *mii = ma->mii_data;
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const struct mii_phydesc *mpd;
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2019-03-25 08:39:51 +03:00
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struct makphy_softc *maksc = (struct makphy_softc *)sc;
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2019-02-19 08:47:08 +03:00
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const char *name;
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2019-03-25 08:39:51 +03:00
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uint16_t reg, model;
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2021-12-28 09:34:40 +03:00
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int rv;
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2001-07-12 21:30:45 +04:00
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2018-12-28 09:20:32 +03:00
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mpd = mii_phy_match(ma, makphys);
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2003-04-29 05:49:33 +04:00
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aprint_naive(": Media interface\n");
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2019-02-19 08:47:08 +03:00
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if (mpd)
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name = mpd->mpd_name;
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2019-03-25 08:39:51 +03:00
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else if (makphy_isi210(parent, ma)) {
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2019-02-19 08:47:08 +03:00
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name = MII_STR_xxMARVELL_I210;
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2019-03-25 08:39:51 +03:00
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maksc->sc_flags |= MAKPHY_F_I210;
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} else
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2019-02-19 08:47:08 +03:00
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panic("Unknown PHY");
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aprint_normal(": %s, rev. %d\n", name, MII_REV(ma->mii_id2));
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2001-07-12 21:30:45 +04:00
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2008-05-04 21:06:09 +04:00
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sc->mii_dev = self;
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2016-11-08 11:48:35 +03:00
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sc->mii_mpd_oui = MII_OUI(ma->mii_id1, ma->mii_id2);
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2019-03-25 08:39:51 +03:00
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sc->mii_mpd_model = model = MII_MODEL(ma->mii_id2);
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2016-11-08 11:48:35 +03:00
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sc->mii_mpd_rev = MII_REV(ma->mii_id2);
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2001-07-12 21:30:45 +04:00
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sc->mii_inst = mii->mii_instance;
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sc->mii_phy = ma->mii_phyno;
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2018-12-28 09:20:32 +03:00
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sc->mii_funcs = &makphy_funcs;
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2001-07-12 21:30:45 +04:00
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sc->mii_pdata = mii;
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2002-03-25 23:51:24 +03:00
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sc->mii_flags = ma->mii_flags;
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2001-07-12 21:30:45 +04:00
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2020-03-16 02:04:50 +03:00
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mii_lock(mii);
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2019-03-25 08:39:51 +03:00
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switch (model) {
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case MII_MODEL_xxMARVELL_E1000:
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if ((maksc->sc_flags & MAKPHY_F_I210) != 0)
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goto page0;
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/* FALLTHROUGH */
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case MII_MODEL_xxMARVELL_E1000_3:
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case MII_MODEL_xxMARVELL_E1000S:
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case MII_MODEL_xxMARVELL_E1000_5:
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/* 88E1000 series has no EADR */
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break;
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default:
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page0:
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/* Make sure page 0 is selected. */
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if (PHY_WRITE(sc, MAKPHY_EADR, 0) != 0)
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aprint_verbose_dev(self,
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"Failed to access EADR. Are you an emulator?\n");
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break;
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}
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2018-06-16 20:44:53 +03:00
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2001-07-12 21:30:45 +04:00
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PHY_RESET(sc);
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Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
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PHY_READ(sc, MII_BMSR, &sc->mii_capabilities);
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sc->mii_capabilities &= ma->mii_capmask;
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2021-12-28 09:34:40 +03:00
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if (sc->mii_capabilities & BMSR_EXTSTAT) {
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rv = PHY_READ(sc, MII_EXTSR, &sc->mii_extcapabilities);
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if (rv != 0) {
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aprint_verbose_dev(self, "Failed to read EXTSR. "
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"Are you an emulator?. "
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"Regard as 1000BASE-T.\n");
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sc->mii_extcapabilities
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|= EXTSR_1000TFDX | EXTSR_1000THDX;
|
2022-01-06 10:39:10 +03:00
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/*
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* Also assume it doesn't support PSSR_LINK bit.
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* It's for QEMU.
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*/
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maksc->sc_flags |= MAKPHY_QUIRK_PSSR_LINK;
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2021-12-28 09:34:40 +03:00
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}
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}
|
2001-07-12 21:30:45 +04:00
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2019-12-12 12:25:37 +03:00
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if (((sc->mii_extcapabilities & (EXTSR_1000TFDX | EXTSR_1000THDX))
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!= 0)
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&& ((sc->mii_extcapabilities & (EXTSR_1000XFDX | EXTSR_1000XHDX))
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|
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!= 0)) {
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bool fiberonly = false, copperonly = false;
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|
2020-01-28 08:08:02 +03:00
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/* Both copper and fiber are set. check MODE[] */
|
2019-12-12 12:25:37 +03:00
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switch (sc->mii_mpd_model) {
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case MII_MODEL_xxMARVELL_E1011:
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case MII_MODEL_xxMARVELL_E1111:
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/* These devices have ESSR register */
|
2021-12-28 09:35:37 +03:00
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rv = PHY_READ(sc, MAKPHY_ESSR, ®);
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if (rv != 0) {
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/*
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|
|
* XXX Emulator (e.g qemu) may not implement
|
|
|
|
* the ESSR register. If so, regard as copper
|
|
|
|
* media.
|
|
|
|
*/
|
|
|
|
copperonly = true;
|
|
|
|
aprint_verbose_dev(self, "Failed to access "
|
|
|
|
"ESSR. Are you an emulator? Regard as "
|
|
|
|
"copper only media.\n");
|
|
|
|
} else if ((reg & ESSR_AUTOSEL_DISABLE) != 0) {
|
2019-12-12 12:25:37 +03:00
|
|
|
switch (reg & ESSR_HWCFG_MODE) {
|
|
|
|
case ESSR_RTBI_FIBER:
|
|
|
|
case ESSR_RGMII_FIBER:
|
|
|
|
case ESSR_RGMII_SGMII: /* right? */
|
|
|
|
case ESSR_TBI_FIBER:
|
|
|
|
case ESSR_GMII_FIBER:
|
|
|
|
fiberonly = true;
|
|
|
|
break;
|
|
|
|
case ESSR_SGMII_WC_COPPER:
|
|
|
|
case ESSR_SGMII_WOC_COPPER:
|
|
|
|
case ESSR_RTBI_COPPER:
|
|
|
|
case ESSR_RGMII_COPPER:
|
|
|
|
case ESSR_GMII_COPPER:
|
|
|
|
copperonly = true;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
2021-12-28 09:36:29 +03:00
|
|
|
} else
|
|
|
|
maksc->sc_flags |= MAKPHY_F_FICO_AUTOSEL;
|
2019-12-12 12:25:37 +03:00
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (fiberonly || copperonly)
|
|
|
|
aprint_debug_dev(self, "both copper and fiber are set "
|
|
|
|
"but MODE[] is %s only.\n",
|
|
|
|
fiberonly ? "fiber" : "copper");
|
|
|
|
if (fiberonly)
|
|
|
|
sc->mii_extcapabilities
|
|
|
|
&= ~(EXTSR_1000TFDX | EXTSR_1000THDX);
|
|
|
|
else if (copperonly) {
|
|
|
|
sc->mii_extcapabilities
|
|
|
|
&= ~(EXTSR_1000XFDX | EXTSR_1000XHDX);
|
|
|
|
sc->mii_flags &= ~MIIF_IS_1000X;
|
|
|
|
}
|
|
|
|
}
|
2020-03-16 02:04:50 +03:00
|
|
|
mii_unlock(mii);
|
2019-11-27 13:19:20 +03:00
|
|
|
mii_phy_add_media(sc);
|
2001-07-12 21:30:45 +04:00
|
|
|
}
|
|
|
|
|
2007-02-23 06:03:10 +03:00
|
|
|
static void
|
|
|
|
makphy_reset(struct mii_softc *sc)
|
|
|
|
{
|
2019-03-25 08:39:51 +03:00
|
|
|
struct makphy_softc *maksc = (struct makphy_softc *)sc;
|
2019-01-16 08:19:30 +03:00
|
|
|
uint16_t reg;
|
2018-12-28 09:20:32 +03:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
KASSERT(mii_locked(sc->mii_pdata));
|
|
|
|
|
2018-12-28 09:20:32 +03:00
|
|
|
mii_phy_reset(sc);
|
2007-02-23 06:03:10 +03:00
|
|
|
|
2019-11-26 11:19:51 +03:00
|
|
|
/* Initialize PHY Specific Control Register. */
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MAKPHY_PSCR, ®);
|
2007-02-23 06:03:10 +03:00
|
|
|
|
2018-06-16 20:44:53 +03:00
|
|
|
/* Assert CRS on transmit. */
|
|
|
|
switch (sc->mii_mpd_model) {
|
2018-12-28 09:20:32 +03:00
|
|
|
case MII_MODEL_MARVELL_E1000_0:
|
2019-03-25 08:39:51 +03:00
|
|
|
if ((maksc->sc_flags & MAKPHY_F_I210) != 0)
|
|
|
|
break;
|
|
|
|
/* FALLTHROUGH */
|
2018-12-28 09:20:32 +03:00
|
|
|
case MII_MODEL_MARVELL_E1000_3:
|
|
|
|
case MII_MODEL_MARVELL_E1000_5:
|
|
|
|
case MII_MODEL_MARVELL_E1000_6:
|
|
|
|
case MII_MODEL_xxMARVELL_E1000S:
|
|
|
|
case MII_MODEL_xxMARVELL_E1011:
|
|
|
|
case MII_MODEL_xxMARVELL_E1111:
|
|
|
|
reg |= PSCR_CRS_ON_TX;
|
2018-06-16 20:44:53 +03:00
|
|
|
break;
|
2018-12-28 09:20:32 +03:00
|
|
|
default: /* No PSCR_CRS_ON_TX bit */
|
2018-06-16 20:44:53 +03:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Enable scrambler if necessary. */
|
|
|
|
if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E3016)
|
2018-12-28 09:20:32 +03:00
|
|
|
reg &= ~E3016_PSCR_SCRAMBLE_DIS;
|
2018-06-16 20:44:53 +03:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Store next page in the Link Partner Next Page register for
|
|
|
|
* compatibility with 802.3ab.
|
|
|
|
*/
|
|
|
|
if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E3016)
|
2018-12-28 09:20:32 +03:00
|
|
|
reg |= E3016_PSCR_REG8NXTPG;
|
2018-06-16 20:44:53 +03:00
|
|
|
|
2018-12-28 09:20:32 +03:00
|
|
|
PHY_WRITE(sc, MAKPHY_PSCR, reg);
|
2018-06-16 20:44:53 +03:00
|
|
|
|
|
|
|
/* Configure LEDs if they were left unconfigured. */
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E3016) {
|
|
|
|
PHY_READ(sc, 0x16, ®);
|
|
|
|
if (reg == 0) {
|
|
|
|
reg = (0x0b << 8) | (0x05 << 4) | 0x04; /* XXX */
|
|
|
|
PHY_WRITE(sc, 0x16, reg);
|
|
|
|
}
|
2018-06-16 20:44:53 +03:00
|
|
|
}
|
|
|
|
|
2018-12-28 09:20:32 +03:00
|
|
|
mii_phy_reset(sc);
|
2007-02-23 06:03:10 +03:00
|
|
|
}
|
|
|
|
|
2018-12-30 09:33:30 +03:00
|
|
|
static void
|
|
|
|
makphy_pdown(struct mii_softc *sc, bool pdown)
|
|
|
|
{
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t bmcr, new;
|
2018-12-30 09:33:30 +03:00
|
|
|
bool need_reset = false;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* XXX
|
|
|
|
* PSCR (register 16) should be modified on some chips.
|
|
|
|
*/
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMCR, &bmcr);
|
2018-12-30 09:33:30 +03:00
|
|
|
if (pdown)
|
|
|
|
new = bmcr | BMCR_PDOWN;
|
|
|
|
else
|
|
|
|
new = bmcr & ~BMCR_PDOWN;
|
|
|
|
if (bmcr != new)
|
|
|
|
need_reset = true;
|
|
|
|
|
|
|
|
if (need_reset)
|
|
|
|
new |= BMCR_RESET;
|
|
|
|
PHY_WRITE(sc, MII_BMCR, new);
|
|
|
|
}
|
|
|
|
|
2004-08-23 10:16:06 +04:00
|
|
|
static int
|
2001-08-25 22:04:01 +04:00
|
|
|
makphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
|
2001-07-12 21:30:45 +04:00
|
|
|
{
|
|
|
|
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
uint16_t bmcr;
|
2018-06-16 20:44:53 +03:00
|
|
|
|
|
|
|
if (!device_is_active(sc->mii_dev))
|
2019-02-19 08:47:08 +03:00
|
|
|
return ENXIO;
|
2001-07-12 21:30:45 +04:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
KASSERT(mii_locked(mii));
|
|
|
|
|
2001-07-12 21:30:45 +04:00
|
|
|
switch (cmd) {
|
|
|
|
case MII_POLLSTAT:
|
2019-03-25 10:34:13 +03:00
|
|
|
/* If we're not polling our PHY instance, just return. */
|
2001-07-12 21:30:45 +04:00
|
|
|
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
2019-02-19 08:47:08 +03:00
|
|
|
return 0;
|
2001-07-12 21:30:45 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MII_MEDIACHG:
|
|
|
|
/*
|
|
|
|
* If the media indicates a different PHY instance,
|
|
|
|
* isolate ourselves.
|
|
|
|
*/
|
|
|
|
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMCR, &bmcr);
|
2018-06-18 12:12:17 +03:00
|
|
|
PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
|
2019-02-19 08:47:08 +03:00
|
|
|
return 0;
|
2001-07-12 21:30:45 +04:00
|
|
|
}
|
|
|
|
|
2019-03-25 10:34:13 +03:00
|
|
|
/* If the interface is not up, don't do anything. */
|
2001-07-12 21:30:45 +04:00
|
|
|
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
|
|
|
break;
|
|
|
|
|
2018-12-30 09:33:30 +03:00
|
|
|
/* Try to power up the PHY in case it's down */
|
|
|
|
if (IFM_SUBTYPE(ife->ifm_media) != IFM_NONE)
|
|
|
|
makphy_pdown(sc, MAKARG_PUP);
|
|
|
|
|
2001-07-12 21:30:45 +04:00
|
|
|
mii_phy_setmedia(sc);
|
2018-06-16 20:44:53 +03:00
|
|
|
|
|
|
|
/*
|
2024-02-10 01:08:30 +03:00
|
|
|
* If autonegotiation is not enabled, we need a
|
2018-06-16 20:44:53 +03:00
|
|
|
* software reset for the settings to take effect.
|
|
|
|
*/
|
2018-12-30 09:33:30 +03:00
|
|
|
if (IFM_SUBTYPE(ife->ifm_media) == IFM_NONE)
|
|
|
|
makphy_pdown(sc, MAKARG_PDOWN);
|
|
|
|
else if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMCR, &bmcr);
|
2018-06-18 12:12:17 +03:00
|
|
|
PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET);
|
2006-10-21 17:55:30 +04:00
|
|
|
}
|
2001-07-12 21:30:45 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MII_TICK:
|
2019-03-25 10:34:13 +03:00
|
|
|
/* If we're not currently selected, just return. */
|
2001-07-12 21:30:45 +04:00
|
|
|
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
2019-02-19 08:47:08 +03:00
|
|
|
return 0;
|
2001-07-12 21:30:45 +04:00
|
|
|
|
|
|
|
if (mii_phy_tick(sc) == EJUSTRETURN)
|
2019-02-19 08:47:08 +03:00
|
|
|
return 0;
|
2001-07-12 21:30:45 +04:00
|
|
|
break;
|
|
|
|
|
|
|
|
case MII_DOWN:
|
|
|
|
mii_phy_down(sc);
|
2019-02-19 08:47:08 +03:00
|
|
|
return 0;
|
2001-07-12 21:30:45 +04:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Update the media status. */
|
|
|
|
mii_phy_status(sc);
|
|
|
|
|
|
|
|
/* Callback if something changed. */
|
|
|
|
mii_phy_update(sc, cmd);
|
2019-02-19 08:47:08 +03:00
|
|
|
return 0;
|
2001-07-12 21:30:45 +04:00
|
|
|
}
|
|
|
|
|
2004-08-23 10:16:06 +04:00
|
|
|
static void
|
2001-08-25 22:04:01 +04:00
|
|
|
makphy_status(struct mii_softc *sc)
|
2001-07-12 21:30:45 +04:00
|
|
|
{
|
2022-01-06 10:39:10 +03:00
|
|
|
struct makphy_softc *maksc = (struct makphy_softc *)sc;
|
2001-07-12 21:30:45 +04:00
|
|
|
struct mii_data *mii = sc->mii_pdata;
|
2019-12-12 12:25:37 +03:00
|
|
|
uint16_t bmcr, gsr, pssr, essr;
|
2001-07-12 21:30:45 +04:00
|
|
|
|
2020-03-16 02:04:50 +03:00
|
|
|
KASSERT(mii_locked(mii));
|
|
|
|
|
2001-07-12 21:30:45 +04:00
|
|
|
mii->mii_media_status = IFM_AVALID;
|
|
|
|
mii->mii_media_active = IFM_ETHER;
|
|
|
|
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_BMCR, &bmcr);
|
2018-12-28 09:20:32 +03:00
|
|
|
/* XXX FIXME: Use different page for Fiber on newer chips */
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MAKPHY_PSSR, &pssr);
|
2001-07-12 21:30:45 +04:00
|
|
|
|
2022-01-06 10:39:10 +03:00
|
|
|
if ((maksc->sc_flags & MAKPHY_QUIRK_PSSR_LINK) != 0) {
|
|
|
|
uint16_t bmsr;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* QEMU e1000 driver has the PSSR register but it doesn't
|
|
|
|
* support the PSSR_LINK bit well. It always returns 1.
|
|
|
|
* To avoid this problem, use the BMSR_LINK bit. It's not
|
|
|
|
* required to read it twice as real device because it's not
|
|
|
|
* latched.
|
|
|
|
*/
|
|
|
|
PHY_READ(sc, MII_BMSR, &bmsr);
|
|
|
|
if (bmsr & BMSR_LINK)
|
|
|
|
pssr |= MAKPHY_PSSR_LINK;
|
|
|
|
else
|
|
|
|
pssr &= ~MAKPHY_PSSR_LINK;
|
|
|
|
}
|
|
|
|
|
2020-08-03 10:25:59 +03:00
|
|
|
if (pssr & MAKPHY_PSSR_LINK)
|
2001-07-12 21:30:45 +04:00
|
|
|
mii->mii_media_status |= IFM_ACTIVE;
|
|
|
|
|
2018-12-30 09:33:30 +03:00
|
|
|
if (bmcr & BMCR_LOOP)
|
|
|
|
mii->mii_media_active |= IFM_LOOP;
|
|
|
|
|
2020-11-04 12:15:10 +03:00
|
|
|
if (bmcr & (BMCR_ISO | BMCR_PDOWN)) {
|
2018-06-18 12:12:17 +03:00
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2018-12-30 09:33:30 +03:00
|
|
|
if ((bmcr & BMCR_AUTOEN) != 0) {
|
|
|
|
/*
|
|
|
|
* Check Speed and Duplex Resolved bit.
|
|
|
|
* Note that this bit is always 1 when autonego is not enabled.
|
|
|
|
*/
|
2020-08-03 10:25:59 +03:00
|
|
|
if (!(pssr & MAKPHY_PSSR_RESOLVED)) {
|
2018-12-30 09:33:30 +03:00
|
|
|
/* Erg, still trying, I guess... */
|
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
} else {
|
2020-08-03 10:25:59 +03:00
|
|
|
if ((pssr & MAKPHY_PSSR_LINK) == 0) {
|
2018-12-30 09:33:30 +03:00
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
return;
|
|
|
|
}
|
2001-07-12 21:30:45 +04:00
|
|
|
}
|
|
|
|
|
2019-12-12 12:25:37 +03:00
|
|
|
/*
|
|
|
|
* XXX The following code support Fiber/Copper auto select mode
|
|
|
|
* only for 88E1011, 88E1111 and 88E1112. For other chips, the document
|
|
|
|
* is required.
|
|
|
|
*/
|
2018-06-16 20:44:53 +03:00
|
|
|
if (sc->mii_flags & MIIF_IS_1000X) {
|
2019-12-12 12:25:37 +03:00
|
|
|
/* Not in Fiber/Copper auto select mode */
|
|
|
|
mii->mii_media_active |= IFM_1000_SX;
|
|
|
|
} else if ((sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1011) ||
|
|
|
|
(sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1111)) {
|
2021-12-28 09:36:29 +03:00
|
|
|
if ((maksc->sc_flags & MAKPHY_F_FICO_AUTOSEL) != 0) {
|
|
|
|
/* Fiber/Copper auto select mode */
|
|
|
|
PHY_READ(sc, MAKPHY_ESSR, &essr);
|
|
|
|
if ((essr & ESSR_FIBER_LINK) == 0)
|
|
|
|
goto copper;
|
|
|
|
else {
|
|
|
|
/* Regard as 1000BASE-SX */
|
|
|
|
mii->mii_media_active |= IFM_1000_SX;
|
|
|
|
}
|
|
|
|
} else
|
2019-12-12 12:25:37 +03:00
|
|
|
goto copper;
|
|
|
|
} else if (sc->mii_mpd_model == MII_MODEL_xxMARVELL_E1112) {
|
|
|
|
/* Fiber/Copper auto select mode */
|
|
|
|
|
|
|
|
PHY_READ(sc, MAKPHY_PSSR, &pssr);
|
2020-08-03 10:25:59 +03:00
|
|
|
if ((pssr & MAKPHY_PSSR_RESOLUTION_FIBER) == 0)
|
2019-12-12 12:25:37 +03:00
|
|
|
goto copper;
|
|
|
|
|
2020-08-03 10:25:59 +03:00
|
|
|
switch (MAKPHY_PSSR_SPEED_get(pssr)) {
|
2019-12-12 12:25:37 +03:00
|
|
|
case SPEED_1000:
|
|
|
|
mii->mii_media_active |= IFM_1000_SX;
|
|
|
|
break;
|
|
|
|
case SPEED_100:
|
|
|
|
mii->mii_media_active |= IFM_100_FX;
|
|
|
|
break;
|
|
|
|
default: /* Undefined (reserved) value */
|
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
mii->mii_media_status = 0;
|
|
|
|
return;
|
|
|
|
}
|
2018-06-16 20:44:53 +03:00
|
|
|
} else {
|
2019-12-12 12:25:37 +03:00
|
|
|
copper:
|
2020-08-03 10:25:59 +03:00
|
|
|
switch (MAKPHY_PSSR_SPEED_get(pssr)) {
|
2018-12-28 09:20:32 +03:00
|
|
|
case SPEED_1000:
|
2001-07-12 21:30:45 +04:00
|
|
|
mii->mii_media_active |= IFM_1000_T;
|
2018-12-28 09:20:32 +03:00
|
|
|
break;
|
|
|
|
case SPEED_100:
|
2001-07-12 21:30:45 +04:00
|
|
|
mii->mii_media_active |= IFM_100_TX;
|
2018-12-28 09:20:32 +03:00
|
|
|
break;
|
|
|
|
case SPEED_10:
|
2001-07-12 21:30:45 +04:00
|
|
|
mii->mii_media_active |= IFM_10_T;
|
2018-12-28 09:20:32 +03:00
|
|
|
break;
|
2018-12-30 09:33:30 +03:00
|
|
|
default: /* Undefined (reserved) value */
|
2018-12-28 09:20:32 +03:00
|
|
|
mii->mii_media_active |= IFM_NONE;
|
|
|
|
mii->mii_media_status = 0;
|
|
|
|
return;
|
|
|
|
}
|
2018-06-16 20:44:53 +03:00
|
|
|
}
|
2001-07-12 21:30:45 +04:00
|
|
|
|
2020-08-03 10:25:59 +03:00
|
|
|
if (pssr & MAKPHY_PSSR_DUPLEX)
|
2018-06-16 20:44:53 +03:00
|
|
|
mii->mii_media_active |= mii_phy_flowstatus(sc) | IFM_FDX;
|
|
|
|
else
|
|
|
|
mii->mii_media_active |= IFM_HDX;
|
2001-07-12 21:30:45 +04:00
|
|
|
|
2018-06-16 20:44:53 +03:00
|
|
|
if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
|
Change MII PHY read/write API from:
int (*mii_readreg_t)(device_t, int, int);
void (*mii_writereg_t)(device_t, int, int, int);
to:
int (*mii_readreg_t)(device_t, int, int, uint16_t *);
int (*mii_writereg_t)(device_t, int, int, uint16_t);
Now we can test if a read/write operation failed or not by the return value.
In 802.3 spec says that the PHY shall not respond to read/write transaction
to the unimplemented register(22.2.4.3). Detecting timeout can be used to
check whether a register is implemented or not (if the register conforms to
the spec). ukphy(4) can be used this for MII_MMDACR and MII_MMDAADR.
Note that I noticed that the following code do infinite loop in the
read/wirte function. If it accesses unimplemented PHY register, it will hang.
It should be fixed:
arm/at91/at91emac.c
arm/ep93xx/epe.c
arm/omap/omapl1x_emac.c
mips/ralink/ralink_eth.c
arch/powerpc/booke/dev/pq3etsec.c(read)
dev/cadence/if_cemac.c <- hkenken
dev/ic/lan9118.c
Tested with the following device:
axe+ukphy
axe+rgephy
axen+rgephy (tested by Andrius V)
wm+atphy
wm+ukphy
wm+igphy
wm+ihphy
wm+makphy
sk+makphy
sk+brgphy
sk+gentbi
msk+makphy
sip+icsphy
sip+ukphy
re+rgephy
bge+brgphy
bnx+brgphy
gsip+gphyter
rtk+rlphy
fxp+inphy (tested by Andrius V)
tlp+acphy
ex+exphy
epic+qsphy
vge+ciphy (tested by Andrius V)
vr+ukphy (tested by Andrius V)
vte+ukphy (tested by Andrius V)
Not tested (MAC):
arm:at91emac
arm:cemac
arm:epe
arm:geminigmac
arm:enet
arm:cpsw
arm:emac(omac)
arm:emac(sunxi)
arm:npe
evbppc:temac
macppc:bm
macppc:gm
mips:aumac
mips:ae
mips:cnmac
mips:reth
mips:sbmac
playstation2:smap
powerpc:tsec
powerpc:emac(ibm4xx)
sgimips:mec
sparc:be
sf
ne(ax88190, dl10019)
awge
ep
gem
hme
smsh
mtd
sm
age
alc
ale
bce
cas
et
jme
lii
nfe
pcn
ste
stge
tl
xi
aue
mue
smsc
udav
url
Not tested (PHY):
amhphy
bmtphy
dmphy
etphy
glxtphy
ikphy
iophy
lxtphy
nsphyter
pnaphy
rdcphy
sqphy
tlphy
tqphy
urlphy
2019-01-22 06:42:24 +03:00
|
|
|
PHY_READ(sc, MII_100T2SR, &gsr);
|
2018-06-18 12:12:17 +03:00
|
|
|
if (gsr & GTSR_MS_RES)
|
2018-06-16 20:44:53 +03:00
|
|
|
mii->mii_media_active |= IFM_ETH_MASTER;
|
|
|
|
}
|
2001-07-12 21:30:45 +04:00
|
|
|
}
|