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Merging cyassl/master and STM.LPC

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This commit is contained in:
kojo 2013-05-26 10:05:35 +09:00
parent 9382f74f2e
commit e4a95342f1
9 changed files with 0 additions and 656 deletions
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4
IDE/MDK-ARM/MDK-ARM/CyaSSL/config-FS.h
View File

@ -76,11 +76,7 @@
// <h>STM32 Hardware Crypt
// <e>STM32F2 Hardware RNG
<<<<<<< HEAD
#define MDK_CONF_STM32F2_RNG 0
=======
#define MDK_CONF_STM32F2_RNG 1
>>>>>>> cyassl/master
#if MDK_CONF_STM32F2_RNG == 1
#define STM32F2_RNG
#else

48
IDE/MDK-ARM/MDK-ARM/CyaSSL/config-RTX-TCP-FS.h
View File

@ -99,11 +99,7 @@
// </h>
// <h>STM32 Hardware Crypt
// <e>STM32F2 Hardware RNG
<<<<<<< HEAD
#define MDK_CONF_STM32F2_RNG 0
=======
#define MDK_CONF_STM32F2_RNG 1
>>>>>>> cyassl/master
#if MDK_CONF_STM32F2_RNG == 1
#define STM32F2_RNG
#else
@ -131,31 +127,19 @@
// </e>
// <e>CertGen
<<<<<<< HEAD
#define MDK_CONF_CERT_GEN 1
=======
#define MDK_CONF_CERT_GEN 0
>>>>>>> cyassl/master
#if MDK_CONF_CERT_GEN == 1
#define CYASSL_CERT_GEN
#endif
// </e>
// <e>KeyGen
<<<<<<< HEAD
#define MDK_CONF_KEY_GEN 1
=======
#define MDK_CONF_KEY_GEN 0
>>>>>>> cyassl/master
#if MDK_CONF_KEY_GEN == 1
#define CYASSL_KEY_GEN
#endif
// </e>
// <e>CRL
<<<<<<< HEAD
#define MDK_CONF_DER_LOAD 1
=======
#define MDK_CONF_DER_LOAD 0
>>>>>>> cyassl/master
#if MDK_CONF_DER_LOAD == 1
#define CYASSL_DER_LOAD
#endif
@ -176,11 +160,7 @@
// <h>MD5, SHA, SHA-256, AES, RC4, ASN, RSA
// </h>
// <e>MD2
<<<<<<< HEAD
#define MDK_CONF_MD2 1
=======
#define MDK_CONF_MD2 0
>>>>>>> cyassl/master
#if MDK_CONF_MD2 == 1
#define CYASSL_MD2
#endif
@ -193,21 +173,13 @@
// </e>
// <e>SHA-384
// <i>This has to be with SHA512
<<<<<<< HEAD
#define MDK_CONF_SHA384 1
=======
#define MDK_CONF_SHA384 0
>>>>>>> cyassl/master
#if MDK_CONF_SHA384 == 1
#define CYASSL_SHA384
#endif
// </e>
// <e>SHA-512
<<<<<<< HEAD
#define MDK_CONF_SHA512 1
=======
#define MDK_CONF_SHA512 0
>>>>>>> cyassl/master
#if MDK_CONF_SHA512 == 1
#define CYASSL_SHA512
#endif
@ -225,11 +197,7 @@
#endif
// </e>
// <e>HC128
<<<<<<< HEAD
#define MDK_CONF_HC128 1
=======
#define MDK_CONF_HC128 0
>>>>>>> cyassl/master
#if MDK_CONF_HC128 == 1
#define HAVE_HC128
#endif
@ -242,11 +210,7 @@
// </e>
// <e>AEAD
<<<<<<< HEAD
#define MDK_CONF_AEAD 1
=======
#define MDK_CONF_AEAD 0
>>>>>>> cyassl/master
#if MDK_CONF_AEAD == 1
#define HAVE_AEAD
#endif
@ -258,11 +222,7 @@
#endif
// </e>
// <e>CAMELLIA
<<<<<<< HEAD
#define MDK_CONF_CAMELLIA 1
=======
#define MDK_CONF_CAMELLIA 0
>>>>>>> cyassl/master
#if MDK_CONF_CAMELLIA == 1
#define HAVE_CAMELLIA
#endif
@ -301,21 +261,13 @@
#endif
// </e>
// <e>AESCCM (Turn off Hardware Crypt)
<<<<<<< HEAD
#define MDK_CONF_AESCCM 1
=======
#define MDK_CONF_AESCCM 0
>>>>>>> cyassl/master
#if MDK_CONF_AESCCM == 1
#define HAVE_AESCCM
#endif
// </e>
// <e>AESGCM (Turn off Hardware Crypt)
<<<<<<< HEAD
#define MDK_CONF_AESGCM 1
=======
#define MDK_CONF_AESGCM 0
>>>>>>> cyassl/master
#if MDK_CONF_AESGCM == 1
#define HAVE_AESGCM
#define BUILD_AESGCM

53
IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.c
View File

@ -59,11 +59,7 @@ unsigned long inet_addr(const char *cp)
/*** tcp_connect is actually associated with following syassl_tcp_connect. ***/
int Cyassl_connect(int sd, const struct sockaddr* sa, int sz)
{
<<<<<<< HEAD
int ret = 0 ;
=======
int ret ;
>>>>>>> cyassl/master
#if defined(CYASSL_KEIL_TCP_NET)
SOCKADDR_IN addr ;
@ -90,11 +86,7 @@ int Cyassl_connect(int sd, const struct sockaddr* sa, int sz)
int Cyassl_accept(int sd, struct sockaddr *addr, int *addrlen)
{
<<<<<<< HEAD
int ret = 0 ;
=======
int ret ;
>>>>>>> cyassl/master
#if defined(CYASSL_KEIL_TCP_NET)
while(1) {
@ -118,11 +110,7 @@ int Cyassl_accept(int sd, struct sockaddr *addr, int *addrlen)
int Cyassl_recv(int sd, void *buf, size_t len, int flags)
{
<<<<<<< HEAD
int ret = 0;
=======
int ret ;
>>>>>>> cyassl/master
#if defined(CYASSL_KEIL_TCP_NET)
while(1) {
#undef recv /* Go to KEIL TCPnet recv */
@ -144,11 +132,7 @@ int Cyassl_recv(int sd, void *buf, size_t len, int flags)
int Cyassl_send(int sd, const void *buf, size_t len, int flags)
{
<<<<<<< HEAD
int ret = 0 ;
=======
int ret ;
>>>>>>> cyassl/master
#if defined(CYASSL_KEIL_TCP_NET)
while(1) {
@ -186,43 +170,6 @@ int Cyassl_tcp_select(int sd, int timeout)
}
#endif
<<<<<<< HEAD
=======
struct tm *Cyassl_MDK_gmtime(const time_t *c)
{
RTC_TimeTypeDef RTC_Time ;
RTC_DateTypeDef RTC_Date ;
static struct tm date ;
RTC_GetTime(RTC_Format_BIN, &RTC_Time) ;
RTC_GetDate(RTC_Format_BIN, &RTC_Date) ;
date.tm_year = RTC_Date.RTC_Year + 100 ;
date.tm_mon = RTC_Date.RTC_Month - 1 ;
date.tm_mday = RTC_Date.RTC_Date ;
date.tm_hour = RTC_Time.RTC_Hours ;
date.tm_min = RTC_Time.RTC_Minutes ;
date.tm_sec = RTC_Time.RTC_Seconds ;
#if defined(DEBUG_CYASSL)
{
char msg[100] ;
sprintf(msg, "Debug::Cyassl_KEIL_gmtime(DATE=/%4d/%02d/%02d TIME=%02d:%02d:%02d)\n",
RTC_Date.RTC_Year+2000, RTC_Date.RTC_Month, RTC_Date.RTC_Date,
RTC_Time.RTC_Hours, RTC_Time.RTC_Minutes, RTC_Time.RTC_Seconds) ;
CYASSL_MSG(msg) ;
}
#endif
return(&date) ;
}
double current_time()
{
return ((double)TIM2->CNT/1000000.0) ;
}
>>>>>>> cyassl/master
extern int getkey(void) ;
extern int sendchar(int c) ;

10
IDE/MDK-ARM/MDK-ARM/CyaSSL/cyassl_MDK_ARM.h
View File

@ -95,19 +95,9 @@ extern int setsockopt(int sockfd, int level, int optname,
extern int select(int nfds, fd_set *readfds, fd_set *writefds,
fd_set *exceptfds, const struct timeval *timeout);
<<<<<<< HEAD
/* CyaSSL MDK-ARM time functions */
#include <time.h>
struct tm *Cyassl_MDK_gmtime(const time_t *c) ;
=======
/** KEIL-RL gmtime ****/
#include <time.h>
#include "stm32f2xx_rtc.h"
extern struct tm *gmtime(const time_t *timer);
extern struct tm *Cyassl_MDK_gmtime(const time_t *timer);
>>>>>>> cyassl/master
extern double current_time(void) ;
#endif /* CYASSL_KEIL_RL_H */

102
IDE/MDK-ARM/MDK-ARM/CyaSSL/main.c
View File

@ -30,13 +30,6 @@
#include <stdio.h>
#include "cyassl_MDK_ARM.h"
<<<<<<< HEAD
=======
#include "stm32f2xx_tim.h"
#include "stm32f2xx_rcc.h"
>>>>>>> cyassl/master
/*-----------------------------------------------------------------------------
* Initialize a Flash Memory Card
*----------------------------------------------------------------------------*/
@ -90,80 +83,6 @@ __task void tcp_poll (void)
}
#endif
<<<<<<< HEAD
=======
/*-----------------------------------------------------------------------------
* initialize RTC
*----------------------------------------------------------------------------*/
#include "stm32f2xx_rtc.h"
#include "stm32f2xx_rcc.h"
#include "stm32f2xx_pwr.h"
static init_RTC()
{
RTC_InitTypeDef RTC_InitStruct ;
RTC_TimeTypeDef RTC_Time ;
RTC_DateTypeDef RTC_Date ;
/* Enable the PWR clock */
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
/* Allow access to RTC */
PWR_BackupAccessCmd(ENABLE);
/***Configures the External Low Speed oscillator (LSE)****/
RCC_LSEConfig(RCC_LSE_ON);
/* Wait till LSE is ready */
while(RCC_GetFlagStatus(RCC_FLAG_LSERDY) == RESET)
{
}
/* Select the RTC Clock Source */
RCC_RTCCLKConfig(RCC_RTCCLKSource_LSE);
/* Enable the RTC Clock */
RCC_RTCCLKCmd(ENABLE);
/* Wait for RTC APB registers synchronisation */
RTC_WaitForSynchro();
/* Calendar Configuration with LSI supposed at 32KHz */
RTC_InitStruct.RTC_AsynchPrediv = 0x7F;
RTC_InitStruct.RTC_SynchPrediv = 0xFF;
RTC_InitStruct.RTC_HourFormat = RTC_HourFormat_24;
RTC_Init(&RTC_InitStruct);
RTC_GetTime(RTC_Format_BIN, &RTC_Time) ;
RTC_GetDate(RTC_Format_BIN, &RTC_Date) ;
}
/*-----------------------------------------------------------------------------
* initialize TIM
*----------------------------------------------------------------------------*/
void init_timer()
{
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure ;
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE) ;
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
TIM_TimeBaseStructure.TIM_Prescaler = 60;
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseStructure.TIM_Period = 0xffffffff;
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
TIM_TimeBaseStructure.TIM_RepetitionCounter = 0;
TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure);
TIM_TimeBaseInit(TIM2, &TIM_TimeBaseStructure) ;
TIM_Cmd(TIM2, ENABLE) ;
}
>>>>>>> cyassl/master
#if defined(HAVE_KEIL_RTX) && defined(CYASSL_MDK_SHELL)
#define SHELL_STACKSIZE 1000
static unsigned char Shell_stack[SHELL_STACKSIZE] ;
@ -199,20 +118,12 @@ void main_task (void)
shell_main() ;
#endif
#else
<<<<<<< HEAD
/************************************/
/*** USER APPLICATION HERE ***/
/************************************/
printf("USER LOGIC STARTED\n") ;
=======
/************************************/
/*** USER APPLICATION HERE ***/
/************************************/
>>>>>>> cyassl/master
#endif
#ifdef HAVE_KEIL_RTX
@ -232,7 +143,6 @@ void main_task (void)
/*** main entry ***/
<<<<<<< HEAD
extern void init_time(void) ;
extern void SystemInit(void);
@ -246,18 +156,6 @@ int main() {
init_time() ;
=======
int main() {
/* stm32_Init (); STM32 setup */
#if !defined(NO_FILESYSTEM)
init_card () ; /* initializing SD card */
#endif
init_RTC() ;
init_timer() ;
SER_Init() ;
>>>>>>> cyassl/master
#if defined(DEBUG_CYASSL)
printf("Turning ON Debug message\n") ;

36
IDE/MDK-ARM/MDK-ARM/CyaSSL/shell.c
View File

@ -384,42 +384,6 @@ static void ipaddr_comm(void *args)
#endif
<<<<<<< HEAD
=======
static void time_main(void *args)
{
char * datetime ;
RTC_TimeTypeDef RTC_Time ;
RTC_DateTypeDef RTC_Date ;
int year ;
if( args == NULL || ((func_args *)args)->argc == 1) {
RTC_GetTime(RTC_Format_BIN, &RTC_Time) ;
RTC_GetDate(RTC_Format_BIN, &RTC_Date) ;
printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n",
RTC_Date.RTC_Month, RTC_Date.RTC_Date, RTC_Date.RTC_Year+2000,
RTC_Time.RTC_Hours, RTC_Time.RTC_Minutes, RTC_Time.RTC_Seconds) ;
} else if(((func_args *)args)->argc == 3 &&
((func_args *)args)->argv[1][0] == '-' &&
((func_args *)args)->argv[1][1] == 'd' ) {
datetime = ((func_args *)args)->argv[2];
sscanf(datetime, "%d/%d/%d",
(int *)&RTC_Date.RTC_Month, (int *)&RTC_Date.RTC_Date, &year) ;
RTC_Date.RTC_Year = year - 2000 ;
RTC_Date.RTC_WeekDay = 0 ;
RTC_SetDate(RTC_Format_BIN, &RTC_Date) ;
} else if(((func_args *)args)->argc == 3 &&
((func_args *)args)->argv[1][0] == '-' &&
((func_args *)args)->argv[1][1] == 't' ) {
datetime = ((func_args *)args)->argv[2];
sscanf(datetime, "%d:%d:%d",
(int *)&RTC_Time.RTC_Hours,
(int *)&RTC_Time.RTC_Minutes,
(int *)&RTC_Time.RTC_Seconds
) ;
RTC_SetTime(RTC_Format_BIN, &RTC_Time) ;
} else printf("Invalid argument\n") ;
}
>>>>>>> cyassl/master
#if defined(HAVE_KEIL_RTX)

9
IDE/MDK-ARM/MDK-ARM/CyaSSL/ssl-dummy.c
View File

@ -45,18 +45,9 @@ int CyaSSL_get_using_nonblock(CYASSL* ssl)
CYASSL_LEAVE("CyaSSL_get_using_nonblock", ssl->options.usingNonblock);
return ssl->options.usingNonblock;
}
<<<<<<< HEAD
Signer* GetCAByName(void* vp, byte* hash)
{
Signer * ca ;
return(ca) ;
}
=======
Signer* GetCAByName(void* vp, byte* hash)
{
return NULL;
}
>>>>>>> cyassl/master

390
IDE/MDK-ARM/MDK-ARM/config/File_Config.c
View File

@ -1,4 +1,3 @@
<<<<<<< HEAD
/*----------------------------------------------------------------------------
* RL-ARM - FlashFS
*----------------------------------------------------------------------------
@ -400,392 +399,3 @@
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/
=======
/*----------------------------------------------------------------------------
* RL-ARM - FlashFS
*----------------------------------------------------------------------------
* Name: FILE_CONFIG.C
* Purpose: Configuration of RL FlashFS by user
* Rev.: V4.50
*----------------------------------------------------------------------------
* This code is part of the RealView Run-Time Library.
* Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved.
*---------------------------------------------------------------------------*/
#include <File_Config.h>
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
//
// <h>File System
// ==============
// <i> Define File System global parameters
// <o>Number of open files <4-16>
// <i>Define number of files that can be
// <i>opened at the same time.
// <i>Default: 8
#define N_FILES 6
// <o>CPU Clock Frequency [Hz]<0-1000000000>
// <i>Define the CPU Clock frequency used for
// <i>flash programming and erasing.
#define CPU_CLK 120000000
// </h>
// <e>Flash Drive
// ==============
// <i>Enable Embedded Flash Drive [F:]
#define FL0_EN 0
// <o>Base address <0x0-0xFFFFF000:0x1000>
// <i>Define the target device Base address
// <i>Default: 0x80000000
#define FL0_BADR 0x80000000
// <o>Device Size <0x4000-0xFFFFF000:0x4000>
// <i>Define the size of Flash device in bytes
// <i>Default: 0x100000 (1MB)
#define FL0_SIZE 0x0200000
// <o>Content of Erased Memory <0=>0x00 <0xFF=>0xFF
// <i>Define the initial value for erased Flash data
// <i>Default: 0xFF
#define FL0_INITV 0xFF
// <s.80>Device Description file
// <i>Specify a file name with a relative path
// <i>Default: FS_FlashDev.h
#define FL0_HFILE "FS_FlashDev.h"
// <q>Default Drive [F:]
// <i>Used when Drive letter not specified
#define FL0_DEF 1
// </e>
// <e>SPI Flash Drive
// ==================
// <i>Enable SPI Flash Drive [S:]
#define SF0_EN 0
// <o>Device Size <0x10000-0xFFFFF000:0x8000>
// <i>Define the size of SPI Flash device in bytes
// <i>Default: 0x100000 (1MB)
#define SF0_SIZE 0x0200000
// <o>Content of Erased Memory <0=>0x00 <0xFF=>0xFF
// <i>Define the initial value for erased Flash data
// <i>Default: 0xFF
#define SF0_INITV 0xFF
// <s.80>Device Description file
// <i>Specify a file name with a relative path
// <i>Default: FS_SPI_FlashDev.h
#define SF0_HFILE "FS_SPI_FlashDev.h"
// <q>Default Drive [S:]
// <i>Used when Drive letter not specified
#define SF0_DEF 0
// </e>
// <e>RAM Drive
// ============
// <i>Enable Embedded RAM Drive [R:]
#define RAM0_EN 0
// <o>Device Size <0x4000-0xFFFFF000:0x4000>
// <i>Define the size of RAM device in bytes
// <i>Default: 0x40000
#define RAM0_SIZE 0x004000
// <o>Number of Sectors <8=>8 <16=>16 <32=>32 <64=>64 <128=>128
// <i>Define number of virtual sectors for RAM device
// <i>Default: 32
#define RAM0_NSECT 64
// <e>Relocate Device Buffer
// <i>Locate RAM Device Buffer at a specific address.
// <i>If not enabled, the linker selects base address.
#define RAM0_RELOC 1
// <o>Base address <0x0-0xFFFFF000:0x1000>
// <i>Define the target device Base address.
// <i>Default: 0x81000000
#define RAM0_BADR 0x81010000
// </e>
// <q>Default Drive [R:]
// <i>Used when Drive letter not specified
#define RAM0_DEF 0
// </e>
// <e>Memory Card Drive 0
// ======================
// <i>Enable Memory Card Drive [M0:]
#define MC0_EN 1
// <o>Bus Mode <0=>SD-Native <1=>SPI
// <i>Define Memory Card bus interface mode.
// <i>SD-Native mode needs MCI peripheral.
// <i>SPI mode uses SD Card in SPI mode.
#define MC0_SPI 0
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Define System Cache buffer size for file IO.
// <i>Increase this number for faster r/w access.
// <i>Default: 4 kB
#define MC0_CASZ 16
// <e>Relocate Cache Buffer
// <i>Locate Cache Buffer at a specific address.
// <i>Some devices like NXP LPC23xx require a Cache buffer
// <i>for DMA transfer located at specific address.
#define MC0_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define the Cache buffer base address.
// <i>For LPC23xx/24xx devices this is USB RAM
// <i>starting at 0x7FD00000.
#define MC0_CADR 0x7FD00000
// </e>
// <q>FAT Journal
// <i>Enable FAT Journal in order to guarantee
// <i>fail-safe FAT file system operation.
#define MC0_FSJ 0
// <q>Default Drive [M0:]
// <i>Used when Drive letter not specified
#define MC0_DEF 1
// </e>
// <e>Memory Card Drive 1
// ======================
// <i>Enable Memory Card Drive [M1:]
#define MC1_EN 0
// <o>Bus Mode <0=>SD-Native <1=>SPI
// <i>Define Memory Card bus interface mode.
// <i>SD-Native mode needs MCI peripheral.
// <i>SPI mode uses SD Card in SPI mode.
#define MC1_SPI 1
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Define System Cache buffer size for file IO.
// <i>Increase this number for faster r/w access.
// <i>Default: 4 kB
#define MC1_CASZ 0
// <e>Relocate Cache Buffer
// <i>Locate Cache Buffer at a specific address.
// <i>Some devices like NXP LPC23xx require a Cache buffer
// <i>for DMA transfer located at specific address.
#define MC1_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define the Cache buffer base address.
// <i>For LPC23xx/24xx devices this is USB RAM
// <i>starting at 0x7FD00000.
#define MC1_CADR 0x7FD00000
// </e>
// <q>FAT Journal
// <i>Enable FAT Journal in order to guarantee
// <i>fail-safe FAT file system operation.
#define MC1_FSJ 0
// <q>Default Drive [M1:]
// <i>Used when Drive letter not specified
#define MC1_DEF 0
// </e>
// <e>USB Flash Drive 0
// ====================
// <i>Enable USB Flash Drive [U0:]
#define USB0_EN 0
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Define System Cache buffer size for file IO.
// <i>Increase this number for faster r/w access.
// <i>Default: 4 kB
#define USB0_CASZ 8
// <q>FAT Journal
// <i>Enable FAT Journal in order to guarantee
// <i>fail-safe FAT file system operation.
#define USB0_FSJ 0
// <q>Default Drive [U0:]
// <i>Used when Drive letter not specified
#define USB0_DEF 1
// </e>
// <e>USB Flash Drive 1
// ====================
// <i>Enable USB Flash Drive [U1:]
#define USB1_EN 0
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Define System Cache buffer size for file IO.
// <i>Increase this number for faster r/w access.
// <i>Default: 4 kB
#define USB1_CASZ 8
// <q>FAT Journal
// <i>Enable FAT Journal in order to guarantee
// <i>fail-safe FAT file system operation.
#define USB1_FSJ 0
// <q>Default Drive [U1:]
// <i>Used when Drive letter not specified
#define USB1_DEF 1
// </e>
// <e>NAND Flash Drive 0
// ===================
// <i>Enable NAND Flash Drive [N0:]
#define NAND0_EN 0
// <o>Page size <528=> 512 + 16 bytes
// <2112=>2048 + 64 bytes
// <4224=>4096 + 128 bytes
// <8448=>8192 + 256 bytes
// <i>Define program Page size in bytes (User + Spare area).
#define NAND0_PGSZ 2112
// <o>Block Size <8=>8 pages <16=>16 pages <32=>32 pages
// <64=>64 pages <128=>128 pages <256=>256 pages
// <i>Define number of pages in a block.
#define NAND0_PGCNT 64
// <o>Device Size [blocks] <512-32768>
// <i>Define number of blocks in NAND Flash device.
#define NAND0_BLCNT 4096
// <o>Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
// <8=>8 pages <16=>16 pages <32=>32 pages
// <i>Define number of cached Pages.
// <i>Default: 4 pages
#define NAND0_CAPG 2
// <o>Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
// <8=>8 blocks <16=>16 blocks <32=>32 blocks
// <64=>64 blocks <128=>128 blocks <256=>256 blocks
// <i>Define number of indexed Flash Blocks.
// <i>Increase this number for better performance.
// <i>Default: 16 blocks
#define NAND0_CABL 16
// <o>Software ECC <0=>None <1=>Hamming (SLC)
// <i>Enable software ECC calculation only,
// <i>if not supported by hardware.
#define NAND0_SWECC 1
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Define System Cache buffer size for file IO.
// <i>Increase this number for faster r/w access.
// <i>Default: 4 kB
#define NAND0_CASZ 4
// <e>Relocate Cache Buffers
// <i>Use this option to locate Cache buffers
// <i>at specific address in RAM or SDRAM.
#define NAND0_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define base address for Cache Buffers.
#define NAND0_CADR 0x80000000
// </e>
// <q>FAT Journal
// <i>Enable FAT Journal in order to guarantee
// <i>fail-safe FAT file system operation.
#define NAND0_FSJ 0
// <q>Default Drive [N0:]
// <i>Used when Drive letter not specified
#define NAND0_DEF 0
// </e>
// <e>NAND Flash Drive 1
// ===================
// <i>Enable NAND Flash Drive [N1:]
#define NAND1_EN 0
// <o>Page size <528=> 512 + 16 bytes
// <2112=>2048 + 64 bytes
// <4224=>4096 + 128 bytes
// <8448=>8192 + 256 bytes
// <i>Define program Page size in bytes (User + Spare area).
#define NAND1_PGSZ 2112
// <o>Block Size <8=>8 pages <16=>16 pages <32=>32 pages
// <64=>64 pages <128=>128 pages <256=>256 pages
// <i>Define number of pages in a block.
#define NAND1_PGCNT 32
// <o>Device Size [blocks] <512-32768>
// <i>Define number of blocks in NAND Flash device.
#define NAND1_BLCNT 512
// <o>Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
// <8=>8 pages <16=>16 pages <32=>32 pages
// <i>Define number of cached Pages.
// <i>Default: 4 pages
#define NAND1_CAPG 4
// <o>Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
// <8=>8 blocks <16=>16 blocks <32=>32 blocks
// <64=>64 blocks <128=>128 blocks <256=>256 blocks
// <i>Define number of indexed Flash Blocks.
// <i>Increase this number for better performance.
// <i>Default: 16 blocks
#define NAND1_CABL 16
// <o>Software ECC <0=>None <1=>Hamming (SLC)
// <i>Enable software ECC calculation only,
// <i>if not supported by hardware.
#define NAND1_SWECC 0
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Define System Cache buffer size for file IO.
// <i>Increase this number for faster r/w access.
// <i>Default: 4 kB
#define NAND1_CASZ 4
// <e>Relocate Cache Buffers
// <i>Use this option to locate Cache buffers
// <i>at specific address in RAM or SDRAM.
#define NAND1_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define base address for Cache Buffers.
#define NAND1_CADR 0x80000000
// </e>
// <q>FAT Journal
// <i>Enable FAT Journal in order to guarantee
// <i>fail-safe FAT file system operation.
#define NAND1_FSJ 0
// <q>Default Drive [N1:]
// <i>Used when Drive letter not specified
#define NAND1_DEF 0
// </e>
//------------- <<< end of configuration section >>> -----------------------
#ifndef __NO_FILE_LIB_C
#include <File_lib.c>
#endif
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/
>>>>>>> cyassl/master

4
IDE/MDK-ARM/MDK-ARM/config/RTX_Conf_CM.c
View File

@ -39,11 +39,7 @@
// <i> Set the stack size for tasks which is assigned by the system.
// <i> Default: 512
#ifndef OS_STKSIZE
<<<<<<< HEAD
#define OS_STKSIZE 499
=======
#define OS_STKSIZE 250
>>>>>>> cyassl/master
#endif
// <q>Check for the stack overflow