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Fixes for STM32 hardware acceleration. Adds CubeMX HAL hashing support for MD5, SHA1, SHA224 and SHA256. Adds support for STM32F7 (WOLFSSL_STM32F7). Fixes issue with AES-GCM and STM32F2. Cleanup of the STM32 macros (adds NO_STM32_HASH, NO_STM32_CRYPTO and NO_STM32_RNG to optionally disable hardware acceleration).

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This commit is contained in:
David Garske 2017-08-24 12:06:42 -07:00
parent 0b11b265f6
commit dcab2f47ee
14 changed files with 678 additions and 270 deletions
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106
IDE/MDK-ARM/STM32F2xx_StdPeriph_Lib/time-STM32F2xx.c
View File

@ -1,4 +1,4 @@
/* main.c
/* time-STM32F2xx.c
*
* Copyright (C) 2006-2016 wolfSSL Inc.
*
@ -19,16 +19,16 @@
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
*/
#ifdef HAVE_CONFIG_H
#include <config.h>
#endif
#include "time.h"
#define PERIPH_BASE ((uint32_t)0x40000000)
#define PERIPH_BASE ((uint32_t)0x40000000)
/*-----------------------------------------------------------------------------
* initialize RTC
* initialize RTC
*----------------------------------------------------------------------------*/
#include "stm32f2xx.h"
@ -46,15 +46,15 @@
#define CR_OFFSET (PWR_OFFSET + 0x00)
#define DBP_BitNumber 0x08
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
#define INITMODE_TIMEOUT ((uint32_t) 0x00010000)
static void init_RTC()
static void init_RTC()
{
__IO uint32_t initcounter = 0x00 ;
uint32_t initstatus = 0x00; /* Enable the PWR clock : RCC_APB1Periph_PWR */
uint32_t initstatus = 0x00; /* Enable the PWR clock : RCC_APB1Periph_PWR */
((uint32_t *)RCC)[0x10] |= ((uint32_t)0x10000000) ;
/* Allow access to RTC */
*(__IO uint32_t *) CR_DBP_BB = ENABLE ;
/* RCC_LSEConfig(RCC_LSE_ON) */
@ -62,7 +62,7 @@ static void init_RTC()
/* Reset LSEBYP bit */
*(__IO uint8_t *) (RCC_BASE + 0x70) = ((uint8_t)0x00);
*(__IO uint8_t *) (RCC_BASE + 0x70) = ((uint8_t)0x01);
/* Wait till LSE is ready */
/* Wait till LSE is ready */
while((RCC->BDCR << 0x2) == 0x0) { }
/* Select the RTC clock source: RCC_RTCCLKSource_LSE */
((RCC_TypeDef *)RCC)->BDCR |= (uint32_t)0x00000100;
@ -70,13 +70,13 @@ static void init_RTC()
/* Enable the RTC Clock */
*(__IO uint32_t *) (PERIPH_BB_BASE + (((RCC_BASE - PERIPH_BASE)+ 0x70) * 32) + (0x0F* 4)) = (uint32_t)ENABLE;
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
RTC->ISR = (uint32_t) RTC_INIT_MASK;
do {
initstatus = RTC->ISR & RTC_ISR_INITF;
initcounter++;
initcounter++;
} while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
@ -86,14 +86,14 @@ static void init_RTC()
RTC->CR |= ((uint32_t)0x00000000) ; /* RTC_HourFormat_24 */
/* Configure the RTC PRER */
RTC->PRER = 0x7f ;
RTC->PRER = 0x7f ;
RTC->PRER |= (uint32_t)(0xff << 16);
/* Exit Initialization mode */
RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
/* Enable the write protection for RTC registers */
RTC->WPR = 0xFF;
RTC->WPR = 0xFF;
}
/*-----------------------------------------------------------------------------
@ -108,16 +108,16 @@ static void init_TIM()
((uint32_t *)RCC)[0x10] |= RCC_APB1Periph_TIM2 ;
tmpcr1 = TIM2->CR1 ;
tmpcr1 &= (uint16_t) (~(((uint16_t)0x0010) | ((uint16_t)0x0060) ));
tmpcr1 &= (uint16_t) (~(((uint16_t)0x0010) | ((uint16_t)0x0060) ));
/* CR1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS) */
tmpcr1 |= (uint16_t)0x0000 ; /* CR1 |= TIM_CounterMode_Up */
TIM2->CR1= tmpcr1 ;
TIM2->ARR = 0xffffffff ; /* ARR= TIM_Period */
TIM2->PSC = 60 ; /* PSC = TIM_Prescaler */
TIM2->EGR = ((uint16_t)0x0001) ; /* EGR = TIM_PSCReloadMode_Immediate */
TIM2->EGR = ((uint16_t)0x0001) ; /* EGR = TIM_PSCReloadMode_Immediate */
*(uint16_t *)(PERIPH_BASE+0x0) |=((uint16_t)0x0001) ;
*(uint16_t *)(PERIPH_BASE+0x0) |=((uint16_t)0x0001) ;
/* TIM_Cmd(TIM2, ENABLE) ; */
}
@ -129,10 +129,10 @@ void init_time(void) {
static void GetTime(uint8_t *h, uint8_t *m, uint8_t *s)
{
uint32_t tmpreg = 0;
tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
*h = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16));
*m = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8));
*s = (uint8_t)Bcd2ToByte((tmpreg & (RTC_TR_ST | RTC_TR_SU)));
*s = (uint8_t)Bcd2ToByte((tmpreg & (RTC_TR_ST | RTC_TR_SU)));
}
static uint32_t ByteToBcd2(uint8_t Value)
@ -151,29 +151,29 @@ static void SetTime(uint8_t h, uint8_t m, uint8_t s)
uint32_t synchrostatus = 0x00;
__IO uint32_t initcounter = 0;
uint32_t initstatus = 0x00;
uint32_t tmpreg ;
uint32_t tmpreg ;
tmpreg = ((ByteToBcd2(h) << 16) | (ByteToBcd2(m) << 8) | ByteToBcd2(s)) ;
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
RTC->ISR = (uint32_t)RTC_INIT_MASK;
/* Wait till RTC is in INIT state and if Time out is reached exit */
do {
initstatus = RTC->ISR & RTC_ISR_INITF;
initcounter++;
initcounter++;
} while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
RTC->ISR &= (uint32_t)RTC_RSF_MASK;
/* Wait the registers to be synchronised */
do {
synchrostatus = RTC->ISR & RTC_ISR_RSF;
synchrocounter++;
synchrocounter++;
} while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
RTC->WPR = 0xFF;
@ -182,7 +182,7 @@ static void SetTime(uint8_t h, uint8_t m, uint8_t s)
static void GetDate(uint8_t *y, uint8_t *m, uint8_t *d)
{
uint32_t tmpreg = 0;
tmpreg = (uint32_t)(RTC->DR & RTC_TR_RESERVED_MASK);
tmpreg = (uint32_t)(RTC->DR & RTC_TR_RESERVED_MASK);
*y = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_DR_YT|RTC_DR_YU)) >>16));
*m = (uint8_t)Bcd2ToByte((uint8_t)((tmpreg & (RTC_DR_MT|RTC_DR_MU)) >> 8));
*d = (uint8_t)Bcd2ToByte((uint8_t)(tmpreg & (RTC_DR_DT |RTC_DR_DU)));
@ -194,20 +194,20 @@ static void SetDate(uint8_t y, uint8_t m, uint8_t d)
uint32_t synchrostatus = 0x00;
__IO uint32_t initcounter = 0;
uint32_t initstatus = 0x00;
uint32_t tmpreg = 0 ;
uint32_t tmpreg = 0 ;
tmpreg = ((ByteToBcd2(y) << 16) | (ByteToBcd2(m) << 8) | ByteToBcd2(d)) ;
/* Disable the write protection for RTC registers */
RTC->WPR = 0xCA;
RTC->WPR = 0x53;
RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
RTC->ISR = (uint32_t)RTC_INIT_MASK;
/* Wait till RTC is in INIT state and if Time out is reached exit */
do {
initstatus = RTC->ISR & RTC_ISR_INITF;
initcounter++;
initcounter++;
} while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
RTC->DR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
@ -216,7 +216,7 @@ static void SetDate(uint8_t y, uint8_t m, uint8_t d)
/* Wait the registers to be synchronised */
do {
synchrostatus = RTC->ISR & RTC_ISR_RSF;
synchrocounter++;
synchrocounter++;
} while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
RTC->WPR = 0xFF;
@ -226,11 +226,11 @@ static void SetDate(uint8_t y, uint8_t m, uint8_t d)
#include <stdio.h>
void CYASSL_MSG(const char *msg) ;
struct tm *Cyassl_MDK_gmtime(const time_t *c)
{
struct tm *Cyassl_MDK_gmtime(const time_t *c)
{
uint8_t h, m, s ;
uint8_t y, mo, d ;
static struct tm date ;
static struct tm date ;
GetTime(&h, &m, &s) ;
GetDate(&y, &mo, &d) ;
@ -242,20 +242,20 @@ struct tm *Cyassl_MDK_gmtime(const time_t *c)
date.tm_min = m ;
date.tm_sec = s ;
#if defined(DEBUG_CYASSL)
#if defined(DEBUG_CYASSL)
{
char msg[100] ;
sprintf(msg,
sprintf(msg,
"Debug::Cyassl_KEIL_gmtime(DATE=/%2d/%02d/%04d TIME=%02d:%02d:%02d)\n",
d, mo, y+2000, h, m, s) ;
CYASSL_MSG(msg) ;
d, mo, y+2000, h, m, s) ;
CYASSL_MSG(msg) ;
}
#endif
return(&date) ;
}
double current_time()
double current_time()
{
return ((double)TIM2->CNT/1000000.0) ;
}
@ -266,35 +266,35 @@ typedef struct func_args {
int return_code;
} func_args;
void time_main(void *args)
void time_main(void *args)
{
char * datetime ;
uint8_t h, m, s ;
uint8_t y, mo, d ;
if( args == NULL || ((func_args *)args)->argc == 1) {
GetTime(&h, &m, &s) ;
GetDate(&y, &mo, &d) ;
printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n",
mo, d, y+2000, h, m, s) ;
} else if(((func_args *)args)->argc == 3 &&
((func_args *)args)->argv[1][0] == '-' &&
printf("Date: %d/%d/%d, Time: %02d:%02d:%02d\n",
mo, d, y+2000, h, m, s) ;
} else if(((func_args *)args)->argc == 3 &&
((func_args *)args)->argv[1][0] == '-' &&
((func_args *)args)->argv[1][1] == 'd' ) {
datetime = ((func_args *)args)->argv[2];
sscanf(datetime, "%d/%d/%d", (int *)&mo, (int *)&d, (int *) &y) ;
SetDate(y-2000, mo, d) ;
} else if(((func_args *)args)->argc == 3 &&
((func_args *)args)->argv[1][0] == '-' &&
SetDate(y-2000, mo, d) ;
} else if(((func_args *)args)->argc == 3 &&
((func_args *)args)->argv[1][0] == '-' &&
((func_args *)args)->argv[1][1] == 't' ) {
datetime = ((func_args *)args)->argv[2];
sscanf(datetime, "%d:%d:%d",
sscanf(datetime, "%d:%d:%d",
(int *)&h, (int *)&m, (int *)&s) ;
SetTime(h, m, s) ;
} else printf("Invalid argument\n") ;
} else printf("Invalid argument\n") ;
}
/*******************************************************************
time()
time()
********************************************************************/
time_t time(time_t * t) { return 0 ; }

26
IDE/OPENSTM32/Inc/user_settings.h
View File

@ -25,6 +25,11 @@ extern "C" {
#undef WOLFSSL_STM32_CUBEMX
#define WOLFSSL_STM32_CUBEMX
/* Optionally Disable Hardware Hashing Support */
//#define NO_STM32_HASH
//#define NO_STM32_RNG
//#define NO_STM32_CRYPTO
#undef FREERTOS
//#define FREERTOS
@ -121,9 +126,9 @@ extern "C" {
#undef RSA_LOW_MEM
//#define RSA_LOW_MEM
/* Enables blinding mode, to prevent timing attacks */
#undef WC_RSA_BLINDING
#define WC_RSA_BLINDING
/* Enables blinding mode, to prevent timing attacks */
#undef WC_RSA_BLINDING
#define WC_RSA_BLINDING
#else
#define NO_RSA
@ -192,6 +197,9 @@ extern "C" {
/* Sha256 */
#undef NO_SHA256
#if 1
#if 1
#define WOLFSSL_SHA224
#endif
#else
#define NO_SHA256
#endif
@ -214,7 +222,7 @@ extern "C" {
/* MD5 */
#undef NO_MD5
#if 1
/* enabled */
/* enabled */
#else
#define NO_MD5
#endif
@ -282,23 +290,23 @@ extern "C" {
#define NO_OLD_RNGNAME
/* Choose RNG method */
#if 0
#if 1
/* Use built-in P-RNG (SHA256 based) with HW RNG */
/* P-RNG + HW RNG (P-RNG is ~8K) */
#undef HAVE_HASHDRBG
#define HAVE_HASHDRBG
extern unsigned int custom_rand_generate(void);
#undef CUSTOM_RAND_GENERATE
#define CUSTOM_RAND_GENERATE custom_rand_generate
#if 0
extern unsigned int custom_rand_generate(void);
#undef CUSTOM_RAND_GENERATE
#define CUSTOM_RAND_GENERATE custom_rand_generate
#endif
#else
/* Bypass P-RNG and use only HW RNG */
extern int custom_rand_generate_block(unsigned char* output, unsigned int sz);
#undef CUSTOM_RAND_GENERATE_BLOCK
#define CUSTOM_RAND_GENERATE_BLOCK custom_rand_generate_block
#endif
#endif
/* ------------------------------------------------------------------------- */

20
wolfcrypt/src/aes.c
View File

@ -256,7 +256,7 @@
/* Define AES implementation includes and functions */
#if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
#if defined(STM32_CRYPTO)
/* STM32F2/F4 hardware AES support for CBC, CTR modes */
/* CRYPT_AES_GCM starts the IV with 2 */
@ -1782,7 +1782,7 @@ static void wc_AesDecrypt(Aes* aes, const byte* inBlock, byte* outBlock)
/* wc_AesSetKey */
#if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
#if defined(STM32_CRYPTO)
int wc_AesSetKey(Aes* aes, const byte* userKey, word32 keylen,
const byte* iv, int dir)
@ -2253,7 +2253,7 @@ int wc_AesSetIV(Aes* aes, const byte* iv)
/* AES-CBC */
#ifdef HAVE_AES_CBC
#if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
#if defined(STM32_CRYPTO)
#ifdef WOLFSSL_STM32_CUBEMX
int wc_AesCbcEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
@ -3000,8 +3000,8 @@ int wc_AesEcbDecrypt(Aes* aes, byte* out, const byte* in, word32 sz)
#endif
/* AES-CTR */
#if defined(WOLFSSL_AES_COUNTER) || (defined(HAVE_AESGCM_DECRYPT) && defined(STM32F4_CRYPTO))
#if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
#if defined(WOLFSSL_AES_COUNTER) || (defined(HAVE_AESGCM_DECRYPT) && defined(STM32_CRYPTO))
#ifdef STM32_CRYPTO
#ifdef WOLFSSL_STM32_CUBEMX
int wc_AesCtrEncrypt(Aes* aes, byte* out, const byte* in, word32 sz)
{
@ -6933,7 +6933,7 @@ int wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
byte initialCounter[AES_BLOCK_SIZE];
byte *ctr;
byte scratch[AES_BLOCK_SIZE];
#if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
#if defined(STM32_CRYPTO) && (defined(WOLFSSL_STM32F4) || defined(WOLFSSL_STM32F7))
#ifdef WOLFSSL_STM32_CUBEMX
CRYP_HandleTypeDef hcryp;
#else
@ -6943,7 +6943,7 @@ int wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
byte* authInPadded = NULL;
byte tag[AES_BLOCK_SIZE];
int authPadSz;
#endif /* STM32F2_CRYPTO || STM32F4_CRYPTO */
#endif /* STM32_CRYPTO */
#endif /* FREESCALE_LTC_AES_GCM */
/* argument checks */
@ -6969,7 +6969,7 @@ int wc_AesGcmEncrypt(Aes* aes, byte* out, const byte* in, word32 sz,
#else
#if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
#if defined(WOLFSSL_STM32F4) || defined(WOLFSSL_STM32F7)
/* additional argument checks - STM32 HW only supports 12 byte IV */
if (ivSz != NONCE_SZ) {
@ -7173,7 +7173,7 @@ int wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
word32 keySize;
#ifdef FREESCALE_LTC_AES_GCM
status_t status;
#elif defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
#elif defined(STM32_CRYPTO) && (defined(WOLFSSL_STM32F4) || defined(WOLFSSL_STM32F7))
#ifdef WOLFSSL_STM32_CUBEMX
CRYP_HandleTypeDef hcryp;
#else
@ -7216,7 +7216,7 @@ int wc_AesGcmDecrypt(Aes* aes, byte* out, const byte* in, word32 sz,
ret = (status == kStatus_Success) ? 0 : AES_GCM_AUTH_E;
#elif defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
#elif defined(STM32_CRYPTO) && (defined(WOLFSSL_STM32F4) || defined(WOLFSSL_STM32F7))
/* additional argument checks - STM32 HW only supports 12 byte IV */
if (ivSz != NONCE_SZ) {

2
wolfcrypt/src/des3.c
View File

@ -124,7 +124,7 @@
/* Hardware Acceleration */
#if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
#if defined(STM32_CRYPTO)
/*
* STM32F2/F4 hardware DES/3DES support through the standard

161
wolfcrypt/src/md5.c
View File

@ -46,100 +46,133 @@
#endif
static INLINE void AddLength(Md5* md5, word32 len);
/* Hardware Acceleration */
#if defined(STM32F2_HASH) || defined(STM32F4_HASH)
#if defined(STM32_HASH)
/*
* STM32F2/F4 hardware MD5 support through the standard peripheral
* library. (See note in README).
* STM32F2/F4/F7 hardware MD5 support through the HASH_* API's from the
* Standard Peripheral Library or CubeMX (See note in README).
*/
#define HAVE_MD5_CUST_API
int wc_InitMd5_ex(Md5* md5, void* heap, int devId)
{
(void)heap;
(void)devId;
#define HAVE_MD5_CUST_API
/* STM32 register size, bytes */
#ifdef WOLFSSL_STM32_CUBEMX
#define MD5_REG_SIZE MD5_BLOCK_SIZE
#else
#define MD5_REG_SIZE 4
/* STM32 struct notes:
* md5->buffer = first 4 bytes used to hold partial block if needed
* md5->buffLen = num bytes currently stored in md5->buffer
* md5->loLen = num bytes that have been written to STM32 FIFO
*/
XMEMSET(md5->buffer, 0, MD5_REG_SIZE);
#endif
#define MD5_HW_TIMEOUT 0xFF
int wc_InitMd5_ex(Md5* md5, void* heap, int devId)
{
if (md5 == NULL)
return BAD_FUNC_ARG;
(void)heap;
(void)devId;
md5->heap = heap;
XMEMSET(md5->buffer, 0, sizeof(md5->buffer));
md5->buffLen = 0;
md5->loLen = 0;
md5->hiLen = 0;
/* initialize HASH peripheral */
HASH_DeInit();
#ifdef WOLFSSL_STM32_CUBEMX
HAL_HASH_DeInit(&md5->hashHandle);
md5->hashHandle.Init.DataType = HASH_DATATYPE_8B;
if (HAL_HASH_Init(&md5->hashHandle) != HAL_OK) {
return ASYNC_INIT_E;
}
/* reset the hash control register */
/* required because Cube MX is not clearing algo bits */
HASH->CR &= ~HASH_CR_ALGO;
#else
HASH_DeInit();
/* configure algo used, algo mode, datatype */
/* reset the control register */
HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HASH
| HASH_DataType_8b);
/* reset HASH processor */
HASH->CR |= HASH_CR_INIT;
/* configure algo used, algo mode, datatype */
HASH->CR |= (HASH_AlgoSelection_MD5 | HASH_AlgoMode_HASH
| HASH_DataType_8b);
/* reset HASH processor */
HASH->CR |= HASH_CR_INIT;
#endif
return 0;
}
int wc_Md5Update(Md5* md5, const byte* data, word32 len)
{
word32 i = 0;
word32 fill = 0;
word32 diff = 0;
int ret = 0;
byte* local;
/* if saved partial block is available */
if (md5->buffLen > 0) {
fill = 4 - md5->buffLen;
if (md5 == NULL || (data == NULL && len > 0)) {
return BAD_FUNC_ARG;
}
/* if enough data to fill, fill and push to FIFO */
if (fill <= len) {
XMEMCPY((byte*)md5->buffer + md5->buffLen, data, fill);
HASH_DataIn(*(uint32_t*)md5->buffer);
/* do block size increments */
local = (byte*)md5->buffer;
data += fill;
len -= fill;
md5->loLen += 4;
/* check that internal buffLen is valid */
if (md5->buffLen >= MD5_REG_SIZE)
return BUFFER_E;
while (len) {
word32 add = min(len, MD5_REG_SIZE - md5->buffLen);
XMEMCPY(&local[md5->buffLen], data, add);
md5->buffLen += add;
data += add;
len -= add;
if (md5->buffLen == MD5_REG_SIZE) {
#ifdef WOLFSSL_STM32_CUBEMX
if (HAL_HASH_MD5_Accumulate(
&md5->hashHandle, local, MD5_REG_SIZE) != HAL_OK) {
ret = ASYNC_OP_E;
}
#else
HASH_DataIn(*(uint32_t*)local);
#endif
AddLength(md5, MD5_REG_SIZE);
md5->buffLen = 0;
} else {
/* append partial to existing stored block */
XMEMCPY((byte*)md5->buffer + md5->buffLen, data, len);
md5->buffLen += len;
return 0;
}
}
/* write input block in the IN FIFO */
for (i = 0; i < len; i += 4)
{
diff = len - i;
if (diff < 4) {
/* store incomplete last block, not yet in FIFO */
XMEMSET(md5->buffer, 0, MD5_REG_SIZE);
XMEMCPY((byte*)md5->buffer, data, diff);
md5->buffLen = diff;
} else {
HASH_DataIn(*(uint32_t*)data);
data+=4;
}
}
/* keep track of total data length thus far */
md5->loLen += (len - md5->buffLen);
return 0;
return ret;
}
int wc_Md5Final(Md5* md5, byte* hash)
{
int ret = 0;
if (md5 == NULL || hash == NULL)
return BAD_FUNC_ARG;
#ifdef WOLFSSL_STM32_CUBEMX
if (HAL_HASH_MD5_Start(&md5->hashHandle,
(byte*)md5->buffer, md5->buffLen,
(byte*)md5->digest, MD5_HW_TIMEOUT) != HAL_OK) {
ret = ASYNC_OP_E;
}
#else
__IO uint16_t nbvalidbitsdata = 0;
/* finish reading any trailing bytes into FIFO */
if (md5->buffLen > 0) {
HASH_DataIn(*(uint32_t*)md5->buffer);
md5->loLen += md5->buffLen;
HASH_DataIn(*(uint32_t*)md5->buffer);
AddLength(md5, md5->buffLen);
}
/* calculate number of valid bits in last word of input data */
@ -161,10 +194,13 @@
md5->digest[3] = HASH->HR[3];
ByteReverseWords(md5->digest, md5->digest, MD5_DIGEST_SIZE);
#endif /* WOLFSSL_STM32_CUBEMX */
XMEMCPY(hash, md5->digest, MD5_DIGEST_SIZE);
return wc_InitMd5(md5); /* reset state */
(void)wc_InitMd5(md5); /* reset state */
return ret;
}
#elif defined(FREESCALE_MMCAU_SHA)
@ -293,16 +329,17 @@
}
#endif /* NEED_SOFT_MD5 */
#ifndef HAVE_MD5_CUST_API
static INLINE void AddMd5Length(Md5* md5, word32 len)
#if !defined(HAVE_MD5_CUST_API) || defined(STM32_HASH)
static INLINE void AddLength(Md5* md5, word32 len)
{
word32 tmp = md5->loLen;
if ((md5->loLen += len) < tmp) {
md5->hiLen++; /* carry low to high */
}
}
#endif
#ifndef HAVE_MD5_CUST_API
static int _InitMd5(Md5* md5)
{
int ret = 0;
@ -378,7 +415,7 @@ int wc_Md5Update(Md5* md5, const byte* data, word32 len)
ByteReverseWords(md5->buffer, md5->buffer, MD5_BLOCK_SIZE);
#endif
XTRANSFORM(md5, local);
AddMd5Length(md5, MD5_BLOCK_SIZE);
AddLength(md5, MD5_BLOCK_SIZE);
md5->buffLen = 0;
}
}
@ -403,7 +440,7 @@ int wc_Md5Final(Md5* md5, byte* hash)
local = (byte*)md5->buffer;
AddMd5Length(md5, md5->buffLen); /* before adding pads */
AddLength(md5, md5->buffLen); /* before adding pads */
local[md5->buffLen++] = 0x80; /* add 1 */
/* pad with zeros */

6
wolfcrypt/src/random.c
View File

@ -1232,7 +1232,7 @@ int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
word32 *rnd32 = (word32 *)rnd;
word32 size = sz;
byte* op = output;
#if ((__PIC32_FEATURE_SET0 == 'E') && (__PIC32_FEATURE_SET1 == 'C'))
RNGNUMGEN1 = _CP0_GET_COUNT();
RNGPOLY1 = _CP0_GET_COUNT();
@ -1412,10 +1412,10 @@ int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)
#define USE_TEST_GENSEED
#endif /* FREESCALE_K70_RNGA */
#elif defined(STM32F2_RNG) || defined(STM32F4_RNG)
#elif defined(STM32_RNG)
/*
* wc_Generate a RNG seed using the hardware random number generator
* on the STM32F2/F4. */
* on the STM32F2/F4/F7. */
#ifdef WOLFSSL_STM32_CUBEMX
int wc_GenerateSeed(OS_Seed* os, byte* output, word32 sz)

153
wolfcrypt/src/sha.c
View File

@ -87,99 +87,134 @@
#include <wolfcrypt/src/misc.c>
#endif
static INLINE void AddLength(Sha* sha, word32 len);
/* Hardware Acceleration */
#if defined(WOLFSSL_PIC32MZ_HASH)
#include <wolfssl/wolfcrypt/port/pic32/pic32mz-crypt.h>
#elif defined(STM32F2_HASH) || defined(STM32F4_HASH)
#elif defined(STM32_HASH)
/*
* STM32F2/F4 hardware SHA1 support through the standard peripheral
* library. (See note in README).
* STM32F2/F4/F7 hardware SHA1 support through the HASH_* API's from the
* Standard Peripheral Library or CubeMX (See note in README).
*/
static int InitSha(Sha* sha)
{
/* STM32 register size, bytes */
#ifdef WOLFSSL_STM32_CUBEMX
#define SHA_REG_SIZE SHA_BLOCK_SIZE
#else
#define SHA_REG_SIZE 4
/* STM32 struct notes:
* sha->buffer = first 4 bytes used to hold partial block if needed
* sha->buffLen = num bytes currently stored in sha->buffer
* sha->loLen = num bytes that have been written to STM32 FIFO
*/
XMEMSET(sha->buffer, 0, SHA_REG_SIZE);
#endif
#define SHA_HW_TIMEOUT 0xFF
int wc_InitSha_ex(Sha* sha, void* heap, int devId)
{
if (sha == NULL)
return BAD_FUNC_ARG;
sha->heap = heap;
XMEMSET(sha->buffer, 0, sizeof(sha->buffer));
sha->buffLen = 0;
sha->loLen = 0;
sha->hiLen = 0;
/* initialize HASH peripheral */
#ifdef WOLFSSL_STM32_CUBEMX
HAL_HASH_DeInit(&sha->hashHandle);
sha->hashHandle.Init.DataType = HASH_DATATYPE_8B;
if (HAL_HASH_Init(&sha->hashHandle) != HAL_OK) {
return ASYNC_INIT_E;
}
/* reset the hash control register */
/* required because Cube MX is not clearing algo bits */
HASH->CR &= ~HASH_CR_ALGO;
#else
HASH_DeInit();
/* configure algo used, algo mode, datatype */
/* reset the hash control register */
HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
/* configure algo used, algo mode, datatype */
HASH->CR |= (HASH_AlgoSelection_SHA1 | HASH_AlgoMode_HASH
| HASH_DataType_8b);
| HASH_DataType_8b);
/* reset HASH processor */
HASH->CR |= HASH_CR_INIT;
#endif
return 0;
}
int wc_ShaUpdate(Sha* sha, const byte* data, word32 len)
{
word32 i = 0;
word32 fill = 0;
word32 diff = 0;
int ret = 0;
byte* local;
/* if saved partial block is available */
if (sha->buffLen) {
fill = 4 - sha->buffLen;
if (sha == NULL || (data == NULL && len > 0)) {
return BAD_FUNC_ARG;
}
/* if enough data to fill, fill and push to FIFO */
if (fill <= len) {
XMEMCPY((byte*)sha->buffer + sha->buffLen, data, fill);
HASH_DataIn(*(uint32_t*)sha->buffer);
/* do block size increments */
local = (byte*)sha->buffer;
data += fill;
len -= fill;
sha->loLen += 4;
/* check that internal buffLen is valid */
if (sha->buffLen >= SHA_REG_SIZE)
return BUFFER_E;
while (len) {
word32 add = min(len, SHA_REG_SIZE - sha->buffLen);
XMEMCPY(&local[sha->buffLen], data, add);
sha->buffLen += add;
data += add;
len -= add;
if (sha->buffLen == SHA_REG_SIZE) {
#ifdef WOLFSSL_STM32_CUBEMX
if (HAL_HASH_SHA1_Accumulate(
&sha->hashHandle, local, SHA_REG_SIZE) != HAL_OK) {
ret = ASYNC_OP_E;
}
#else
HASH_DataIn(*(uint32_t*)local);
#endif
AddLength(sha, SHA_REG_SIZE);
sha->buffLen = 0;
} else {
/* append partial to existing stored block */
XMEMCPY((byte*)sha->buffer + sha->buffLen, data, len);
sha->buffLen += len;
return 0;
}
}
/* write input block in the IN FIFO */
for(i = 0; i < len; i += 4)
{
diff = len - i;
if ( diff < 4) {
/* store incomplete last block, not yet in FIFO */
XMEMSET(sha->buffer, 0, SHA_REG_SIZE);
XMEMCPY((byte*)sha->buffer, data, diff);
sha->buffLen = diff;
} else {
HASH_DataIn(*(uint32_t*)data);
data+=4;
}
}
/* keep track of total data length thus far */
sha->loLen += (len - sha->buffLen);
return 0;
return ret;
}
int wc_ShaFinal(Sha* sha, byte* hash)
{
int ret = 0;
if (sha == NULL || hash == NULL)
return BAD_FUNC_ARG;
#ifdef WOLFSSL_STM32_CUBEMX
if (HAL_HASH_SHA1_Start(&sha->hashHandle,
(byte*)sha->buffer, sha->buffLen,
(byte*)sha->digest, SHA_HW_TIMEOUT) != HAL_OK) {
ret = ASYNC_OP_E;
}
HAL_HASH_DeInit(&sha->hashHandle);
#else
__IO uint16_t nbvalidbitsdata = 0;
/* finish reading any trailing bytes into FIFO */
if (sha->buffLen) {
if (sha->buffLen > 0) {
HASH_DataIn(*(uint32_t*)sha->buffer);
sha->loLen += sha->buffLen;
AddLength(sha, sha->buffLen);
}
/* calculate number of valid bits in last word of input data */
@ -202,10 +237,13 @@
sha->digest[4] = HASH->HR[4];
ByteReverseWords(sha->digest, sha->digest, SHA_DIGEST_SIZE);
#endif /* WOLFSSL_STM32_CUBEMX */
XMEMCPY(hash, sha->digest, SHA_DIGEST_SIZE);
return wc_InitSha(sha); /* reset state */
(void)wc_InitSha_ex(sha, sha->heap, INVALID_DEVID); /* reset state */
return ret;
}
@ -303,6 +341,16 @@
#endif /* End Hardware Acceleration */
#if defined(USE_SHA_SOFTWARE_IMPL) || defined(STM32_HASH)
static INLINE void AddLength(Sha* sha, word32 len)
{
word32 tmp = sha->loLen;
if ((sha->loLen += len) < tmp)
sha->hiLen++; /* carry low to high */
}
#endif
/* Software implementation */
#ifdef USE_SHA_SOFTWARE_IMPL
@ -410,13 +458,6 @@
#endif /* !USE_CUSTOM_SHA_TRANSFORM */
static INLINE void AddLength(Sha* sha, word32 len)
{
word32 tmp = sha->loLen;
if ( (sha->loLen += len) < tmp)
sha->hiLen++; /* carry low to high */
}
int wc_InitSha_ex(Sha* sha, void* heap, int devId)
{
int ret = 0;

326
wolfcrypt/src/sha256.c
View File

@ -100,7 +100,9 @@
#endif
#ifndef WOLFSSL_PIC32MZ_HASH
static INLINE void AddLength(Sha256* sha256, word32 len);
#if !defined(WOLFSSL_PIC32MZ_HASH) && !defined(STM32_HASH)
static int InitSha256(Sha256* sha256)
{
int ret = 0;
@ -330,6 +332,159 @@ static int InitSha256(Sha256* sha256)
#elif defined(WOLFSSL_PIC32MZ_HASH)
#include <wolfssl/wolfcrypt/port/pic32/pic32mz-crypt.h>
#elif defined(STM32_HASH)
/*
* STM32F2/F4/F7 hardware SHA256 support through the HASH_* API's from the
* Standard Peripheral Library or CubeMX (See note in README).
*/
/* STM32 register size, bytes */
#ifdef WOLFSSL_STM32_CUBEMX
#define SHA256_REG_SIZE SHA256_BLOCK_SIZE
#else
#define SHA256_REG_SIZE 4
/* STM32 struct notes:
* sha256->buffer = first 4 bytes used to hold partial block if needed
* sha256->buffLen = num bytes currently stored in sha256->buffer
* sha256->loLen = num bytes that have been written to STM32 FIFO
*/
#endif
#define SHA256_HW_TIMEOUT 0xFF
int wc_InitSha256_ex(Sha256* sha256, void* heap, int devId)
{
if (sha256 == NULL)
return BAD_FUNC_ARG;
sha256->heap = heap;
XMEMSET(sha256->buffer, 0, sizeof(sha256->buffer));
sha256->buffLen = 0;
sha256->loLen = 0;
sha256->hiLen = 0;
/* initialize HASH peripheral */
#ifdef WOLFSSL_STM32_CUBEMX
HAL_HASH_DeInit(&sha256->hashHandle);
sha256->hashHandle.Init.DataType = HASH_DATATYPE_8B;
if (HAL_HASH_Init(&sha256->hashHandle) != HAL_OK) {
return ASYNC_INIT_E;
}
/* reset the hash control register */
/* required because Cube MX is not clearing algo bits */
HASH->CR &= ~HASH_CR_ALGO;
#else
HASH_DeInit();
/* reset the hash control register */
HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
/* configure algo used, algo mode, datatype */
HASH->CR |= (HASH_AlgoSelection_SHA256 | HASH_AlgoMode_HASH
| HASH_DataType_8b);
/* reset HASH processor */
HASH->CR |= HASH_CR_INIT;
#endif
return 0;
}
int wc_Sha256Update(Sha256* sha256, const byte* data, word32 len)
{
int ret = 0;
byte* local;
if (sha256 == NULL || (data == NULL && len > 0)) {
return BAD_FUNC_ARG;
}
/* do block size increments */
local = (byte*)sha256->buffer;
/* check that internal buffLen is valid */
if (sha256->buffLen >= SHA256_REG_SIZE)
return BUFFER_E;
while (len) {
word32 add = min(len, SHA256_REG_SIZE - sha256->buffLen);
XMEMCPY(&local[sha256->buffLen], data, add);
sha256->buffLen += add;
data += add;
len -= add;
if (sha256->buffLen == SHA256_REG_SIZE) {
#ifdef WOLFSSL_STM32_CUBEMX
if (HAL_HASHEx_SHA256_Accumulate(
&sha256->hashHandle, local, SHA256_REG_SIZE) != HAL_OK) {
ret = ASYNC_OP_E;
}
#else
HASH_DataIn(*(uint32_t*)local);
#endif
AddLength(sha256, SHA256_REG_SIZE);
sha256->buffLen = 0;
}
}
return ret;
}
int wc_Sha256Final(Sha256* sha256, byte* hash)
{
int ret = 0;
if (sha256 == NULL || hash == NULL)
return BAD_FUNC_ARG;
#ifdef WOLFSSL_STM32_CUBEMX
if (HAL_HASHEx_SHA256_Start(&sha256->hashHandle,
(byte*)sha256->buffer, sha256->buffLen,
(byte*)sha256->digest, SHA256_HW_TIMEOUT) != HAL_OK) {
ret = ASYNC_OP_E;
}
#else
__IO uint16_t nbvalidbitsdata = 0;
/* finish reading any trailing bytes into FIFO */
if (sha256->buffLen > 0) {
HASH_DataIn(*(uint32_t*)sha256->buffer);
AddLength(sha256, sha256->buffLen);
}
/* calculate number of valid bits in last word of input data */
nbvalidbitsdata = 8 * (sha256->loLen % SHA256_REG_SIZE);
/* configure number of valid bits in last word of the data */
HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
/* start HASH processor */
HASH_StartDigest();
/* wait until Busy flag == RESET */
while (HASH_GetFlagStatus(HASH_FLAG_BUSY) != RESET) {}
/* read message digest */
sha256->digest[0] = HASH->HR[0];
sha256->digest[1] = HASH->HR[1];
sha256->digest[2] = HASH->HR[2];
sha256->digest[3] = HASH->HR[3];
sha256->digest[4] = HASH->HR[4];
sha256->digest[5] = HASH_DIGEST->HR[5];
sha256->digest[6] = HASH_DIGEST->HR[6];
sha256->digest[7] = HASH_DIGEST->HR[7];
ByteReverseWords(sha256->digest, sha256->digest, SHA256_DIGEST_SIZE);
#endif /* WOLFSSL_STM32_CUBEMX */
XMEMCPY(hash, sha256->digest, SHA256_DIGEST_SIZE);
(void)wc_InitSha256_ex(sha256, sha256->heap, INVALID_DEVID);
return ret;
}
#else
#define NEED_SOFT_SHA256
@ -450,14 +605,17 @@ static int InitSha256(Sha256* sha256)
/* End wc_ software implementation */
#ifdef XTRANSFORM
#if defined(XTRANSFORM) || defined(STM32_HASH)
static INLINE void AddLength(Sha256* sha256, word32 len)
{
word32 tmp = sha256->loLen;
if ( (sha256->loLen += len) < tmp)
sha256->hiLen++; /* carry low to high */
}
#endif
static INLINE void AddLength(Sha256* sha256, word32 len)
{
word32 tmp = sha256->loLen;
if ( (sha256->loLen += len) < tmp)
sha256->hiLen++; /* carry low to high */
}
#ifdef XTRANSFORM
static INLINE int Sha256Update(Sha256* sha256, const byte* data, word32 len)
{
@ -1771,6 +1929,152 @@ static int Transform_AVX2(Sha256* sha256)
#ifdef WOLFSSL_SHA224
#ifdef STM32_HASH
#define Sha256Update Sha224Update
#define Sha256Final Sha224Final
/*
* STM32F2/F4/F7 hardware SHA224 support through the HASH_* API's from the
* Standard Peripheral Library or CubeMX (See note in README).
*/
/* STM32 register size, bytes */
#ifdef WOLFSSL_STM32_CUBEMX
#define SHA224_REG_SIZE SHA224_BLOCK_SIZE
#else
#define SHA224_REG_SIZE 4
/* STM32 struct notes:
* sha224->buffer = first 4 bytes used to hold partial block if needed
* sha224->buffLen = num bytes currently stored in sha256->buffer
* sha224->loLen = num bytes that have been written to STM32 FIFO
*/
#endif
#define SHA224_HW_TIMEOUT 0xFF
static int InitSha224(Sha224* sha224)
{
if (sha224 == NULL)
return BAD_FUNC_ARG;
XMEMSET(sha224->buffer, 0, sizeof(sha224->buffer));
sha224->buffLen = 0;
sha224->loLen = 0;
sha224->hiLen = 0;
/* initialize HASH peripheral */
#ifdef WOLFSSL_STM32_CUBEMX
HAL_HASH_DeInit(&sha224->hashHandle);
sha224->hashHandle.Init.DataType = HASH_DATATYPE_8B;
if (HAL_HASH_Init(&sha224->hashHandle) != HAL_OK) {
return ASYNC_INIT_E;
}
/* required because Cube MX is not clearing algo bits */
HASH->CR &= ~HASH_CR_ALGO;
#else
HASH_DeInit();
/* reset the hash control register */
/* required because Cube MX is not clearing algo bits */
HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
/* configure algo used, algo mode, datatype */
HASH->CR |= (HASH_AlgoSelection_SHA224 | HASH_AlgoMode_HASH
| HASH_DataType_8b);
/* reset HASH processor */
HASH->CR |= HASH_CR_INIT;
#endif
return 0;
}
static int Sha224Update(Sha256* sha224, const byte* data, word32 len)
{
int ret = 0;
byte* local;
/* do block size increments */
local = (byte*)sha224->buffer;
/* check that internal buffLen is valid */
if (sha224->buffLen >= SHA224_REG_SIZE)
return BUFFER_E;
while (len) {
word32 add = min(len, SHA224_REG_SIZE - sha224->buffLen);
XMEMCPY(&local[sha224->buffLen], data, add);
sha224->buffLen += add;
data += add;
len -= add;
if (sha224->buffLen == SHA224_REG_SIZE) {
#ifdef WOLFSSL_STM32_CUBEMX
if (HAL_HASHEx_SHA224_Accumulate(
&sha224->hashHandle, local, SHA224_REG_SIZE) != HAL_OK) {
ret = ASYNC_OP_E;
}
#else
HASH_DataIn(*(uint32_t*)local);
#endif
AddLength(sha224, SHA224_REG_SIZE);
sha224->buffLen = 0;
}
}
return ret;
}
static int Sha224Final(Sha256* sha224)
{
int ret = 0;
#ifdef WOLFSSL_STM32_CUBEMX
if (HAL_HASHEx_SHA224_Start(&sha224->hashHandle,
(byte*)sha224->buffer, sha224->buffLen,
(byte*)sha224->digest, SHA224_HW_TIMEOUT) != HAL_OK) {
ret = ASYNC_OP_E;
}
#else
__IO uint16_t nbvalidbitsdata = 0;
/* finish reading any trailing bytes into FIFO */
if (sha224->buffLen > 0) {
HASH_DataIn(*(uint32_t*)sha224->buffer);
AddLength(sha224, sha224->buffLen);
}
/* calculate number of valid bits in last word of input data */
nbvalidbitsdata = 8 * (sha224->loLen % SHA224_REG_SIZE);
/* configure number of valid bits in last word of the data */
HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
/* start HASH processor */
HASH_StartDigest();
/* wait until Busy flag == RESET */
while (HASH_GetFlagStatus(HASH_FLAG_BUSY) != RESET) {}
/* read message digest */
sha224->digest[0] = HASH->HR[0];
sha224->digest[1] = HASH->HR[1];
sha224->digest[2] = HASH->HR[2];
sha224->digest[3] = HASH->HR[3];
sha224->digest[4] = HASH->HR[4];
sha224->digest[5] = HASH_DIGEST->HR[5];
sha224->digest[6] = HASH_DIGEST->HR[6];
ByteReverseWords(sha224->digest, sha224->digest, SHA224_DIGEST_SIZE);
#endif /* WOLFSSL_STM32_CUBEMX */
return ret;
}
#else
static int InitSha224(Sha224* sha224)
{
@ -1801,6 +2105,8 @@ static int Transform_AVX2(Sha256* sha256)
return ret;
}
#endif /* STM32_HASH */
int wc_InitSha224_ex(Sha224* sha224, void* heap, int devId)
{
int ret = 0;
@ -1845,7 +2151,7 @@ static int Transform_AVX2(Sha256* sha256)
}
#endif /* WOLFSSL_ASYNC_CRYPT */
ret = Sha256Update((Sha256 *)sha224, data, len);
ret = Sha256Update((Sha256*)sha224, data, len);
return ret;
}
@ -1871,7 +2177,7 @@ static int Transform_AVX2(Sha256* sha256)
if (ret != 0)
return ret;
#if defined(LITTLE_ENDIAN_ORDER)
#if defined(LITTLE_ENDIAN_ORDER) && !defined(STM32_HASH)
ByteReverseWords(sha224->digest, sha224->digest, SHA224_DIGEST_SIZE);
#endif
XMEMCPY(hash, sha224->digest, SHA224_DIGEST_SIZE);

10
wolfcrypt/test/test.c
View File

@ -5031,8 +5031,7 @@ int aes_test(void)
return -4216;
/* test not supported on STM32 crypto HW or PIC32MZ HW */
#if !defined(STM32F2_CRYPTO) && !defined(STM32F4_CRYPTO) && \
!defined(WOLFSSL_PIC32MZ_CRYPT)
#if !defined(STM32_CRYPTO) && !defined(WOLFSSL_PIC32MZ_CRYPT)
/* and an additional 9 bytes to reuse tmp left buffer */
ret = wc_AesCtrEncrypt(&enc, cipher, ctrPlain, sizeof(oddCipher));
if (ret != 0) {
@ -5405,8 +5404,7 @@ int aesgcm_test(void)
/* FIPS, QAT and STM32F2/4 HW Crypto only support 12-byte IV */
#if !defined(HAVE_FIPS) && !defined(HAVE_INTEL_QA) && \
!defined(STM32F2_CRYPTO) && !defined(STM32F4_CRYPTO) && \
!defined(WOLFSSL_PIC32MZ_CRYPT) && \
!defined(STM32_CRYPTO) && !defined(WOLFSSL_PIC32MZ_CRYPT) && \
!defined(WOLFSSL_XILINX_CRYPT)
#define ENABLE_NON_12BYTE_IV_TEST
@ -5454,7 +5452,7 @@ int aesgcm_test(void)
byte resultP[sizeof(p)];
byte resultC[sizeof(p)];
int result;
#if !defined(HAVE_FIPS) && !defined(STM32F2_CRYPTO) && !defined(STM32F4_CRYPTO)
#if !defined(HAVE_FIPS) && !defined(STM32_CRYPTO)
int ivlen;
#endif
int alen, plen;
@ -5535,7 +5533,7 @@ int aesgcm_test(void)
return -4309;
#endif /* BENCH_AESGCM_LARGE */
#if !defined(HAVE_FIPS) && !defined(STM32F2_CRYPTO) && !defined(STM32F4_CRYPTO)
#if !defined(HAVE_FIPS) && !defined(STM32_CRYPTO)
/* Variable IV length test */
for (ivlen=0; ivlen<(int)sizeof(k1); ivlen++) {
/* AES-GCM encrypt and decrypt both use AES encrypt internally */

2
wolfssl/wolfcrypt/des3.h
View File

@ -58,7 +58,7 @@ enum {
#define DES3_KEYLEN 24
#if defined(STM32F2_CRYPTO) || defined(STM32F4_CRYPTO)
#if defined(STM32_CRYPTO)
enum {
DES_CBC = 0,
DES_ECB = 1

6
wolfssl/wolfcrypt/md5.h
View File

@ -40,9 +40,6 @@
/* in bytes */
enum {
#if defined(STM32F2_HASH) || defined(STM32F4_HASH)
MD5_REG_SIZE = 4, /* STM32 register size, bytes */
#endif
MD5 = 0, /* hash type unique */
MD5_BLOCK_SIZE = 64,
MD5_DIGEST_SIZE = 16,
@ -75,6 +72,9 @@ typedef struct Md5 {
#ifdef WOLFSSL_PIC32MZ_HASH
hashUpdCache cache; /* cache for updates */
#endif
#if defined(STM32_HASH) && defined(WOLFSSL_STM32_CUBEMX)
HASH_HandleTypeDef hashHandle;
#endif
#ifdef WOLFSSL_ASYNC_CRYPT
WC_ASYNC_DEV asyncDev;
#endif /* WOLFSSL_ASYNC_CRYPT */

83
wolfssl/wolfcrypt/settings.h
View File

@ -91,6 +91,12 @@
/* Uncomment next line if using STM32F2 */
/* #define WOLFSSL_STM32F2 */
/* Uncomment next line if using STM32F4 */
/* #define WOLFSSL_STM32F4 */
/* Uncomment next line if using STM32F7 */
/* #define WOLFSSL_STM32F7 */
/* Uncomment next line if using QL SEP settings */
/* #define WOLFSSL_QL */
@ -960,33 +966,9 @@ extern void uITRON4_free(void *p) ;
#define GCM_TABLE
#endif
#ifdef WOLFSSL_STM32F2
#define SIZEOF_LONG_LONG 8
#define NO_DEV_RANDOM
#define NO_WOLFSSL_DIR
#undef NO_RABBIT
#define NO_RABBIT
#undef NO_64BIT
#define NO_64BIT
#define STM32F2_RNG
#define STM32F2_CRYPTO
#if !defined(__GNUC__) && !defined(__ICCARM__)
#define KEIL_INTRINSICS
#endif
#define NO_OLD_RNGNAME
#ifdef WOLFSSL_STM32_CUBEMX
#include "stm32f2xx_hal.h"
#ifndef STM32_HAL_TIMEOUT
#define STM32_HAL_TIMEOUT 0xFF
#endif
#else
#include "stm32f2xx.h"
#include "stm32f2xx_cryp.h"
#include "stm32f2xx_hash.h"
#endif /* WOLFSSL_STM32_CUBEMX */
#endif
#if defined(WOLFSSL_STM32F2) || defined(WOLFSSL_STM32F4) || \
defined(WOLFSSL_STM32F7)
#ifdef WOLFSSL_STM32F4
#define SIZEOF_LONG_LONG 8
#define NO_DEV_RANDOM
#define NO_WOLFSSL_DIR
@ -994,23 +976,56 @@ extern void uITRON4_free(void *p) ;
#define NO_RABBIT
#undef NO_64BIT
#define NO_64BIT
#define STM32F4_RNG
#define STM32F4_CRYPTO
#define NO_OLD_RNGNAME
#ifndef NO_STM32_RNG
#undef STM32_RNG
#define STM32_RNG
#endif
#ifndef NO_STM32_CRYPTO
#undef STM32_CRYPTO
#define STM32_CRYPTO
#endif
#ifndef NO_STM32_HASH
#undef STM32_HASH
#define STM32_HASH
#endif
#if !defined(__GNUC__) && !defined(__ICCARM__)
#define KEIL_INTRINSICS
#endif
#define NO_OLD_RNGNAME
#ifdef WOLFSSL_STM32_CUBEMX
#include "stm32f4xx_hal.h"
#if defined(WOLFSSL_STM32F2)
#include "stm32f2xx_hal.h"
#elif defined(WOLFSSL_STM32F4)
#include "stm32f4xx_hal.h"
#elif defined(WOLFSSL_STM32F7)
#include "stm32f7xx_hal.h"
#endif
#ifndef STM32_HAL_TIMEOUT
#define STM32_HAL_TIMEOUT 0xFF
#endif
#else
#include "stm32f4xx.h"
#include "stm32f4xx_cryp.h"
#include "stm32f4xx_hash.h"
#if defined(WOLFSSL_STM32F2)
#include "stm32f2xx.h"
#ifdef STM32_CRYPTO
#include "stm32f2xx_cryp.h"
#endif
#ifdef STM32_HASH
#include "stm32f2xx_hash.h"
#endif
#elif defined(WOLFSSL_STM32F4)
#include "stm32f4xx.h"
#ifdef STM32_CRYPTO
#include "stm32f4xx_cryp.h"
#endif
#ifdef STM32_HASH
#include "stm32f4xx_hash.h"
#endif
#elif defined(WOLFSSL_STM32F7)
#include "stm32f7xx.h"
#endif
#endif /* WOLFSSL_STM32_CUBEMX */
#endif
#endif /* WOLFSSL_STM32F2 || WOLFSSL_STM32F4 || WOLFSSL_STM32F7 */
#ifdef MICRIUM
#include <stdlib.h>

44
wolfssl/wolfcrypt/sha.h
View File

@ -51,9 +51,6 @@
/* in bytes */
enum {
#if defined(STM32F2_HASH) || defined(STM32F4_HASH)
SHA_REG_SIZE = 4, /* STM32 register size, bytes */
#endif
SHA = 1, /* hash type unique */
SHA_BLOCK_SIZE = 64,
SHA_DIGEST_SIZE = 20,
@ -64,25 +61,28 @@ enum {
#ifndef WOLFSSL_TI_HASH
/* Sha digest */
typedef struct Sha {
#ifdef FREESCALE_LTC_SHA
ltc_hash_ctx_t ctx;
#else
word32 buffLen; /* in bytes */
word32 loLen; /* length in bytes */
word32 hiLen; /* length in bytes */
word32 buffer[SHA_BLOCK_SIZE / sizeof(word32)];
#ifdef WOLFSSL_PIC32MZ_HASH
word32 digest[PIC32_DIGEST_SIZE / sizeof(word32)];
#else
word32 digest[SHA_DIGEST_SIZE / sizeof(word32)];
#endif
void* heap;
#ifdef WOLFSSL_PIC32MZ_HASH
hashUpdCache cache; /* cache for updates */
#endif
#ifdef WOLFSSL_ASYNC_CRYPT
WC_ASYNC_DEV asyncDev;
#endif /* WOLFSSL_ASYNC_CRYPT */
#ifdef FREESCALE_LTC_SHA
ltc_hash_ctx_t ctx;
#else
word32 buffLen; /* in bytes */
word32 loLen; /* length in bytes */
word32 hiLen; /* length in bytes */
word32 buffer[SHA_BLOCK_SIZE / sizeof(word32)];
#ifdef WOLFSSL_PIC32MZ_HASH
word32 digest[PIC32_DIGEST_SIZE / sizeof(word32)];
#else
word32 digest[SHA_DIGEST_SIZE / sizeof(word32)];
#endif
void* heap;
#ifdef WOLFSSL_PIC32MZ_HASH
hashUpdCache cache; /* cache for updates */
#endif
#if defined(STM32_HASH) && defined(WOLFSSL_STM32_CUBEMX)
HASH_HandleTypeDef hashHandle;
#endif
#ifdef WOLFSSL_ASYNC_CRYPT
WC_ASYNC_DEV asyncDev;
#endif /* WOLFSSL_ASYNC_CRYPT */
#endif /* FREESCALE_LTC_SHA */
} Sha;

3
wolfssl/wolfcrypt/sha256.h
View File

@ -77,6 +77,9 @@ typedef struct Sha256 {
#ifdef WOLFSSL_PIC32MZ_HASH
hashUpdCache cache; /* cache for updates */
#endif
#if defined(STM32_HASH) && defined(WOLFSSL_STM32_CUBEMX)
HASH_HandleTypeDef hashHandle;
#endif
#ifdef WOLFSSL_ASYNC_CRYPT
WC_ASYNC_DEV asyncDev;
#endif /* WOLFSSL_ASYNC_CRYPT */