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Improve the "adder" for compatibility layer SHA context when hardware acceleration is used.

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This commit is contained in:
David Garske 2023-02-24 07:28:15 -08:00
parent aef44ff029
commit b1f421d0a6
1 changed files with 18 additions and 25 deletions
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43
wolfssl/openssl/sha.h
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@ -36,20 +36,23 @@
extern "C" {
#endif
/* adder for HW crypto */
#if defined(STM32_HASH)
#define CTX_SHA_HW_ADDER sizeof(STM32_HASH_Context)
#elif defined(WOLFSSL_IMXRT1170_CAAM)
#define CTX_SHA_HW_ADDER (sizeof(caam_hash_ctx_t) + sizeof(caam_handle_t))
#elif defined(WOLFSSL_ESPWROOM32) && \
!defined(NO_WOLFSSL_ESP32WROOM32_CRYPT_HASH)
#define CTX_SHA_HW_ADDER sizeof(WC_ESP32SHA)
#else
#define CTX_SHA_HW_ADDER 0
#endif
#ifndef NO_SHA
typedef struct WOLFSSL_SHA_CTX {
/* big enough to hold wolfcrypt Sha, but check on init */
#if defined(STM32_HASH)
void* holder[(112 + WC_ASYNC_DEV_SIZE + sizeof(STM32_HASH_Context)) /
sizeof(void*)];
#elif defined(WOLFSSL_ESPWROOM32) && !defined(NO_WOLFSSL_ESP32WROOM32_CRYPT_HASH)
void* holder[(112 + WC_ASYNC_DEV_SIZE + sizeof(WC_ESP32SHA)) / sizeof(void*)];
#elif defined(WOLFSSL_IMXRT1170_CAAM)
void* holder[(112 + WC_ASYNC_DEV_SIZE + sizeof(caam_hash_ctx_t) +
sizeof(caam_handle_t)) / sizeof(void*)];
#else
void* holder[(112 + WC_ASYNC_DEV_SIZE) / sizeof(void*)];
#endif
void* holder[(112 + WC_ASYNC_DEV_SIZE + CTX_SHA_HW_ADDER) / sizeof(void*)];
#if defined(WOLFSSL_DEVCRYPTO_HASH) || defined(WOLFSSL_HASH_KEEP)
void* keephash_holder[sizeof(void*) + (2 * sizeof(unsigned int))];
#endif
@ -99,16 +102,6 @@ typedef WOLFSSL_SHA_CTX SHA_CTX;
#endif /* OPENSSL_EXTRA || OPENSSL_EXTRA_X509_SMALL */
#endif /* !NO_SHA */
/* adder for HW crypto */
#ifdef STM32_HASH
#define CTX_SHA2_HW_ADDER 34
#elif defined(WOLFSSL_IMXRT1170_CAAM)
#define CTX_SHA2_HW_ADDER sizeof(caam_hash_ctx_t) + sizeof(caam_handle_t)
#elif defined(WOLFSSL_ESPWROOM32)
#define CTX_SHA2_HW_ADDER sizeof(WC_ESP32SHA)
#else
#define CTX_SHA2_HW_ADDER 0
#endif
#ifdef WOLFSSL_SHA224
@ -117,7 +110,7 @@ typedef WOLFSSL_SHA_CTX SHA_CTX;
* to Sha224, is expected to also be 16 byte aligned addresses. */
typedef struct WOLFSSL_SHA224_CTX {
/* big enough to hold wolfcrypt Sha224, but check on init */
ALIGN16 void* holder[(274 + CTX_SHA2_HW_ADDER + WC_ASYNC_DEV_SIZE) /
ALIGN16 void* holder[(274 + CTX_SHA_HW_ADDER + WC_ASYNC_DEV_SIZE) /
sizeof(void*)];
#if defined(WOLFSSL_DEVCRYPTO_HASH) || defined(WOLFSSL_HASH_KEEP)
ALIGN16 void* keephash_holder[sizeof(void*) + (2 * sizeof(unsigned int))];
@ -158,7 +151,7 @@ typedef WOLFSSL_SHA224_CTX SHA224_CTX;
* to Sha256, is expected to also be 16 byte aligned addresses. */
typedef struct WOLFSSL_SHA256_CTX {
/* big enough to hold wolfcrypt Sha256, but check on init */
ALIGN16 void* holder[(274 + CTX_SHA2_HW_ADDER + WC_ASYNC_DEV_SIZE) /
ALIGN16 void* holder[(274 + CTX_SHA_HW_ADDER + WC_ASYNC_DEV_SIZE) /
sizeof(void*)];
#if defined(WOLFSSL_DEVCRYPTO_HASH) || defined(WOLFSSL_HASH_KEEP)
ALIGN16 void* keephash_holder[sizeof(void*) + (2 * sizeof(unsigned int))];
@ -209,7 +202,7 @@ typedef WOLFSSL_SHA256_CTX SHA256_CTX;
#ifdef WOLFSSL_SHA384
typedef struct WOLFSSL_SHA384_CTX {
/* big enough to hold wolfCrypt Sha384, but check on init */
void* holder[(268 + CTX_SHA2_HW_ADDER + WC_ASYNC_DEV_SIZE) / sizeof(void*)];
void* holder[(268 + CTX_SHA_HW_ADDER + WC_ASYNC_DEV_SIZE) / sizeof(void*)];
#if defined(WOLFSSL_DEVCRYPTO_HASH) || defined(WOLFSSL_HASH_KEEP)
void* keephash_holder[sizeof(void*) + (2 * sizeof(unsigned int))];
#endif
@ -244,7 +237,7 @@ typedef WOLFSSL_SHA384_CTX SHA384_CTX;
#ifdef WOLFSSL_SHA512
typedef struct WOLFSSL_SHA512_CTX {
/* big enough to hold wolfCrypt Sha384, but check on init */
void* holder[(288 + CTX_SHA2_HW_ADDER + WC_ASYNC_DEV_SIZE) / sizeof(void*)];
void* holder[(288 + CTX_SHA_HW_ADDER + WC_ASYNC_DEV_SIZE) / sizeof(void*)];
#if defined(WOLFSSL_DEVCRYPTO_HASH) || defined(WOLFSSL_HASH_KEEP)
void* keephash_holder[sizeof(void*) + (2 * sizeof(unsigned int))];
#endif