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Takashi Kojo 2014-05-05 09:39:59 +09:00
parent b712380a60
commit 238e7b9458
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338
IDE/MDK-ARM/LPC43xx/startup_LPC43xx.s
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;/***********************************************************************
; * $Id: startup_LPC43xx.s 6473 2011-02-16 17:40:54Z nxp27266 $
; *
; * Project: LPC43xx CMSIS Package
; *
; * Description: Cortex-M3 Core Device Startup File for the NXP LPC43xx
; * Device Series.
; *
; * Copyright(C) 2011, NXP Semiconductor
; * All rights reserved.
; *
; * modified by KEIL
; ***********************************************************************
; * Software that is described herein is for illustrative purposes only
; * which provides customers with programming information regarding the
; * products. This software is supplied "AS IS" without any warranties.
; * NXP Semiconductors assumes no responsibility or liability for the
; * use of the software, conveys no license or title under any patent,
; * copyright, or mask work right to the product. NXP Semiconductors
; * reserves the right to make changes in the software without
; * notification. NXP Semiconductors also make no representation or
; * warranty that such application will be suitable for the specified
; * use without further testing or modification.
; **********************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00003000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x0000a000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
Sign_Value EQU 0x5A5A5A5A
__Vectors DCD __initial_sp ; 0 Top of Stack
DCD Reset_Handler ; 1 Reset Handler
DCD NMI_Handler ; 2 NMI Handler
DCD HardFault_Handler ; 3 Hard Fault Handler
DCD MemManage_Handler ; 4 MPU Fault Handler
DCD BusFault_Handler ; 5 Bus Fault Handler
DCD UsageFault_Handler ; 6 Usage Fault Handler
DCD Sign_Value ; 7 Reserved
DCD 0 ; 8 Reserved
DCD 0 ; 9 Reserved
DCD 0 ; 10 Reserved
DCD SVC_Handler ; 11 SVCall Handler
DCD DebugMon_Handler ; 12 Debug Monitor Handler
DCD 0 ; 13 Reserved
DCD PendSV_Handler ; 14 PendSV Handler
DCD SysTick_Handler ; 15 SysTick Handler
; External Interrupts
DCD DAC_IRQHandler ; 16 D/A Converter
DCD M0CORE_IRQHandler ; 17 M0 Core
DCD DMA_IRQHandler ; 18 General Purpose DMA
DCD EZH_IRQHandler ; 19 EZH/EDM
DCD FLASH_EEPROM_IRQHandler ; 20 Reserved for Typhoon
DCD ETH_IRQHandler ; 21 Ethernet
DCD SDIO_IRQHandler ; 22 SD/MMC
DCD LCD_IRQHandler ; 23 LCD
DCD USB0_IRQHandler ; 24 USB0
DCD USB1_IRQHandler ; 25 USB1
DCD SCT_IRQHandler ; 26 State Configurable Timer
DCD RIT_IRQHandler ; 27 Repetitive Interrupt Timer
DCD TIMER0_IRQHandler ; 28 Timer0
DCD TIMER1_IRQHandler ; 29 Timer1
DCD TIMER2_IRQHandler ; 30 Timer2
DCD TIMER3_IRQHandler ; 31 Timer3
DCD MCPWM_IRQHandler ; 32 Motor Control PWM
DCD ADC0_IRQHandler ; 33 A/D Converter 0
DCD I2C0_IRQHandler ; 34 I2C0
DCD I2C1_IRQHandler ; 35 I2C1
DCD SPI_IRQHandler ; 36 SPI
DCD ADC1_IRQHandler ; 37 A/D Converter 1
DCD SSP0_IRQHandler ; 38 SSP0
DCD SSP1_IRQHandler ; 39 SSP1
DCD UART0_IRQHandler ; 40 UART0
DCD UART1_IRQHandler ; 41 UART1
DCD UART2_IRQHandler ; 42 UART2
DCD UART3_IRQHandler ; 43 UART3
DCD I2S0_IRQHandler ; 44 I2S0
DCD I2S1_IRQHandler ; 45 I2S1
DCD SPIFI_IRQHandler ; 46 SPI Flash Interface
DCD SGPIO_IRQHandler ; 47 SGPIO
DCD GPIO0_IRQHandler ; 48 GPIO0
DCD GPIO1_IRQHandler ; 49 GPIO1
DCD GPIO2_IRQHandler ; 50 GPIO2
DCD GPIO3_IRQHandler ; 51 GPIO3
DCD GPIO4_IRQHandler ; 52 GPIO4
DCD GPIO5_IRQHandler ; 53 GPIO5
DCD GPIO6_IRQHandler ; 54 GPIO6
DCD GPIO7_IRQHandler ; 55 GPIO7
DCD GINT0_IRQHandler ; 56 GINT0
DCD GINT1_IRQHandler ; 57 GINT1
DCD EVRT_IRQHandler ; 58 Event Router
DCD CAN1_IRQHandler ; 59 C_CAN1
DCD 0 ; 60 Reserved
DCD VADC_IRQHandler ; 61 VADC
DCD ATIMER_IRQHandler ; 62 ATIMER
DCD RTC_IRQHandler ; 63 RTC
DCD 0 ; 64 Reserved
DCD WDT_IRQHandler ; 65 WDT
DCD M0s_IRQHandler ; 66 M0s
DCD CAN0_IRQHandler ; 67 C_CAN0
DCD QEI_IRQHandler ; 68 QEI
;CRP address at offset 0x2FC relative to the BOOT Bank address
IF :LNOT::DEF:NO_CRP
SPACE (0x2FC - (. - __Vectors))
; EXPORT CRP_Key
CRP_Key DCD 0xFFFFFFFF
; 0xFFFFFFFF => CRP Disabled
; 0x12345678 => CRP Level 1
; 0x87654321 => CRP Level 2
; 0x43218765 => CRP Level 3 (ARE YOU SURE?)
; 0x4E697370 => NO ISP (ARE YOU SURE?)
ENDIF
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT DAC_IRQHandler [WEAK]
EXPORT M0CORE_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT EZH_IRQHandler [WEAK]
EXPORT FLASH_EEPROM_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT LCD_IRQHandler [WEAK]
EXPORT USB0_IRQHandler [WEAK]
EXPORT USB1_IRQHandler [WEAK]
EXPORT SCT_IRQHandler [WEAK]
EXPORT RIT_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
EXPORT TIMER3_IRQHandler [WEAK]
EXPORT MCPWM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT I2C0_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT SSP0_IRQHandler [WEAK]
EXPORT SSP1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT I2S0_IRQHandler [WEAK]
EXPORT I2S1_IRQHandler [WEAK]
EXPORT SPIFI_IRQHandler [WEAK]
EXPORT SGPIO_IRQHandler [WEAK]
EXPORT GPIO0_IRQHandler [WEAK]
EXPORT GPIO1_IRQHandler [WEAK]
EXPORT GPIO2_IRQHandler [WEAK]
EXPORT GPIO3_IRQHandler [WEAK]
EXPORT GPIO4_IRQHandler [WEAK]
EXPORT GPIO5_IRQHandler [WEAK]
EXPORT GPIO6_IRQHandler [WEAK]
EXPORT GPIO7_IRQHandler [WEAK]
EXPORT GINT0_IRQHandler [WEAK]
EXPORT GINT1_IRQHandler [WEAK]
EXPORT EVRT_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT VADC_IRQHandler [WEAK]
EXPORT ATIMER_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT M0s_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT QEI_IRQHandler [WEAK]
DAC_IRQHandler
M0CORE_IRQHandler
DMA_IRQHandler
EZH_IRQHandler
FLASH_EEPROM_IRQHandler
ETH_IRQHandler
SDIO_IRQHandler
LCD_IRQHandler
USB0_IRQHandler
USB1_IRQHandler
SCT_IRQHandler
RIT_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
TIMER3_IRQHandler
MCPWM_IRQHandler
ADC0_IRQHandler
I2C0_IRQHandler
I2C1_IRQHandler
SPI_IRQHandler
ADC1_IRQHandler
SSP0_IRQHandler
SSP1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
I2S0_IRQHandler
I2S1_IRQHandler
SPIFI_IRQHandler
SGPIO_IRQHandler
GPIO0_IRQHandler
GPIO1_IRQHandler
GPIO2_IRQHandler
GPIO3_IRQHandler
GPIO4_IRQHandler
GPIO5_IRQHandler
GPIO6_IRQHandler
GPIO7_IRQHandler
GINT0_IRQHandler
GINT1_IRQHandler
EVRT_IRQHandler
CAN1_IRQHandler
VADC_IRQHandler
ATIMER_IRQHandler
RTC_IRQHandler
WDT_IRQHandler
M0s_IRQHandler
CAN0_IRQHandler
QEI_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

22
IDE/MDK-ARM/MDK-ARM/config/Dbg_Flash.ini
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/******************************************************************************/
/* Dbg_Flash.ini Initialization File for Debugging from Internal */
/* Flash for NXP LPC18xx/LPC43xx */
/******************************************************************************/
/* This file is part of the uVision/ARM development tools. */
/* Copyright (c) 2005-2012 Keil Software. All rights reserved. */
/* This software may only be used under the terms of a valid, current, */
/* end user licence from KEIL for a compatible version of KEIL software */
/* development tools. Nothing else gives you the right to use this software. */
/******************************************************************************/
FUNC void Per_Reset (void) {
// Reset peripherals: LCD, USB0, USB1, DMA, SDIO, ETHERNET
_WDWORD(0x40053100, 0x005F0000); // Issue reset
_sleep_(1);
}
Per_Reset(); // Reset some peripherals
KILL BUTTON * // Kill all buttons
DEFINE BUTTON "Reset Peripherals", "Per_Reset()" // Create peripheral reset button

401
IDE/MDK-ARM/MDK-ARM/config/File_Config.c
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/*----------------------------------------------------------------------------
* RL-ARM - FlashFS
*----------------------------------------------------------------------------
* Name: FILE_CONFIG.C
* Purpose: Configuration of RL FlashFS by user
* Rev.: V4.70
*----------------------------------------------------------------------------
* This code is part of the RealView Run-Time Library.
* Copyright (c) 2004-2013 KEIL - An ARM Company. All rights reserved.
*---------------------------------------------------------------------------*/
#include <File_Config.h>
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
//
// <h>File System
// ==============
// <i> Define File System global parameters
// <o>Number of open files <4-16>
// <i>Define number of files that can be
// <i>opened at the same time.
// <i>Default: 8
#define N_FILES 6
// <o>FAT Name Cache Size <0-1000000>
// <i>Define number of cached FAT file or directory names.
// <i>48 bytes of RAM is required for each cached name.
#define FAT_NAME_CACNT 0
// <e>Relocate FAT Name Cache Buffer
// <i>Locate Cache Buffer at a specific address.
#define FAT_NAME_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define the Cache buffer base address.
#define FAT_NAME_CADR 0x60000000
// </e>
// <o>CPU Clock Frequency [Hz]<0-1000000000>
// <i>Define the CPU Clock frequency used for
// <i>flash programming and erasing.
#define CPU_CLK 180000000
// </h>
// <e>Flash Drive
// ==============
// <i>Enable Embedded Flash Drive [F:]
#define FL0_EN 0
// <o>Base address <0x0-0xFFFFF000:0x1000>
// <i>Define the target device Base address
// <i>Default: 0x80000000
#define FL0_BADR 0x80000000
// <o>Device Size <0x4000-0xFFFFF000:0x4000>
// <i>Define the size of Flash device in bytes
// <i>Default: 0x100000 (1MB)
#define FL0_SIZE 0x0200000
// <o>Content of Erased Memory <0=>0x00 <0xFF=>0xFF
// <i>Define the initial value for erased Flash data
// <i>Default: 0xFF
#define FL0_INITV 0xFF
// <s.80>Device Description file
// <i>Specify a file name with a relative path
// <i>Default: FS_FlashDev.h
#define FL0_HFILE "FS_FlashDev.h"
// <q>Default Drive [F:]
// <i>Used when Drive letter not specified
#define FL0_DEF 1
// </e>
// <e>SPI Flash Drive
// ==================
// <i>Enable SPI Flash Drive [S:]
#define SF0_EN 0
// <o>Device Size <0x10000-0xFFFFF000:0x8000>
// <i>Define the size of SPI Flash device in bytes
// <i>Default: 0x100000 (1MB)
#define SF0_SIZE 0x0200000
// <o>Content of Erased Memory <0=>0x00 <0xFF=>0xFF
// <i>Define the initial value for erased Flash data
// <i>Default: 0xFF
#define SF0_INITV 0xFF
// <s.80>Device Description file
// <i>Specify a file name with a relative path
// <i>Default: FS_SPI_FlashDev.h
#define SF0_HFILE "FS_SPI_FlashDev.h"
// <q>Default Drive [S:]
// <i>Used when Drive letter not specified
#define SF0_DEF 0
// </e>
// <e>RAM Drive
// ============
// <i>Enable Embedded RAM Drive [R:]
#define RAM0_EN 0
// <o>Device Size <0x4000-0xFFFFF000:0x4000>
// <i>Define the size of RAM device in bytes
// <i>Default: 0x40000
#define RAM0_SIZE 0x004000
// <o>Number of Sectors <8=>8 <16=>16 <32=>32 <64=>64 <128=>128
// <i>Define number of virtual sectors for RAM device
// <i>Default: 32
#define RAM0_NSECT 64
// <e>Relocate Device Buffer
// <i>Locate RAM Device Buffer at a specific address.
// <i>If not enabled, the linker selects base address.
#define RAM0_RELOC 1
// <o>Base address <0x0-0xFFFFF000:0x1000>
// <i>Define the target device Base address.
// <i>Default: 0x81000000
#define RAM0_BADR 0x81010000
// </e>
// <q>Default Drive [R:]
// <i>Used when Drive letter not specified
#define RAM0_DEF 0
// </e>
// <e>Memory Card Drive 0
// ======================
// <i>Enable Memory Card Drive [M0:]
#define MC0_EN 1
// <o>Bus Mode <0=>SD-Native <1=>SPI
// <i>Define Memory Card bus interface mode.
// <i>SD-Native mode needs MCI peripheral.
// <i>SPI mode uses SD Card in SPI mode.
#define MC0_SPI 0
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Define System Cache buffer size for file IO.
// <i>Increase this number for faster r/w access.
// <i>Default: 4 kB
#define MC0_CASZ 4
// <e>Relocate Cache Buffer
// <i>Locate Cache Buffer at a specific address.
// <i>Some devices like NXP LPC23xx require a Cache buffer
// <i>for DMA transfer located at specific address.
#define MC0_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define the Cache buffer base address.
// <i>For LPC23xx/24xx devices this is USB RAM
// <i>starting at 0x7FD00000.
#define MC0_CADR 0x7FD00000
// </e>
// <q>FAT Journal
// <i>Enable FAT Journal in order to guarantee
// <i>fail-safe FAT file system operation.
#define MC0_FSJ 0
// <q>Default Drive [M0:]
// <i>Used when Drive letter not specified
#define MC0_DEF 1
// </e>
// <e>Memory Card Drive 1
// ======================
// <i>Enable Memory Card Drive [M1:]
#define MC1_EN 0
// <o>Bus Mode <0=>SD-Native <1=>SPI
// <i>Define Memory Card bus interface mode.
// <i>SD-Native mode needs MCI peripheral.
// <i>SPI mode uses SD Card in SPI mode.
#define MC1_SPI 1
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Define System Cache buffer size for file IO.
// <i>Increase this number for faster r/w access.
// <i>Default: 4 kB
#define MC1_CASZ 0
// <e>Relocate Cache Buffer
// <i>Locate Cache Buffer at a specific address.
// <i>Some devices like NXP LPC23xx require a Cache buffer
// <i>for DMA transfer located at specific address.
#define MC1_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define the Cache buffer base address.
// <i>For LPC23xx/24xx devices this is USB RAM
// <i>starting at 0x7FD00000.
#define MC1_CADR 0x7FD00000
// </e>
// <q>FAT Journal
// <i>Enable FAT Journal in order to guarantee
// <i>fail-safe FAT file system operation.
#define MC1_FSJ 0
// <q>Default Drive [M1:]
// <i>Used when Drive letter not specified
#define MC1_DEF 0
// </e>
// <e>USB Flash Drive 0
// ====================
// <i>Enable USB Flash Drive [U0:]
#define USB0_EN 0
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Define System Cache buffer size for file IO.
// <i>Increase this number for faster r/w access.
// <i>Default: 4 kB
#define USB0_CASZ 8
// <q>FAT Journal
// <i>Enable FAT Journal in order to guarantee
// <i>fail-safe FAT file system operation.
#define USB0_FSJ 0
// <q>Default Drive [U0:]
// <i>Used when Drive letter not specified
#define USB0_DEF 0
// </e>
// <e>USB Flash Drive 1
// ====================
// <i>Enable USB Flash Drive [U1:]
#define USB1_EN 0
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Define System Cache buffer size for file IO.
// <i>Increase this number for faster r/w access.
// <i>Default: 4 kB
#define USB1_CASZ 8
// <q>FAT Journal
// <i>Enable FAT Journal in order to guarantee
// <i>fail-safe FAT file system operation.
#define USB1_FSJ 0
// <q>Default Drive [U1:]
// <i>Used when Drive letter not specified
#define USB1_DEF 0
// </e>
// <e>NAND Flash Drive 0
// ===================
// <i>Enable NAND Flash Drive [N0:]
#define NAND0_EN 0
// <o>Page size <528=> 512 + 16 bytes
// <2112=>2048 + 64 bytes
// <4224=>4096 + 128 bytes
// <8448=>8192 + 256 bytes
// <i>Define program Page size in bytes (User + Spare area).
#define NAND0_PGSZ 2112
// <o>Block Size <8=>8 pages <16=>16 pages <32=>32 pages
// <64=>64 pages <128=>128 pages <256=>256 pages
// <i>Define number of pages in a block.
#define NAND0_PGCNT 64
// <o>Device Size [blocks] <512-32768>
// <i>Define number of blocks in NAND Flash device.
#define NAND0_BLCNT 4096
// <o>Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
// <8=>8 pages <16=>16 pages <32=>32 pages
// <i>Define number of cached Pages.
// <i>Default: 4 pages
#define NAND0_CAPG 2
// <o>Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
// <8=>8 blocks <16=>16 blocks <32=>32 blocks
// <64=>64 blocks <128=>128 blocks <256=>256 blocks
// <i>Define number of indexed Flash Blocks.
// <i>Increase this number for better performance.
// <i>Default: 16 blocks
#define NAND0_CABL 16
// <o>Software ECC <0=>None <1=>Hamming (SLC)
// <i>Enable software ECC calculation only,
// <i>if not supported by hardware.
#define NAND0_SWECC 1
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Define System Cache buffer size for file IO.
// <i>Increase this number for faster r/w access.
// <i>Default: 4 kB
#define NAND0_CASZ 4
// <e>Relocate Cache Buffers
// <i>Use this option to locate Cache buffers
// <i>at specific address in RAM or SDRAM.
#define NAND0_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define base address for Cache Buffers.
#define NAND0_CADR 0x80000000
// </e>
// <q>FAT Journal
// <i>Enable FAT Journal in order to guarantee
// <i>fail-safe FAT file system operation.
#define NAND0_FSJ 0
// <q>Default Drive [N0:]
// <i>Used when Drive letter not specified
#define NAND0_DEF 0
// </e>
// <e>NAND Flash Drive 1
// ===================
// <i>Enable NAND Flash Drive [N1:]
#define NAND1_EN 0
// <o>Page size <528=> 512 + 16 bytes
// <2112=>2048 + 64 bytes
// <4224=>4096 + 128 bytes
// <8448=>8192 + 256 bytes
// <i>Define program Page size in bytes (User + Spare area).
#define NAND1_PGSZ 2112
// <o>Block Size <8=>8 pages <16=>16 pages <32=>32 pages
// <64=>64 pages <128=>128 pages <256=>256 pages
// <i>Define number of pages in a block.
#define NAND1_PGCNT 32
// <o>Device Size [blocks] <512-32768>
// <i>Define number of blocks in NAND Flash device.
#define NAND1_BLCNT 512
// <o>Page Caching <0=>OFF <1=>1 page <2=>2 pages <4=>4 pages
// <8=>8 pages <16=>16 pages <32=>32 pages
// <i>Define number of cached Pages.
// <i>Default: 4 pages
#define NAND1_CAPG 4
// <o>Block Indexing <0=>OFF <1=>1 block <2=>2 blocks <4=>4 blocks
// <8=>8 blocks <16=>16 blocks <32=>32 blocks
// <64=>64 blocks <128=>128 blocks <256=>256 blocks
// <i>Define number of indexed Flash Blocks.
// <i>Increase this number for better performance.
// <i>Default: 16 blocks
#define NAND1_CABL 16
// <o>Software ECC <0=>None <1=>Hamming (SLC)
// <i>Enable software ECC calculation only,
// <i>if not supported by hardware.
#define NAND1_SWECC 0
// <o>File System Cache <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Define System Cache buffer size for file IO.
// <i>Increase this number for faster r/w access.
// <i>Default: 4 kB
#define NAND1_CASZ 4
// <e>Relocate Cache Buffers
// <i>Use this option to locate Cache buffers
// <i>at specific address in RAM or SDRAM.
#define NAND1_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define base address for Cache Buffers.
#define NAND1_CADR 0x80000000
// </e>
// <q>FAT Journal
// <i>Enable FAT Journal in order to guarantee
// <i>fail-safe FAT file system operation.
#define NAND1_FSJ 0
// <q>Default Drive [N1:]
// <i>Used when Drive letter not specified
#define NAND1_DEF 0
// </e>
//------------- <<< end of configuration section >>> -----------------------
#ifndef __NO_FILE_LIB_C
#include <File_lib.c>
#endif
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

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IDE/MDK-ARM/MDK-ARM/config/Net_Config.c
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/*----------------------------------------------------------------------------
* RL-ARM - TCPnet
*----------------------------------------------------------------------------
* Name: NET_CONFIG.C
* Purpose: Configuration of RL TCPnet by user.
* Rev.: V4.60
*----------------------------------------------------------------------------
* This code is part of the RealView Run-Time Library.
* Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved.
*---------------------------------------------------------------------------*/
#include <Net_Config.h>
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
//
// <h>System Definitions
// =====================
// <i> Global TCPnet System definitions
// <s.15>Local Host Name
// <i> This is the name under which embedded host can be
// <i> accessed on a local area network.
// <i> Default: "mcb2300"
#define LHOST_NAME "mcb2300"
// <o>Memory Pool size <1500-64000:4><#/4>
// <i> This is the size of a memory pool in bytes. Buffers for
// <i> TCPnet packets are allocated from this memory pool.
// <i> Default: 8000 bytes
#define MEM_SIZE 4000
// <o>Tick Timer interval <10=> 10 ms <20=> 20 ms <25=> 25 ms
// <40=> 40 ms <50=> 50 ms <100=> 100 ms
// <200=> 200 ms
// <i> System Tick Timer interval for software timers
// <i> Default: 100 ms
#define TICK_INTERVAL 10
// </h>
// <e>Ethernet Network Interface
// =============================
// <i> Enable or disable Ethernet Network Interface
#define ETH_ENABLE 1
// <h>MAC Address
// ==============
// <i> Local Ethernet MAC Address
// <i> Value FF:FF:FF:FF:FF:FF is not allowed.
// <i> It is an ethernet Broadcast MAC address.
// <o>Address byte 1 <0x00-0xff:2>
// <i> LSB is an ethernet Multicast bit.
// <i> Must be 0 for local MAC address.
// <i> Default: 0x00
#define _MAC1 0x30
// <o>Address byte 2 <0x00-0xff>
// <i> Default: 0x30
#define _MAC2 0x06
// <o>Address byte 3 <0x00-0xff>
// <i> Default: 0x6C
#define _MAC3 0x6C
// <o>Address byte 4 <0x00-0xff>
// <i> Default: 0x00
#define _MAC4 0x00
// <o>Address byte 5 <0x00-0xff>
// <i> Default: 0x00
#define _MAC5 0x00
// <o>Address byte 6 <0x00-0xff>
// <i> Default: 0x01
#define _MAC6 0x01
// </h>
// <h>IP Address
// =============
// <i> Local Static IP Address
// <i> Value 255.255.255.255 is not allowed.
// <i> It is a Broadcast IP address.
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define _IP1 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define _IP2 168
// <o>Address byte 3 <0-255>
// <i> Default: 0
#define _IP3 0
// <o>Address byte 4 <0-255>
// <i> Default: 100
#define _IP4 100
// </h>
// <h>Subnet mask
// ==============
// <i> Local Subnet mask
// <o>Mask byte 1 <0-255>
// <i> Default: 255
#define _MSK1 255
// <o>Mask byte 2 <0-255>
// <i> Default: 255
#define _MSK2 255
// <o>Mask byte 3 <0-255>
// <i> Default: 255
#define _MSK3 255
// <o>Mask byte 4 <0-255>
// <i> Default: 0
#define _MSK4 0
// </h>
// <h>Default Gateway
// ==================
// <i> Default Gateway IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define _GW1 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define _GW2 168
// <o>Address byte 3 <0-255>
// <i> Default: 0
#define _GW3 0
// <o>Address byte 4 <0-255>
// <i> Default: 254
#define _GW4 254
// </h>
// <h>Primary DNS Server
// =====================
// <i> Primary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define _pDNS1 194
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define _pDNS2 25
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define _pDNS3 2
// <o>Address byte 4 <0-255>
// <i> Default: 129
#define _pDNS4 129
// </h>
// <h>Secondary DNS Server
// =======================
// <i> Secondary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define _sDNS1 194
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define _sDNS2 25
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define _sDNS3 2
// <o>Address byte 4 <0-255>
// <i> Default: 130
#define _sDNS4 130
// </h>
// <h>ARP Definitions
// ==================
// <i> Address Resolution Protocol Definitions
// <o>Cache Table size <5-100>
// <i> Number of cached hardware/IP addresses
// <i> Default: 10
#define ARP_TABSIZE 10
// <o>Cache Timeout in seconds <5-255>
// <i> A timeout for a cached hardware/IP addresses
// <i> Default: 150
#define ARP_TIMEOUT 150
// <o>Number of Retries <0-20>
// <i> Number of Retries to resolve an IP address
// <i> before ARP module gives up
// <i> Default: 4
#define ARP_MAXRETRY 4
// <o>Resend Timeout in seconds <1-10>
// <i> A timeout to resend the ARP Request
// <i> Default: 2
#define ARP_RESEND 10
// <q>Send Notification on Address changes
// <i> When this option is enabled, the embedded host
// <i> will send a Gratuitous ARP notification at startup,
// <i> or when the device IP address has changed.
// <i> Default: Disabled
#define ARP_NOTIFY 1
// </h>
// <e>IGMP Group Management
// ========================
// <i> Enable or disable Internet Group Management Protocol
#define IGMP_ENABLE 0
// <o>Membership Table size <2-50>
// <i> Number of Groups this host can join
// <i> Default: 5
#define IGMP_TABSIZE 5
// </e>
// <q>NetBIOS Name Service
// =======================
// <i> When this option is enabled, the embedded host can be
// <i> accessed by his name on the local LAN using NBNS protocol.
// <i> You need to modify also the number of UDP Sockets,
// <i> because NBNS protocol uses one UDP socket to run.
#define NBNS_ENABLE 0
// <e>Dynamic Host Configuration
// =============================
// <i> When this option is enabled, local IP address, Net Mask
// <i> and Default Gateway are obtained automatically from
// <i> the DHCP Server on local LAN.
// <i> You need to modify also the number of UDP Sockets,
// <i> because DHCP protocol uses one UDP socket to run.
#define DHCP_ENABLE 1
// <s.40>Vendor Class Identifier
// <i> This value is optional. If specified, it is added
// <i> to DHCP request message, identifying vendor type.
// <i> Default: ""
#define DHCP_VCID ""
// <q>Bootfile Name
// <i> This value is optional. If enabled, the Bootfile Name
// <i> (option 67) is also requested from DHCP server.
// <i> Default: disabled
#define DHCP_BOOTF 1
// </e>
// </e>
// <e>PPP Network Interface
// ========================
// <i> Enable or disable PPP Network Interface
#define PPP_ENABLE 0
// <h>IP Address
// =============
// <i> Local Static IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define _IP1P 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define _IP2P 168
// <o>Address byte 3 <0-255>
// <i> Default: 125
#define _IP3P 125
// <o>Address byte 4 <0-255>
// <i> Default: 1
#define _IP4P 1
// </h>
// <h>Subnet mask
// ==============
// <i> Local Subnet mask
// <o>Mask byte 1 <0-255>
// <i> Default: 255
#define _MSK1P 255
// <o>Mask byte 2 <0-255>
// <i> Default: 255
#define _MSK2P 255
// <o>Mask byte 3 <0-255>
// <i> Default: 255
#define _MSK3P 255
// <o>Mask byte 4 <0-255>
// <i> Default: 0
#define _MSK4P 0
// </h>
// <h>Primary DNS Server
// =====================
// <i> Primary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define _pDNS1P 194
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define _pDNS2P 25
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define _pDNS3P 2
// <o>Address byte 4 <0-255>
// <i> Default: 129
#define _pDNS4P 129
// </h>
// <h>Secondary DNS Server
// =======================
// <i> Secondary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define _sDNS1P 194
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define _sDNS2P 25
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define _sDNS3P 2
// <o>Address byte 4 <0-255>
// <i> Default: 130
#define _sDNS4P 130
// </h>
// <e>Logon Authentication
// =======================
// <i> Enable or disable user authentication
#define PPP_AUTHEN 1
// <q>Unsecured password (PAP)
// <i>Allow or use Password Authentication Protocol.
#define PPP_PAPEN 1
// <q>Secured password (CHAP-MD5)
// <i>Request or use Challenge Handshake Authentication
// <i>Protocol with MD5 digest algorithm.
#define PPP_CHAPEN 1
// </e>
// <q>Obtain Client IP address automatically
// =========================================
// <i> This option only applies when PPP Dial-up is used to dial
// <i> to remote PPP Server. If checked, network connection
// <i> dynamically obtains an IP address from remote PPP Server.
#define PPP_GETIP 1
// <q>Use Default Gateway on remote Network
// ========================================
// <i> This option only applies when both Ethernet and PPP Dial-up
// <i> are used. If checked, data that cannot be sent to local LAN
// <i> is forwarded to Dial-up network instead.
#define PPP_DEFGW 1
// <o>Async Control Character Map <0x0-0xffffffff>
// <i> A bit-map of control characters 0-31, which are
// <i> transmitted escaped as a 2 byte sequence.
// <i> For XON/XOFF set this value to: 0x000A 0000
// <i> Default: 0x00000000
#define PPP_ACCM 0x00000000
// <o>LCP Echo Interval in seconds <0-3600>
// <i> If no frames are received within this interval, PPP sends an
// <i> Echo Request and expects an Echo Response from the peer.
// <i> If the response is not received, the link is terminated.
// <i> A value of 0 disables the LCP Echo test.
// <i> Default: 30
#define PPP_ECHOTOUT 30
// <o>Number of Retries <0-20>
// <i> How many times PPP will try to retransmit data
// <i> before giving up. Increase this value for links
// <i> with low baud rates or high latency.
// <i> Default: 3
#define PPP_MAXRETRY 3
// <o>Retry Timeout in seconds <1-10>
// <i> If no response received within this time frame,
// <i> PPP module will try to resend the data again.
// <i> Default: 2
#define PPP_RETRYTOUT 2
// </e>
// <e>SLIP Network Interface
// ========================
// <i> Enable or disable SLIP Network Interface
#define SLIP_ENABLE 0
// <h>IP Address
// =============
// <i> Local Static IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define _IP1S 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define _IP2S 168
// <o>Address byte 3 <0-255>
// <i> Default: 225
#define _IP3S 225
// <o>Address byte 4 <0-255>
// <i> Default: 1
#define _IP4S 1
// </h>
// <h>Subnet mask
// ==============
// <i> Local Subnet mask
// <o>Mask byte 1 <0-255>
// <i> Default: 255
#define _MSK1S 255
// <o>Mask byte 2 <0-255>
// <i> Default: 255
#define _MSK2S 255
// <o>Mask byte 3 <0-255>
// <i> Default: 255
#define _MSK3S 255
// <o>Mask byte 4 <0-255>
// <i> Default: 0
#define _MSK4S 0
// </h>
// <h>Primary DNS Server
// =====================
// <i> Primary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define _pDNS1S 194
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define _pDNS2S 25
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define _pDNS3S 2
// <o>Address byte 4 <0-255>
// <i> Default: 129
#define _pDNS4S 129
// </h>
// <h>Secondary DNS Server
// =======================
// <i> Secondary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define _sDNS1S 194
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define _sDNS2S 25
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define _sDNS3S 2
// <o>Address byte 4 <0-255>
// <i> Default: 130
#define _sDNS4S 130
// </h>
// <q>Use Default Gateway on remote Network
// ========================================
// <i> This option only applies when both Ethernet and SLIP Dial-up
// <i> are used. If checked, data that cannot be sent to local LAN
// <i> is forwarded to Dial-up network instead.
#define SLIP_DEFGW 1
// </e>
// <e>UDP Sockets
// ==============
// <i> Enable or disable UDP Sockets
#define UDP_ENABLE 1
// <o>Number of UDP Sockets <1-20>
// <i> Number of available UDP sockets
// <i> Default: 5
#define UDP_NUMSOCKS 20
// </e>
// <e>TCP Sockets
// ==============
// <i> Enable or disable TCP Sockets
#define TCP_ENABLE 1
// <o>Number of TCP Sockets <1-20>
// <i> Number of available TCP sockets
// <i> Default: 5
#define TCP_NUMSOCKS 10
// <o>Number of Retries <0-20>
// <i> How many times TCP module will try to retransmit data
// <i> before giving up. Increase this value for high-latency
// <i> and low_throughput networks.
// <i> Default: 5
#define TCP_MAXRETRY 20
// <o>Retry Timeout in seconds <1-10>
// <i> If data frame not acknowledged within this time frame,
// <i> TCP module will try to resend the data again.
// <i> Default: 4
#define TCP_RETRYTOUT 4
// <o>Default Connect Timeout in seconds <1-600>
// <i> Default TCP Socket Keep Alive timeout. When it expires
// <i> with no TCP data frame send, TCP Connection is closed.
// <i> Default: 120
#define TCP_DEFTOUT 120
// <o>Maximum Segment Size <536-1460>
// <i> The Maximum Segment Size specifies the maximum
// <i> number of bytes in the TCP segment's Data field.
// <i> Default: 1460
#define TCP_MAXSEGSZ 1460
/* TCP fixed timeouts */
#define TCP_INIT_RETRY_TOUT 1 /* TCP initial Retransmit period in sec. */
#define TCP_SYN_RETRY_TOUT 2 /* TCP SYN frame retransmit period in sec. */
#define TCP_CONRETRY 7 /* Number of retries to establish a conn. */
// </e>
// <e>HTTP Server
// ==============
// <i> Enable or disable HTTP Server
#define HTTP_ENABLE 0
// <o>Number of HTTP Sessions <1-10>
// <i> Number of simultaneously active HTTP Sessions.
// <i> Default: 3
#define HTTP_NUMSESS 3
// <o>Port Number <1-65535>
// <i> Listening port number.
// <i> Default: 80
#define HTTP_PORTNUM 80
// <s.50>Server-Id header
// <i> This value is optional. If specified, it overrides
// <i> the default HTTP Server header from the library.
// <i> Default: ""
#define HTTP_SRVID ""
// <e>Enable User Authentication
// <i> When enabled, the user will have to authenticate
// <i> himself by username and password before accessing
// <i> any page on this Embedded WEB server.
#define HTTP_ENAUTH 1
// <s.20>Authentication Realm
// <i> Default: "Embedded WEB Server"
#define HTTP_AUTHREALM "Embedded WEB Server"
// <s.15>Authentication Username
// <i> Default: "admin"
#define HTTP_AUTHUSER "admin"
// <s.15>Authentication Password
// <i> Default: ""
#define HTTP_AUTHPASSW ""
// </e>
// </e>
// <e>Telnet Server
// ================
// <i> Enable or disable Telnet Server
#define TNET_ENABLE 0
// <o>Number of Telnet Connections <1-10>
// <i> Number of simultaneously active Telnet Connections.
// <i> Default: 1
#define TNET_NUMSESS 1
// <o>Port Number <1-65535>
// <i> Listening port number.
// <i> Default: 23
#define TNET_PORTNUM 23
// <o>Idle Connection Timeout in seconds <0-3600>
// <i> When timeout expires, the connection is closed.
// <i> A value of 0 disables disconnection on timeout.
// <i> Default: 120
#define TNET_IDLETOUT 120
// <q>Disable Echo
// <i> When disabled, the server will not echo
// <i> characters it receives.
// <i> Default: Not disabled
#define TNET_NOECHO 0
// <e>Enable User Authentication
// <i> When enabled, the user will have to authenticate
// <i> himself by username and password before access
// <i> to the system is allowed.
#define TNET_ENAUTH 1
// <s.15>Authentication Username
// <i> Default: "admin"
#define TNET_AUTHUSER "admin"
// <s.15>Authentication Password
// <i> Default: ""
#define TNET_AUTHPASSW ""
// </e>
// </e>
// <e>TFTP Server
// ==============
// <i> Enable or disable TFTP Server
#define TFTP_ENABLE 0
// <o>Number of TFTP Sessions <1-10>
// <i> Number of simultaneously active TFTP Sessions
// <i> Default: 1
#define TFTP_NUMSESS 1
// <o>Port Number <1-65535>
// <i> Listening port number.
// <i> Default: 69
#define TFTP_PORTNUM 69
// <q>Enable Firewall Support
// <i> Use the same Port Number to receive
// <i> requests and send answers to clients.
// <i> Default: Not Enabled
#define TFTP_ENFWALL 0
// <o>Inactive Session Timeout in seconds <5-120>
// <i> When timeout expires TFTP Session is closed.
// <i> Default: 15
#define TFTP_DEFTOUT 15
// <o>Number of Retries <1-10>
// <i> How many times TFTP Server will try to
// <i> retransmit the data before giving up.
// <i> Default: 4
#define TFTP_MAXRETRY 4
// </e>
// <e>TFTP Client
// ==============
// <i> Enable or disable TFTP Client
#define TFTPC_ENABLE 0
// <o>Block Size <128=>128 <256=>256 <512=>512
// <1024=>1024 <1428=>1428
// <i> Size of transfer block in bytes.
// <i> Default: 512
#define TFTPC_BLOCKSZ 512
// <o>Number of Retries <1-10>
// <i> How many times TFTP Client will try to
// <i> retransmit the data before giving up.
// <i> Default: 4
#define TFTPC_MAXRETRY 4
// <o>Retry Timeout <2=>200 ms <5=>500 ms <10=>1 sec
// <20=>2 sec <50=>5 sec <100=>10 sec
// <i> If data frame not acknowledged within this time frame,
// <i> TFTP Client will try to resend the data again.
// <i> Default: 500 ms
#define TFTPC_RETRYTO 5
// </e>
// <e>FTP Server
// ==============
// <i> Enable or disable FTP Server
#define FTP_ENABLE 0
// <o>Number of FTP Sessions <1-10>
// <i> Number of simultaneously active FTP Sessions
// <i> Default: 1
#define FTP_NUMSESS 1
// <o>Port Number <1-65535>
// <i> Listening port number.
// <i> Default: 21
#define FTP_PORTNUM 21
// <s.50>Welcome Message
// <i> This value is optional. If specified,
// <i> it overrides the default welcome message.
// <i> Default: ""
#define FTP_WELMSG ""
// <o>Idle Session Timeout in seconds <0-3600>
// <i> When timeout expires, the connection is closed.
// <i> A value of 0 disables disconnection on timeout.
// <i> Default: 120
#define FTP_IDLETOUT 120
// <e>Enable User Authentication
// <i> When enabled, the user will have to authenticate
// <i> himself by username and password before access
// <i> to the system is allowed.
#define FTP_ENAUTH 1
// <s.15>Authentication Username
// <i> Default: "admin"
#define FTP_AUTHUSER "admin"
// <s.15>Authentication Password
// <i> Default: ""
#define FTP_AUTHPASSW ""
// </e>
// </e>
// <e>FTP Client
// =============
// <i> Enable or disable FTP Client
#define FTPC_ENABLE 0
// <o>Response Timeout in seconds <1-120>
// <i> This is a time for FTP Client to wait for a response from
// <i> the Server. If timeout expires, Client aborts operation.
// <i> Default: 10
#define FTPC_DEFTOUT 10
// <q>Passive mode (PASV)
// <i> The client initiates a data connection to the server.
// <i> Default: Not passive (Active)
#define FTPC_PASVMODE 0
// </e>
// <e>DNS Client
// =============
// <i> Enable or disable DNS Client
#define DNS_ENABLE 1
// <o>Cache Table size <5-100>
// <i> Number of cached DNS host names/IP addresses
// <i> Default: 20
#define DNS_TABSIZE 20
// </e>
// <e>SMTP Client
// ==============
// <i> Enable or disable SMTP Client
#define SMTP_ENABLE 0
// <o>Response Timeout in seconds <5-120>
// <i> This is a time for SMTP Client to wait for a response from
// <i> SMTP Server. If timeout expires, Client aborts operation.
// <i> Default: 20
#define SMTP_DEFTOUT 20
// </e>
// <e>SNMP Agent
// =============
// <i> Enable or disable SNMP Agent
#define SNMP_ENABLE 0
// <s.15>Community Name
// <i> Defines where an SNMP message is destined for.
// <i> Default: "public"
#define SNMP_COMMUNITY "public"
// <o>Port Number <1-65535>
// <i> Listening port number.
// <i> Default: 161
#define SNMP_PORTNUM 161
// <o>Trap Port Number <1-65535>
// <i> Port number for Trap operations.
// <i> Default: 162
#define SNMP_TRAPPORT 162
// <h>Trap Server
// ==============
// <i> Trap Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define SNMP_TRAPIP1 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define SNMP_TRAPIP2 168
// <o>Address byte 3 <0-255>
// <i> Default: 0
#define SNMP_TRAPIP3 0
// <o>Address byte 4 <0-255>
// <i> Default: 100
#define SNMP_TRAPIP4 100
// </h>
// </e>
// <e>BSD Socket Interface
// =======================
// <i> Enable or disable Berkeley Socket Programming Interface
#define BSD_ENABLE 1
// <o>Number of BSD Sockets <1-20>
// <i> Number of available Berkeley Sockets
// <i> Default: 2
#define BSD_NUMSOCKS 10
// <o>Number of Streaming Server Sockets <0-20>
// <i> Defines a number of Streaming (TCP) Server sockets,
// <i> that listen for an incoming connection from the client.
// <i> Default: 1
#define BSD_SRVSOCKS 2
// <o>Receive Timeout in seconds <0-600>
// <i> A timeout for socket receive in blocking mode.
// <i> Timeout value of 0 means indefinite timeout.
// <i> Default: 20
#define BSD_RCVTOUT 20
// <q>Hostname Resolver
// <i> Enable or disable Berkeley style hostname resolver.
#define BSD_GETHOSTEN 1
// </e>
//------------- <<< end of configuration section >>> -----------------------
/*----------------------------------------------------------------------------
* Fatal Error Handler
*---------------------------------------------------------------------------*/
void sys_error (ERROR_CODE code) {
/* This function is called when a fatal error is encountered. The normal */
/* program execution is not possible anymore. Add your crytical error .*/
/* handler code here. */
switch (code) {
case ERR_MEM_ALLOC:
/* Out of memory. */
break;
case ERR_MEM_FREE:
/* Trying to release non existing memory block. */
break;
case ERR_MEM_CORRUPT:
/* Memory Link pointer is Corrupted. */
/* More data written than the size of allocated mem block. */
break;
case ERR_MEM_LOCK:
/* Locked Memory management function (alloc/free) re-entered. */
/* RTX multithread protection malfunctioning, not implemented */
/* or interrupt disable is not functioning correctly. */
break;
case ERR_UDP_ALLOC:
/* Out of UDP Sockets. */
break;
case ERR_TCP_ALLOC:
/* Out of TCP Sockets. */
break;
case ERR_TCP_STATE:
/* TCP State machine in undefined state. */
break;
}
/* End-less loop */
while (1);
}
/*----------------------------------------------------------------------------
* TCPnet Config Functions
*---------------------------------------------------------------------------*/
#define __NET_CONFIG__
#include <Net_lib.c>
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

139
IDE/MDK-ARM/MDK-ARM/config/Net_Debug.c
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@ -1,139 +0,0 @@
/*----------------------------------------------------------------------------
* RL-ARM - TCPnet
*----------------------------------------------------------------------------
* Name: NET_DEBUG.C
* Purpose: Debug Module
* Rev.: V4.60
*----------------------------------------------------------------------------
* This code is part of the RealView Run-Time Library.
* Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved.
*---------------------------------------------------------------------------*/
#include <Net_Config.h>
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
// <q>Print Time Stamp
// ===================
// <i> Enable printing the time-info in debug messages
#define DBG_TIME 1
// <h>TCPnet Debug Definitions
// ===========================
// <o>Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Dynamic Memory debug messages
#define DBG_MEM 1
// <o>Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Ethernet debug messages
#define DBG_ETH 1
// <o>PPP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off PPP debug messages
#define DBG_PPP 0
// <o>SLIP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off SLIP debug messages
#define DBG_SLIP 0
// <o>ARP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off ARP debug messages
#define DBG_ARP 1
// <o>IP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off IP debug messages
#define DBG_IP 1
// <o>ICMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off ICMP debug messages
#define DBG_ICMP 1
// <o>IGMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off IGMP debug messages
#define DBG_IGMP 1
// <o>UDP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off UDP debug messages
#define DBG_UDP 1
// <o>TCP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TCP debug messages
#define DBG_TCP 2
// <o>NBNS Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off NetBIOS Name Service debug messages
#define DBG_NBNS 1
// <o>DHCP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Dynamic Host Configuration debug messages
#define DBG_DHCP 2
// <o>DNS Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Domain Name Service debug messages
#define DBG_DNS 1
// <o>SNMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Simple Network Management debug messages
#define DBG_SNMP 1
// <o>BSD Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off BSD Interface debug messages
#define DBG_BSD 2
// </h>
// <h>Application Debug Definitions
// ================================
// <o>HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Web Server debug messages
#define DBG_HTTP 1
// <o>FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off FTP Server debug messages
#define DBG_FTP 1
// <o>FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off FTP Client debug messages
#define DBG_FTPC 1
// <o>Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Telnet Server debug messages
#define DBG_TNET 1
// <o>TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TFTP Server debug messages
#define DBG_TFTP 1
// <o>TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TFTP Client debug messages
#define DBG_TFTPC 1
// <o>SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off SMTP Client debug messages
#define DBG_SMTP 1
// </h>
//------------- <<< end of configuration section >>> -----------------------
/*--------------------------- init_debug ------------------------------------*/
void init_debug (void) {
/* Add your code to initialize the Debug output. This is usually the */
/* serial interface. The function is called at TCPnet system startup. */
/* You may need to customize also the 'putchar()' function. */
}
/*----------------------------------------------------------------------------
* TCPnet Debug Functions
*---------------------------------------------------------------------------*/
#define __NET_DEBUG__
#include <Net_lib.c>
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

205
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@ -1,205 +0,0 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
*----------------------------------------------------------------------------
* Name: RTX_CONFIG.C
* Purpose: Configuration of RTX Kernel for Cortex-M
* Rev.: V4.60
*----------------------------------------------------------------------------
* This code is part of the RealView Run-Time Library.
* Copyright (c) 2004-2012 KEIL - An ARM Company. All rights reserved.
*---------------------------------------------------------------------------*/
#include <RTL.h>
/*----------------------------------------------------------------------------
* RTX User configuration part BEGIN
*---------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
//
// <h>Task Configuration
// =====================
//
// <o>Number of concurrent running tasks <0-250>
// <i> Define max. number of tasks that will run at the same time.
// <i> Default: 6
#ifndef OS_TASKCNT
#define OS_TASKCNT 6
#endif
// <o>Number of tasks with user-provided stack <0-250>
// <i> Define the number of tasks that will use a bigger stack.
// <i> The memory space for the stack is provided by the user.
// <i> Default: 0
#ifndef OS_PRIVCNT
#define OS_PRIVCNT 2
#endif
// <o>Task stack size [bytes] <20-4096:8><#/4>
// <i> Set the stack size for tasks which is assigned by the system.
// <i> Default: 512
#ifndef OS_STKSIZE
#define OS_STKSIZE 499
#endif
// <q>Check for the stack overflow
// ===============================
// <i> Include the stack checking code for a stack overflow.
// <i> Note that additional code reduces the Kernel performance.
#ifndef OS_STKCHECK
#define OS_STKCHECK 1
#endif
// <q>Run in privileged mode
// =========================
// <i> Run all Tasks in privileged mode.
// <i> Default: Unprivileged
#ifndef OS_RUNPRIV
#define OS_RUNPRIV 1
#endif
// </h>
// <h>Tick Timer Configuration
// =============================
// <o>Hardware timer <0=> Core SysTick <1=> Peripheral Timer
// <i> Define the on-chip timer used as a time-base for RTX.
// <i> Default: Core SysTick
#ifndef OS_TIMER
#define OS_TIMER 0
#endif
// <o>Timer clock value [Hz] <1-1000000000>
// <i> Set the timer clock value for selected timer.
// <i> Default: 6000000 (6MHz)
#ifndef OS_CLOCK
#define OS_CLOCK 120000000
#endif
// <o>Timer tick value [us] <1-1000000>
// <i> Set the timer tick value for selected timer.
// <i> Default: 10000 (10ms)
#ifndef OS_TICK
#define OS_TICK 1000
#endif
// </h>
// <h>System Configuration
// =======================
// <e>Round-Robin Task switching
// =============================
// <i> Enable Round-Robin Task switching.
#ifndef OS_ROBIN
#define OS_ROBIN 1
#endif
// <o>Round-Robin Timeout [ticks] <1-1000>
// <i> Define how long a task will execute before a task switch.
// <i> Default: 5
#ifndef OS_ROBINTOUT
#define OS_ROBINTOUT 5
#endif
// </e>
// <o>Number of user timers <0-250>
// <i> Define max. number of user timers that will run at the same time.
// <i> Default: 0 (User timers disabled)
#ifndef OS_TIMERCNT
#define OS_TIMERCNT 1
#endif
// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
// <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries
// <48=> 48 entries <64=> 64 entries
// <96=> 96 entries
// <i> ISR functions store requests to this buffer,
// <i> when they are called from the iterrupt handler.
// <i> Default: 16 entries
#ifndef OS_FIFOSZ
#define OS_FIFOSZ 16
#endif
// </h>
//------------- <<< end of configuration section >>> -----------------------
// Standard library system mutexes
// ===============================
// Define max. number system mutexes that are used to protect
// the arm standard runtime library. For microlib they are not used.
#ifndef OS_MUTEXCNT
#define OS_MUTEXCNT 8
#endif
/*----------------------------------------------------------------------------
* RTX User configuration part END
*---------------------------------------------------------------------------*/
#define OS_TRV ((U32)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
/*----------------------------------------------------------------------------
* Global Functions
*---------------------------------------------------------------------------*/
/*--------------------------- os_idle_demon ---------------------------------*/
__task void os_idle_demon (void) {
/* The idle demon is a system task, running when no other task is ready */
/* to run. The 'os_xxx' function calls are not allowed from this task. */
for (;;) {
/* HERE: include optional user code to be executed when no task runs.*/
}
}
/*--------------------------- os_tick_init ----------------------------------*/
#if (OS_TIMER != 0)
int os_tick_init (void) {
/* Initialize hardware timer as system tick timer. */
/* ... */
return (-1); /* Return IRQ number of timer (0..239) */
}
#endif
/*--------------------------- os_tick_irqack --------------------------------*/
#if (OS_TIMER != 0)
void os_tick_irqack (void) {
/* Acknowledge timer interrupt. */
/* ... */
}
#endif
/*--------------------------- os_tmr_call -----------------------------------*/
void os_tmr_call (U16 info) {
/* This function is called when the user timer has expired. Parameter */
/* 'info' holds the value, defined when the timer was created. */
/* HERE: include optional user code to be executed on timeout. */
}
/*--------------------------- os_error --------------------------------------*/
void os_error (U32 err_code) {
/* This function is called when a runtime error is detected. Parameter */
/* 'err_code' holds the runtime error code (defined in RTL.H). */
/* HERE: include optional code to be executed on runtime error. */
for (;;);
}
/*----------------------------------------------------------------------------
* RTX Configuration Functions
*---------------------------------------------------------------------------*/
#include <RTX_lib.c>
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

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/******************************************************************************/
/* STM32_SWO.ini: STM32 Debugger Initialization File */
/******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>> //
/******************************************************************************/
/* This file is part of the uVision/ARM development tools. */
/* Copyright (c) 2005-2009 Keil Software. All rights reserved. */
/* This software may only be used under the terms of a valid, current, */
/* end user licence from KEIL for a compatible version of KEIL software */
/* development tools. Nothing else gives you the right to use this software. */
/******************************************************************************/
FUNC void DebugSetup (void) {
// <h> Debug MCU Configuration
// <o1.0> DBG_SLEEP <i> Debug Sleep Mode
// <o1.1> DBG_STOP <i> Debug Stop Mode
// <o1.2> DBG_STANDBY <i> Debug Standby Mode
// <o1.5> TRACE_IOEN <i> Trace I/O Enable
// <o1.6..7> TRACE_MODE <i> Trace Mode
// <0=> Asynchronous
// <1=> Synchronous: TRACEDATA Size 1
// <2=> Synchronous: TRACEDATA Size 2
// <3=> Synchronous: TRACEDATA Size 4
// <o1.8> DBG_IWDG_STOP <i> Independant Watchdog Stopped when Core is halted
// <o1.9> DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
// <o1.10> DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
// <o1.11> DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
// <o1.12> DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
// <o1.13> DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
// <o1.14> DBG_CAN_STOP <i> CAN Stopped when Core is halted
// </h>
_WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR
}
DebugSetup(); // Debugger Setup

419
IDE/MDK-ARM/MDK-ARM/config/startup_stm32f2xx.s
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;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f2xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 18-April-2011
;* Description : STM32F2xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00009000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

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/*----------------------------------------------------------------------------
* RL-ARM - RTX
*----------------------------------------------------------------------------
* Name: RTX_Conf_CM.C
* Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
* Rev.: V4.73
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
#include "cmsis_os.h"
/*----------------------------------------------------------------------------
* RTX User configuration part BEGIN
*---------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
//
// <h>Thread Configuration
// =======================
//
// <o>Number of concurrent running threads <0-250>
// <i> Defines max. number of threads that will run at the same time.
// <i> Default: 6
#ifndef OS_TASKCNT
#define OS_TASKCNT 6
#endif
// <o>Default Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines default stack size for threads with osThreadDef stacksz = 0
// <i> Default: 200
#ifndef OS_STKSIZE
#define OS_STKSIZE 50
#endif
// <o>Main Thread stack size [bytes] <64-32768:8><#/4>
// <i> Defines stack size for main thread.
// <i> Default: 200
#ifndef OS_MAINSTKSIZE
#define OS_MAINSTKSIZE 2000
#endif
// <o>Number of threads with user-provided stack size <0-250>
// <i> Defines the number of threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVCNT
#define OS_PRIVCNT 0
#endif
// <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
// <i> Defines the combined stack size for threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVSTKSIZE
#define OS_PRIVSTKSIZE 0
#endif
// <q>Check for stack overflow
// <i> Includes the stack checking code for stack overflow.
// <i> Note that additional code reduces the Kernel performance.
#ifndef OS_STKCHECK
#define OS_STKCHECK 1
#endif
// <o>Processor mode for thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_RUNPRIV
#define OS_RUNPRIV 1
#endif
// </h>
// <h>RTX Kernel Timer Tick Configuration
// ======================================
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
// <i> Use the Cortex-M SysTick timer as a time-base for RTX.
#ifndef OS_SYSTICK
#define OS_SYSTICK 1
#endif
//
// <o>Timer clock value [Hz] <1-1000000000>
// <i> Defines the timer clock value.
// <i> Default: 12000000 (12MHz)
#ifndef OS_CLOCK
#define OS_CLOCK 12000000
#endif
// <o>Timer tick value [us] <1-1000000>
// <i> Defines the timer tick value.
// <i> Default: 1000 (1ms)
#ifndef OS_TICK
#define OS_TICK 1000
#endif
// </h>
// <h>System Configuration
// =======================
//
// <e>Round-Robin Thread switching
// ===============================
//
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN
#define OS_ROBIN 1
#endif
// <o>Round-Robin Timeout [ticks] <1-1000>
// <i> Defines how long a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBINTOUT
#define OS_ROBINTOUT 5
#endif
// </e>
// <e>User Timers
// ==============
// <i> Enables user Timers
#ifndef OS_TIMERS
#define OS_TIMERS 1
#endif
// <o>Timer Thread Priority
// <1=> Low
// <2=> Below Normal <3=> Normal <4=> Above Normal
// <5=> High
// <6=> Realtime (highest)
// <i> Defines priority for Timer Thread
// <i> Default: High
#ifndef OS_TIMERPRIO
#define OS_TIMERPRIO 5
#endif
// <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines stack size for Timer thread.
// <i> Default: 200
#ifndef OS_TIMERSTKSZ
#define OS_TIMERSTKSZ 50
#endif
// <o>Timer Callback Queue size <1-32>
// <i> Number of concurrent active timer callback functions.
// <i> Default: 4
#ifndef OS_TIMERCBQS
#define OS_TIMERCBQS 4
#endif
// </e>
// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
// <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries
// <48=> 48 entries <64=> 64 entries
// <96=> 96 entries
// <i> ISR functions store requests to this buffer,
// <i> when they are called from the interrupt handler.
// <i> Default: 16 entries
#ifndef OS_FIFOSZ
#define OS_FIFOSZ 16
#endif
// </h>
//------------- <<< end of configuration section >>> -----------------------
// Standard library system mutexes
// ===============================
// Define max. number system mutexes that are used to protect
// the arm standard runtime library. For microlib they are not used.
#ifndef OS_MUTEXCNT
#define OS_MUTEXCNT 8
#endif
/*----------------------------------------------------------------------------
* RTX User configuration part END
*---------------------------------------------------------------------------*/
#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
/*----------------------------------------------------------------------------
* Global Functions
*---------------------------------------------------------------------------*/
/*--------------------------- os_idle_demon ---------------------------------*/
void os_idle_demon (void) {
/* The idle demon is a system thread, running when no other thread is */
/* ready to run. */
for (;;) {
/* HERE: include optional user code to be executed when no thread runs.*/
}
}
#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
/*--------------------------- os_tick_init ----------------------------------*/
// Initialize alternative hardware timer as RTX kernel timer
// Return: IRQ number of the alternative hardware timer
int os_tick_init (void) {
return (-1); /* Return IRQ number of timer (0..239) */
}
/*--------------------------- os_tick_val -----------------------------------*/
// Get alternative hardware timer current value (0 .. OS_TRV)
uint32_t os_tick_val (void) {
return (0);
}
/*--------------------------- os_tick_ovf -----------------------------------*/
// Get alternative hardware timer overflow flag
// Return: 1 - overflow, 0 - no overflow
uint32_t os_tick_ovf (void) {
return (0);
}
/*--------------------------- os_tick_irqack --------------------------------*/
// Acknowledge alternative hardware timer interrupt
void os_tick_irqack (void) {
/* ... */
}
#endif // (OS_SYSTICK == 0)
/*--------------------------- os_error --------------------------------------*/
/* OS Error Codes */
#define OS_ERROR_STACK_OVF 1
#define OS_ERROR_FIFO_OVF 2
#define OS_ERROR_MBX_OVF 3
extern osThreadId svcThreadGetId (void);
void os_error (uint32_t error_code) {
/* This function is called when a runtime error is detected. */
/* Parameter 'error_code' holds the runtime error code. */
/* HERE: include optional code to be executed on runtime error. */
switch (error_code) {
case OS_ERROR_STACK_OVF:
/* Stack overflow detected for the currently running task. */
/* Thread can be identified by calling svcThreadGetId(). */
break;
case OS_ERROR_FIFO_OVF:
/* ISR FIFO Queue buffer overflow detected. */
break;
case OS_ERROR_MBX_OVF:
/* Mailbox overflow detected. */
break;
}
for (;;);
}
/*----------------------------------------------------------------------------
* RTX Configuration Functions
*---------------------------------------------------------------------------*/
#include "RTX_CM_lib.h"
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

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;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f2xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 18-April-2011
;* Description : STM32F2xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00009000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

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/**
******************************************************************************
* @file system_stm32f2xx.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-April-2011
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F2xx devices,
* and is generated by the clock configuration tool
* "STM32f2xx_Clock_Configuration_V1.0.0.xls"
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f2xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
* in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F2xx device revision | Rev B and Y
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 120000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 120000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 240
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 5
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 3
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Enabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f2xx_system
* @{
*/
/** @addtogroup STM32F2xx_System_Private_Includes
* @{
*/
#include "stm32f2xx.h"
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Defines
* @{
*/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM322xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 25
#define PLL_N 240
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 5
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 120000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @Note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
static void SetSysClock(void)
{
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
/**
* @brief Setup the external memory controller. Called in startup_stm32f2xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f2xx.s before jump to main.
* This function configures the external SRAM mounted on STM322xG_EVAL board
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
| PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
| PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+
+-------------------+--------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR = 0x00000078;
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcc0ccccc;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xa2aa0a0a;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xf3ff0f0f;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xc00000cc;
GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xaaaa800a;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xffffc00f;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xaa000aaa;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xff000fff;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00080aaa;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000c0fff;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR = 0x00000001;
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010400;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 0;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 4;
p.FSMC_BusTurnAroundDuration = 1;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
*/
}
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::File System
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: FS_Config.c
* Purpose: File System Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>File System
// <i>Define File System global parameters
// <o>Number of open files <4-16>
// <i>Define number of files that can be
// <i>opened at the same time.
// <i>Default: 8
#define NUM_FILES 8
// <o>FAT Name Cache Size <0-1000000>
// <i>Define number of cached FAT file or directory names.
// <i>48 bytes of RAM is required for each cached name.
#define FAT_NAME_CACHE_SIZE 0
// <e>Relocate FAT Name Cache Buffer
// <i>Locate Cache Buffer at a specific address.
#define FAT_NAME_CACHE_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define the Cache buffer base address.
#define FAT_NAME_CACHE_ADDR 0x60000000
// </e>
// </h>
#include "..\RTE_Components.h"
#ifdef RTE_FileSystem_Drive_RAM
#include "FS_Config_RAM.h"
#endif
#ifdef RTE_FileSystem_Drive_NOR_0
#include "FS_Config_NOR_0.h"
#endif
#ifdef RTE_FileSystem_Drive_NOR_1
#include "FS_Config_NOR_1.h"
#endif
#ifdef RTE_FileSystem_Drive_NAND_0
#include "FS_Config_NAND_0.h"
#endif
#ifdef RTE_FileSystem_Drive_NAND_1
#include "FS_Config_NAND_1.h"
#endif
#ifdef RTE_FileSystem_Drive_MC_0
#include "FS_Config_MC_0.h"
#endif
#ifdef RTE_FileSystem_Drive_MC_1
#include "FS_Config_MC_1.h"
#endif
#ifdef RTE_FileSystem_Drive_USB_0
#include "FS_Config_USB_0.h"
#endif
#ifdef RTE_FileSystem_Drive_USB_1
#include "FS_Config_USB_1.h"
#endif
#include "fs_config.h"

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::File System:Drive
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: FS_Config_MC_0.h
* Purpose: File System Configuration for Memory Card Drive
* Rev.: V5.01
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Memory Card Drive 0
// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
#define MC0_ENABLE 1
// <o>Connect to hardware via Driver_MCI# <0-255>
// <i>Select driver control block for hardware interface
#define MC0_MCI_DRIVER 0
// <o>Connect to hardware via Driver_SPI# <0-255>
// <i>Select driver control block for hardware interface when in SPI mode
#define MC0_SPI_DRIVER 0
// <o>Memory Card Interface Mode <0=>Native <1=>SPI
// <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
// <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
// <i>When using SPI both Driver_SPI# and Driver_MCI# must be specified
// <i>since the MCI driver provides the control interface lines.
#define MC0_SPI 0
// <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Drive Cache stores data sectors and may be increased to speed-up
// <i>file read/write operations on this drive (default: 4 KB)
#define MC0_CACHE_SIZE 4
// <e>Locate Drive Cache and Drive Buffer
// <i>Some microcontrollers support DMA only in specific memory areas and
// <i>require to locate the drive buffers at a fixed address.
#define MC0_CACHE_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Set buffer base address to RAM areas that support DMA with the drive.
#define MC0_CACHE_ADDR 0x7FD00000
// </e>
// <q>Use FAT Journal
// <i>Protect File Allocation Table and Directory Entries for
// <i>fail-safe operation.
#define MC0_FAT_JOURNAL 0
// <q>Default Drive "M0:"
// <i>Use this drive when no drive letter is specified.
#define MC0_DEFAULT_DRIVE 1
// </h>

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/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'CryptBenchmark'
* Target: 'CryptBenchmark'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */
#define RTE_Drivers_MCI0 /* Driver MCI0 */
#define RTE_FileSystem_Core /* File System Core */
#define RTE_FileSystem_LFN /* File System with Long Filename support */
#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */
#endif /* RTE_COMPONENTS_H */

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/* config-FS.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// <<< Use Configuration Wizard in Context Menu >>>
// <h> wolfCrypt Configuration
// <h>Cert/Key Strage
// <o>Cert Storage <0=> SD Card <1=> Mem Buff (1024bytes) <2=> Mem Buff (2048bytes)
#define MDK_CONF_CERT_BUFF 0
#if MDK_CONF_CERT_BUFF== 1
#define USE_CERT_BUFFERS_1024
#elif MDK_CONF_CERT_BUFF == 2
#define USE_CERT_BUFFERS_2048
#endif
//</h>
// <h>Crypt Algrithm
// <h>MD5, SHA, SHA-256, AES, RC4, ASN, RSA
// </h>
// <e>MD2
#define MDK_CONF_MD2 0
#if MDK_CONF_MD2 == 1
#define CYASSL_MD2
#endif
// </e>
// <e>MD4
#define MDK_CONF_MD4 1
#if MDK_CONF_MD4 == 0
#define NO_MD4
#endif
// </e>
// <e>SHA-384
// <i>This has to be with SHA512
#define MDK_CONF_SHA384 0
#if MDK_CONF_SHA384 == 1
#define CYASSL_SHA384
#endif
// </e>
// <e>SHA-512
#define MDK_CONF_SHA512 0
#if MDK_CONF_SHA512 == 1
#define CYASSL_SHA512
#endif
// </e>
// <e>RIPEMD
#define MDK_CONF_RIPEMD 0
#if MDK_CONF_RIPEMD == 1
#define CYASSL_RIPEMD
#endif
// </e>
// <e>HMAC
#define MDK_CONF_HMAC 1
#if MDK_CONF_HMAC == 0
#define NO_HMAC
#endif
// </e>
// <e>HC128
#define MDK_CONF_HC128 0
#if MDK_CONF_HC128 == 1
#define HAVE_HC128
#endif
// </e>
// <e>RABBIT
#define MDK_CONF_RABBIT 1
#if MDK_CONF_RABBI == 0
#define NO_RABBIT
#endif
// </e>
// <e>AEAD
#define MDK_CONF_AEAD 0
#if MDK_CONF_AEAD == 1
#define HAVE_AEAD
#endif
// </e>
// <e>DES3
#define MDK_CONF_DES3 1
#if MDK_CONF_DES3 == 0
#define NO_DES3
#endif
// </e>
// <e>CAMELLIA
#define MDK_CONF_CAMELLIA 0
#if MDK_CONF_CAMELLIA == 1
#define HAVE_CAMELLIA
#endif
// </e>
// <e>DH
// <i>need this for CYASSL_SERVER, OPENSSL_EXTRA
#define MDK_CONF_DH 1
#if MDK_CONF_DH == 0
#define NO_DH
#endif
// </e>
// <e>DSA
#define MDK_CONF_DSA 1
#if MDK_CONF_DSA == 0
#define NO_DSA
#endif
// </e>
// <e>PWDBASED
#define MDK_CONF_PWDBASED 1
#if MDK_CONF_PWDBASED == 0
#define NO_PWDBASED
#endif
// </e>
// <e>ECC
#define MDK_CONF_ECC 0
#if MDK_CONF_ECC == 1
#define HAVE_ECC
#endif
// </e>
// <e>PSK
#define MDK_CONF_PSK 1
#if MDK_CONF_PSK == 0
#define NO_PSK
#endif
// </e>
// <e>AESCCM (Turn off Hardware Crypt)
#define MDK_CONF_AESCCM 0
#if MDK_CONF_AESCCM == 1
#define HAVE_AESCCM
#endif
// </e>
// <e>AESGCM (Turn off Hardware Crypt)
#define MDK_CONF_AESGCM 0
#if MDK_CONF_AESGCM == 1
#define HAVE_AESGCM
#define BUILD_AESGCM
#endif
// </e>
// <e>NTRU (need License, "crypto_ntru.h")
#define MDK_CONF_NTRU 0
#if MDK_CONF_NTRU == 1
#define HAVE_NTRU
#endif
// </e>
// </h>
// <h>Hardware Crypt (See document for usage)
// <e>Hardware RNG
#define MDK_CONF_STM32F2_RNG 0
#if MDK_CONF_STM32F2_RNG == 1
#define STM32F2_RNG
#else
#endif
// </e>
// <e>Hardware Crypt
#define MDK_CONF_STM32F2_CRYPTO 0
#if MDK_CONF_STM32F2_CRYPTO == 1
#define STM32F2_CRYPTO
#endif
// </e>
// </h>
//</h>
// <<< end of configuration section >>>

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/* settings.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* Place OS specific preprocessor flags, defines, includes here, will be
included into every file because types.h includes it */
#ifndef CTAO_CRYPT_SETTINGS_H
#define CTAO_CRYPT_SETTINGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Uncomment next line if using IPHONE */
/* #define IPHONE */
/* Uncomment next line if using ThreadX */
/* #define THREADX */
/* Uncomment next line if using Micrium ucOS */
/* #define MICRIUM */
/* Uncomment next line if using Mbed */
/* #define MBED */
/* Uncomment next line if using Microchip PIC32 ethernet starter kit */
/* #define MICROCHIP_PIC32 */
/* Uncomment next line if using Microchip TCP/IP stack, version 5 */
/* #define MICROCHIP_TCPIP_V5 */
/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */
/* #define MICROCHIP_TCPIP */
/* Uncomment next line if using PIC32MZ Crypto Engine */
/* #define CYASSL_MICROCHIP_PIC32MZ */
/* Uncomment next line if using FreeRTOS */
/* #define FREERTOS */
/* Uncomment next line if using FreeRTOS Windows Simulator */
/* #define FREERTOS_WINSIM */
/* Uncomment next line if using RTIP */
/* #define EBSNET */
/* Uncomment next line if using lwip */
/* #define CYASSL_LWIP */
/* Uncomment next line if building CyaSSL for a game console */
/* #define CYASSL_GAME_BUILD */
/* Uncomment next line if building CyaSSL for LSR */
/* #define CYASSL_LSR */
/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */
/* #define FREESCALE_MQX */
/* Uncomment next line if using STM32F2 */
/* #define CYASSL_STM32F2 */
/* Uncomment next line if using Comverge settings */
/* #define COMVERGE */
/* Uncomment next line if using QL SEP settings */
/* #define CYASSL_QL */
/* Uncomment next line if using LwIP native TCP socket settings */
/* #define HAVE_LWIP_NATIVE */
/* Uncomment next line if building for EROAD */
/* #define CYASSL_EROAD */
#include <cyassl/ctaocrypt/visibility.h>
#ifdef IPHONE
#define SIZEOF_LONG_LONG 8
#endif
#ifdef CYASSL_USER_SETTINGS
#include <user_settings.h>
#endif
#ifdef COMVERGE
#define THREADX
#define HAVE_NETX
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define NO_RSA
#define NO_SESSION_CACHE
#define HAVE_ECC
#endif
#ifdef THREADX
#define SIZEOF_LONG_LONG 8
#endif
#ifdef HAVE_NETX
#include "nx_api.h"
#endif
#if defined(HAVE_LWIP_NATIVE) /* using LwIP native TCP socket */
#define CYASSL_LWIP
#define NO_WRITEV
#define SINGLE_THREADED
#define CYASSL_USER_IO
#define NO_FILESYSTEM
#endif
#ifdef MICROCHIP_PIC32
/* #define CYASSL_MICROCHIP_PIC32MZ */
#define SIZEOF_LONG_LONG 8
#define SINGLE_THREADED
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#endif
#ifdef CYASSL_MICROCHIP_PIC32MZ
#define CYASSL_PIC32MZ_CE
#define CYASSL_PIC32MZ_CRYPT
#define HAVE_AES_ENGINE
#define CYASSL_PIC32MZ_RNG
/* #define CYASSL_PIC32MZ_HASH */
#define CYASSL_AES_COUNTER
#define HAVE_AESGCM
#define NO_BIG_INT
#endif
#ifdef MICROCHIP_TCPIP_V5
/* include timer functions */
#include "TCPIP Stack/TCPIP.h"
#endif
#ifdef MICROCHIP_TCPIP
/* include timer, NTP functions */
#ifdef MICROCHIP_MPLAB_HARMONY
#include "tcpip/tcpip.h"
#else
#include "system/system_services.h"
#include "tcpip/sntp.h"
#endif
#endif
#ifdef MBED
#define CYASSL_USER_IO
#define NO_FILESYSTEM
#define NO_CERT
#define USE_CERT_BUFFERS_1024
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define HAVE_ECC
#define NO_SESSION_CACHE
#define CYASSL_CMSIS_RTOS
#endif
#ifdef CYASSL_EROAD
#define FREESCALE_MQX
#define FREESCALE_MMCAU
#define SINGLE_THREADED
#define NO_STDIO_FILESYSTEM
#define CYASSL_LEANPSK
#define HAVE_NULL_CIPHER
#define NO_OLD_TLS
#define NO_ASN
#define NO_BIG_INT
#define NO_RSA
#define NO_DSA
#define NO_DH
#define NO_CERTS
#define NO_PWDBASED
#define NO_DES3
#define NO_MD4
#define NO_RC4
#define NO_MD5
#define NO_SESSION_CACHE
#define NO_MAIN_DRIVER
#endif
#ifdef FREERTOS_WINSIM
#define FREERTOS
#define USE_WINDOWS_API
#endif
/* Micrium will use Visual Studio for compilation but not the Win32 API */
#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \
&& !defined(EBSNET) && !defined(CYASSL_EROAD)
#define USE_WINDOWS_API
#endif
#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER)
#include <stdlib.h>
#define XMALLOC(s, h, type) malloc((s))
#define XFREE(p, h, type) free((p))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif
#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL)
#undef XMALLOC
#define XMALLOC yaXMALLOC
#undef XFREE
#define XFREE yaXFREE
#undef XREALLOC
#define XREALLOC yaXREALLOC
#endif
#ifdef FREERTOS
#ifndef NO_WRITEV
#define NO_WRITEV
#endif
#ifndef NO_SHA512
#define NO_SHA512
#endif
#ifndef NO_DH
#define NO_DH
#endif
#ifndef NO_DSA
#define NO_DSA
#endif
#ifndef NO_HC128
#define NO_HC128
#endif
#ifndef SINGLE_THREADED
#include "FreeRTOS.h"
#include "semphr.h"
#endif
#endif
#ifdef EBSNET
#include "rtip.h"
/* #define DEBUG_CYASSL */
#define NO_CYASSL_DIR /* tbd */
#if (POLLOS)
#define SINGLE_THREADED
#endif
#if (RTPLATFORM)
#if (!RTP_LITTLE_ENDIAN)
#define BIG_ENDIAN_ORDER
#endif
#else
#if (!KS_LITTLE_ENDIAN)
#define BIG_ENDIAN_ORDER
#endif
#endif
#if (WINMSP3)
#undef SIZEOF_LONG
#define SIZEOF_LONG_LONG 8
#else
#sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG
#endif
#define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC))
#define XFREE(p, h, type) (rtp_free(p))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif /* EBSNET */
#ifdef CYASSL_GAME_BUILD
#define SIZEOF_LONG_LONG 8
#if defined(__PPU) || defined(__XENON)
#define BIG_ENDIAN_ORDER
#endif
#endif
#ifdef CYASSL_LSR
#define HAVE_WEBSERVER
#define SIZEOF_LONG_LONG 8
#define CYASSL_LOW_MEMORY
#define NO_WRITEV
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define NO_DEV_RANDOM
#define NO_CYASSL_DIR
#define NO_RABBIT
#ifndef NO_FILESYSTEM
#define LSR_FS
#include "inc/hw_types.h"
#include "fs.h"
#endif
#define CYASSL_LWIP
#include <errno.h> /* for tcp errno */
#define CYASSL_SAFERTOS
#if defined(__IAR_SYSTEMS_ICC__)
/* enum uses enum */
#pragma diag_suppress=Pa089
#endif
#endif
#ifdef CYASSL_SAFERTOS
#ifndef SINGLE_THREADED
#include "SafeRTOS/semphr.h"
#endif
#include "SafeRTOS/heap.h"
#define XMALLOC(s, h, type) pvPortMalloc((s))
#define XFREE(p, h, type) vPortFree((p))
#define XREALLOC(p, n, h, t) pvPortRealloc((p), (n))
#endif
#ifdef CYASSL_LOW_MEMORY
#undef RSA_LOW_MEM
#define RSA_LOW_MEM
#undef CYASSL_SMALL_STACK
#define CYASSL_SMALL_STACK
#undef TFM_TIMING_RESISTANT
#define TFM_TIMING_RESISTANT
#endif
#ifdef FREESCALE_MQX
#define SIZEOF_LONG_LONG 8
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_RABBIT
#define NO_CYASSL_DIR
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#define FREESCALE_K70_RNGA
/* #define FREESCALE_K53_RNGB */
#include "mqx.h"
#ifndef NO_FILESYSTEM
#include "mfs.h"
#include "fio.h"
#endif
#ifndef SINGLE_THREADED
#include "mutex.h"
#endif
#define XMALLOC(s, h, t) (void *)_mem_alloc_system((s))
#define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));}
/* Note: MQX has no realloc, using fastmath above */
#endif
#ifdef CYASSL_STM32F2
#define SIZEOF_LONG_LONG 8
#define NO_DEV_RANDOM
#define NO_CYASSL_DIR
#define NO_RABBIT
#define STM32F2_RNG
#define STM32F2_CRYPTO
#define KEIL_INTRINSICS
#endif
#ifdef MICRIUM
#include "stdlib.h"
#include "net_cfg.h"
#include "ssl_cfg.h"
#include "net_secure_os.h"
#define CYASSL_TYPES
typedef CPU_INT08U byte;
typedef CPU_INT16U word16;
typedef CPU_INT32U word32;
#if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32)
#define SIZEOF_LONG 4
#undef SIZEOF_LONG_LONG
#else
#undef SIZEOF_LONG
#define SIZEOF_LONG_LONG 8
#endif
#define STRING_USER
#define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr)))
#define XSTRNCPY(pstr_dest, pstr_src, len_max) \
((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \
(CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max)))
#define XSTRNCMP(pstr_1, pstr_2, len_max) \
((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \
(CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max)))
#define XSTRSTR(pstr, pstr_srch) \
((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \
(CPU_CHAR *)(pstr_srch)))
#define XMEMSET(pmem, data_val, size) \
((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \
(CPU_SIZE_T)(size)))
#define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \
(void *)(psrc), (CPU_SIZE_T)(size)))
#define XMEMCMP(pmem_1, pmem_2, size) \
(((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \
(CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES)
#define XMEMMOVE XMEMCPY
#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
#define MICRIUM_MALLOC
#define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \
(CPU_SIZE_T)(s), (void *)0))
#define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \
(p), (void *)0))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif
#if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED)
#undef NO_FILESYSTEM
#else
#define NO_FILESYSTEM
#endif
#if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG)
#define DEBUG_CYASSL
#else
#undef DEBUG_CYASSL
#endif
#if (SSL_CFG_OPENSSL_EN == DEF_ENABLED)
#define OPENSSL_EXTRA
#else
#undef OPENSSL_EXTRA
#endif
#if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED)
#undef SINGLE_THREADED
#else
#define SINGLE_THREADED
#endif
#if (SSL_CFG_DH_EN == DEF_ENABLED)
#undef NO_DH
#else
#define NO_DH
#endif
#if (SSL_CFG_DSA_EN == DEF_ENABLED)
#undef NO_DSA
#else
#define NO_DSA
#endif
#if (SSL_CFG_PSK_EN == DEF_ENABLED)
#undef NO_PSK
#else
#define NO_PSK
#endif
#if (SSL_CFG_3DES_EN == DEF_ENABLED)
#undef NO_DES
#else
#define NO_DES
#endif
#if (SSL_CFG_AES_EN == DEF_ENABLED)
#undef NO_AES
#else
#define NO_AES
#endif
#if (SSL_CFG_RC4_EN == DEF_ENABLED)
#undef NO_RC4
#else
#define NO_RC4
#endif
#if (SSL_CFG_RABBIT_EN == DEF_ENABLED)
#undef NO_RABBIT
#else
#define NO_RABBIT
#endif
#if (SSL_CFG_HC128_EN == DEF_ENABLED)
#undef NO_HC128
#else
#define NO_HC128
#endif
#if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
#define BIG_ENDIAN_ORDER
#else
#undef BIG_ENDIAN_ORDER
#define LITTLE_ENDIAN_ORDER
#endif
#if (SSL_CFG_MD4_EN == DEF_ENABLED)
#undef NO_MD4
#else
#define NO_MD4
#endif
#if (SSL_CFG_WRITEV_EN == DEF_ENABLED)
#undef NO_WRITEV
#else
#define NO_WRITEV
#endif
#if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED)
#define NO_DEV_RANDOM
#else
#undef NO_DEV_RANDOM
#endif
#if (SSL_CFG_USER_IO_EN == DEF_ENABLED)
#define CYASSL_USER_IO
#else
#undef CYASSL_USER_IO
#endif
#if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED)
#undef LARGE_STATIC_BUFFERS
#undef STATIC_CHUNKS_ONLY
#else
#define LARGE_STATIC_BUFFERS
#define STATIC_CHUNKS_ONLY
#endif
#if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED)
#define CYASSL_DER_LOAD
#else
#undef CYASSL_DER_LOAD
#endif
#if (SSL_CFG_DTLS_EN == DEF_ENABLED)
#define CYASSL_DTLS
#else
#undef CYASSL_DTLS
#endif
#if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED)
#define CYASSL_CALLBACKS
#else
#undef CYASSL_CALLBACKS
#endif
#if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED)
#define USE_FAST_MATH
#else
#undef USE_FAST_MATH
#endif
#if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED)
#define TFM_TIMING_RESISTANT
#else
#undef TFM_TIMING_RESISTANT
#endif
#endif /* MICRIUM */
#ifdef CYASSL_QL
#ifndef CYASSL_SEP
#define CYASSL_SEP
#endif
#ifndef OPENSSL_EXTRA
#define OPENSSL_EXTRA
#endif
#ifndef SESSION_CERTS
#define SESSION_CERTS
#endif
#ifndef HAVE_AESCCM
#define HAVE_AESCCM
#endif
#ifndef ATOMIC_USER
#define ATOMIC_USER
#endif
#ifndef CYASSL_DER_LOAD
#define CYASSL_DER_LOAD
#endif
#ifndef KEEP_PEER_CERT
#define KEEP_PEER_CERT
#endif
#ifndef HAVE_ECC
#define HAVE_ECC
#endif
#ifndef SESSION_INDEX
#define SESSION_INDEX
#endif
#endif /* CYASSL_QL */
#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \
!defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY)
#define USE_CYASSL_MEMORY
#endif
#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS)
#undef KEEP_PEER_CERT
#define KEEP_PEER_CERT
#endif
/* stream ciphers except arc4 need 32bit alignment, intel ok without */
#ifndef XSTREAM_ALIGNMENT
#if defined(__x86_64__) || defined(__ia64__) || defined(__i386__)
#define NO_XSTREAM_ALIGNMENT
#else
#define XSTREAM_ALIGNMENT
#endif
#endif
/* if using hardware crypto and have alignment requirements, specify the
requirement here. The record header of SSL/TLS will prvent easy alignment.
This hint tries to help as much as possible. */
#ifndef CYASSL_GENERAL_ALIGNMENT
#ifdef CYASSL_AESNI
#define CYASSL_GENERAL_ALIGNMENT 16
#elif defined(XSTREAM_ALIGNMENT)
#define CYASSL_GENERAL_ALIGNMENT 4
#else
#define CYASSL_GENERAL_ALIGNMENT 0
#endif
#endif
#ifdef HAVE_CRL
/* not widely supported yet */
#undef NO_SKID
#define NO_SKID
#endif
/* Place any other flags or defines here */
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* CTAO_CRYPT_SETTINGS_H */

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/******************************************************************************/
/* STM32_SWO.ini: STM32 Debugger Initialization File */
/******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>> //
/******************************************************************************/
/* This file is part of the uVision/ARM development tools. */
/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */
/* This software may only be used under the terms of a valid, current, */
/* end user licence from KEIL for a compatible version of KEIL software */
/* development tools. Nothing else gives you the right to use this software. */
/******************************************************************************/
FUNC void DebugSetup (void) {
// <h> Debug MCU Configuration
// <o1.0> DBG_SLEEP <i> Debug Sleep Mode
// <o1.1> DBG_STOP <i> Debug Stop Mode
// <o1.2> DBG_STANDBY <i> Debug Standby Mode
// <o1.5> TRACE_IOEN <i> Trace I/O Enable
// <o1.6..7> TRACE_MODE <i> Trace Mode
// <0=> Asynchronous
// <1=> Synchronous: TRACEDATA Size 1
// <2=> Synchronous: TRACEDATA Size 2
// <3=> Synchronous: TRACEDATA Size 4
// <o1.8> DBG_IWDG_STOP <i> Independant Watchdog Stopped when Core is halted
// <o1.9> DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
// <o1.10> DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
// <o1.11> DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
// <o1.12> DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
// <o1.13> DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
// <o1.14> DBG_CAN_STOP <i> CAN Stopped when Core is halted
// </h>
_WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR
}
DebugSetup(); // Debugger Setup

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/*----------------------------------------------------------------------------
* RL-ARM - RTX
*----------------------------------------------------------------------------
* Name: RTX_Conf_CM.C
* Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
* Rev.: V4.73
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
#include "cmsis_os.h"
/*----------------------------------------------------------------------------
* RTX User configuration part BEGIN
*---------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
//
// <h>Thread Configuration
// =======================
//
// <o>Number of concurrent running threads <0-250>
// <i> Defines max. number of threads that will run at the same time.
// <i> Default: 6
#ifndef OS_TASKCNT
#define OS_TASKCNT 6
#endif
// <o>Default Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines default stack size for threads with osThreadDef stacksz = 0
// <i> Default: 200
#ifndef OS_STKSIZE
#define OS_STKSIZE 50
#endif
// <o>Main Thread stack size [bytes] <64-32768:8><#/4>
// <i> Defines stack size for main thread.
// <i> Default: 200
#ifndef OS_MAINSTKSIZE
#define OS_MAINSTKSIZE 2000
#endif
// <o>Number of threads with user-provided stack size <0-250>
// <i> Defines the number of threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVCNT
#define OS_PRIVCNT 0
#endif
// <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
// <i> Defines the combined stack size for threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVSTKSIZE
#define OS_PRIVSTKSIZE 0
#endif
// <q>Check for stack overflow
// <i> Includes the stack checking code for stack overflow.
// <i> Note that additional code reduces the Kernel performance.
#ifndef OS_STKCHECK
#define OS_STKCHECK 1
#endif
// <o>Processor mode for thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_RUNPRIV
#define OS_RUNPRIV 1
#endif
// </h>
// <h>RTX Kernel Timer Tick Configuration
// ======================================
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
// <i> Use the Cortex-M SysTick timer as a time-base for RTX.
#ifndef OS_SYSTICK
#define OS_SYSTICK 1
#endif
//
// <o>Timer clock value [Hz] <1-1000000000>
// <i> Defines the timer clock value.
// <i> Default: 12000000 (12MHz)
#ifndef OS_CLOCK
#define OS_CLOCK 12000000
#endif
// <o>Timer tick value [us] <1-1000000>
// <i> Defines the timer tick value.
// <i> Default: 1000 (1ms)
#ifndef OS_TICK
#define OS_TICK 1000
#endif
// </h>
// <h>System Configuration
// =======================
//
// <e>Round-Robin Thread switching
// ===============================
//
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN
#define OS_ROBIN 1
#endif
// <o>Round-Robin Timeout [ticks] <1-1000>
// <i> Defines how long a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBINTOUT
#define OS_ROBINTOUT 5
#endif
// </e>
// <e>User Timers
// ==============
// <i> Enables user Timers
#ifndef OS_TIMERS
#define OS_TIMERS 1
#endif
// <o>Timer Thread Priority
// <1=> Low
// <2=> Below Normal <3=> Normal <4=> Above Normal
// <5=> High
// <6=> Realtime (highest)
// <i> Defines priority for Timer Thread
// <i> Default: High
#ifndef OS_TIMERPRIO
#define OS_TIMERPRIO 5
#endif
// <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines stack size for Timer thread.
// <i> Default: 200
#ifndef OS_TIMERSTKSZ
#define OS_TIMERSTKSZ 50
#endif
// <o>Timer Callback Queue size <1-32>
// <i> Number of concurrent active timer callback functions.
// <i> Default: 4
#ifndef OS_TIMERCBQS
#define OS_TIMERCBQS 4
#endif
// </e>
// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
// <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries
// <48=> 48 entries <64=> 64 entries
// <96=> 96 entries
// <i> ISR functions store requests to this buffer,
// <i> when they are called from the interrupt handler.
// <i> Default: 16 entries
#ifndef OS_FIFOSZ
#define OS_FIFOSZ 16
#endif
// </h>
//------------- <<< end of configuration section >>> -----------------------
// Standard library system mutexes
// ===============================
// Define max. number system mutexes that are used to protect
// the arm standard runtime library. For microlib they are not used.
#ifndef OS_MUTEXCNT
#define OS_MUTEXCNT 8
#endif
/*----------------------------------------------------------------------------
* RTX User configuration part END
*---------------------------------------------------------------------------*/
#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
/*----------------------------------------------------------------------------
* Global Functions
*---------------------------------------------------------------------------*/
/*--------------------------- os_idle_demon ---------------------------------*/
void os_idle_demon (void) {
/* The idle demon is a system thread, running when no other thread is */
/* ready to run. */
for (;;) {
/* HERE: include optional user code to be executed when no thread runs.*/
}
}
#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
/*--------------------------- os_tick_init ----------------------------------*/
// Initialize alternative hardware timer as RTX kernel timer
// Return: IRQ number of the alternative hardware timer
int os_tick_init (void) {
return (-1); /* Return IRQ number of timer (0..239) */
}
/*--------------------------- os_tick_val -----------------------------------*/
// Get alternative hardware timer current value (0 .. OS_TRV)
uint32_t os_tick_val (void) {
return (0);
}
/*--------------------------- os_tick_ovf -----------------------------------*/
// Get alternative hardware timer overflow flag
// Return: 1 - overflow, 0 - no overflow
uint32_t os_tick_ovf (void) {
return (0);
}
/*--------------------------- os_tick_irqack --------------------------------*/
// Acknowledge alternative hardware timer interrupt
void os_tick_irqack (void) {
/* ... */
}
#endif // (OS_SYSTICK == 0)
/*--------------------------- os_error --------------------------------------*/
/* OS Error Codes */
#define OS_ERROR_STACK_OVF 1
#define OS_ERROR_FIFO_OVF 2
#define OS_ERROR_MBX_OVF 3
extern osThreadId svcThreadGetId (void);
void os_error (uint32_t error_code) {
/* This function is called when a runtime error is detected. */
/* Parameter 'error_code' holds the runtime error code. */
/* HERE: include optional code to be executed on runtime error. */
switch (error_code) {
case OS_ERROR_STACK_OVF:
/* Stack overflow detected for the currently running task. */
/* Thread can be identified by calling svcThreadGetId(). */
break;
case OS_ERROR_FIFO_OVF:
/* ISR FIFO Queue buffer overflow detected. */
break;
case OS_ERROR_MBX_OVF:
/* Mailbox overflow detected. */
break;
}
for (;;);
}
/*----------------------------------------------------------------------------
* RTX Configuration Functions
*---------------------------------------------------------------------------*/
#include "RTX_CM_lib.h"
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

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;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f2xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 18-April-2011
;* Description : STM32F2xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00009000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

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/**
******************************************************************************
* @file system_stm32f2xx.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-April-2011
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F2xx devices,
* and is generated by the clock configuration tool
* "STM32f2xx_Clock_Configuration_V1.0.0.xls"
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f2xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
* in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F2xx device revision | Rev B and Y
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 120000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 120000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 240
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 5
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 3
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Enabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f2xx_system
* @{
*/
/** @addtogroup STM32F2xx_System_Private_Includes
* @{
*/
#include "stm32f2xx.h"
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Defines
* @{
*/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM322xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 25
#define PLL_N 240
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 5
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 120000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @Note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
static void SetSysClock(void)
{
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
/**
* @brief Setup the external memory controller. Called in startup_stm32f2xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f2xx.s before jump to main.
* This function configures the external SRAM mounted on STM322xG_EVAL board
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
| PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
| PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+
+-------------------+--------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR = 0x00000078;
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcc0ccccc;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xa2aa0a0a;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xf3ff0f0f;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xc00000cc;
GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xaaaa800a;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xffffc00f;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xaa000aaa;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xff000fff;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00080aaa;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000c0fff;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR = 0x00000001;
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010400;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 0;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 4;
p.FSMC_BusTurnAroundDuration = 1;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
*/
}
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::File System
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: FS_Config.c
* Purpose: File System Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>File System
// <i>Define File System global parameters
// <o>Number of open files <4-16>
// <i>Define number of files that can be
// <i>opened at the same time.
// <i>Default: 8
#define NUM_FILES 8
// <o>FAT Name Cache Size <0-1000000>
// <i>Define number of cached FAT file or directory names.
// <i>48 bytes of RAM is required for each cached name.
#define FAT_NAME_CACHE_SIZE 0
// <e>Relocate FAT Name Cache Buffer
// <i>Locate Cache Buffer at a specific address.
#define FAT_NAME_CACHE_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define the Cache buffer base address.
#define FAT_NAME_CACHE_ADDR 0x60000000
// </e>
// </h>
#include "..\RTE_Components.h"
#ifdef RTE_FileSystem_Drive_RAM
#include "FS_Config_RAM.h"
#endif
#ifdef RTE_FileSystem_Drive_NOR_0
#include "FS_Config_NOR_0.h"
#endif
#ifdef RTE_FileSystem_Drive_NOR_1
#include "FS_Config_NOR_1.h"
#endif
#ifdef RTE_FileSystem_Drive_NAND_0
#include "FS_Config_NAND_0.h"
#endif
#ifdef RTE_FileSystem_Drive_NAND_1
#include "FS_Config_NAND_1.h"
#endif
#ifdef RTE_FileSystem_Drive_MC_0
#include "FS_Config_MC_0.h"
#endif
#ifdef RTE_FileSystem_Drive_MC_1
#include "FS_Config_MC_1.h"
#endif
#ifdef RTE_FileSystem_Drive_USB_0
#include "FS_Config_USB_0.h"
#endif
#ifdef RTE_FileSystem_Drive_USB_1
#include "FS_Config_USB_1.h"
#endif
#include "fs_config.h"

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::File System:Drive
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: FS_Config_MC_0.h
* Purpose: File System Configuration for Memory Card Drive
* Rev.: V5.01
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Memory Card Drive 0
// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
#define MC0_ENABLE 1
// <o>Connect to hardware via Driver_MCI# <0-255>
// <i>Select driver control block for hardware interface
#define MC0_MCI_DRIVER 0
// <o>Connect to hardware via Driver_SPI# <0-255>
// <i>Select driver control block for hardware interface when in SPI mode
#define MC0_SPI_DRIVER 0
// <o>Memory Card Interface Mode <0=>Native <1=>SPI
// <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
// <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
// <i>When using SPI both Driver_SPI# and Driver_MCI# must be specified
// <i>since the MCI driver provides the control interface lines.
#define MC0_SPI 0
// <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Drive Cache stores data sectors and may be increased to speed-up
// <i>file read/write operations on this drive (default: 4 KB)
#define MC0_CACHE_SIZE 4
// <e>Locate Drive Cache and Drive Buffer
// <i>Some microcontrollers support DMA only in specific memory areas and
// <i>require to locate the drive buffers at a fixed address.
#define MC0_CACHE_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Set buffer base address to RAM areas that support DMA with the drive.
#define MC0_CACHE_ADDR 0x7FD00000
// </e>
// <q>Use FAT Journal
// <i>Protect File Allocation Table and Directory Entries for
// <i>fail-safe operation.
#define MC0_FAT_JOURNAL 0
// <q>Default Drive "M0:"
// <i>Use this drive when no drive letter is specified.
#define MC0_DEFAULT_DRIVE 1
// </h>

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/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'CryptTest'
* Target: 'CryptTest'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */
#define RTE_Drivers_MCI0 /* Driver MCI0 */
#define RTE_FileSystem_Core /* File System Core */
#define RTE_FileSystem_LFN /* File System with Long Filename support */
#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */
#endif /* RTE_COMPONENTS_H */

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/* config-FS.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// <<< Use Configuration Wizard in Context Menu >>>
// <h> wolfCrypt Configuration
// <h>Cert/Key Strage
// <o>Cert Storage <0=> SD Card <1=> Mem Buff (1024bytes) <2=> Mem Buff (2048bytes)
#define MDK_CONF_CERT_BUFF 0
#if MDK_CONF_CERT_BUFF== 1
#define USE_CERT_BUFFERS_1024
#elif MDK_CONF_CERT_BUFF == 2
#define USE_CERT_BUFFERS_2048
#endif
//</h>
// <h>Crypt Algrithm
// <h>MD5, SHA, SHA-256, AES, RC4, ASN, RSA
// </h>
// <e>MD2
#define MDK_CONF_MD2 0
#if MDK_CONF_MD2 == 1
#define CYASSL_MD2
#endif
// </e>
// <e>MD4
#define MDK_CONF_MD4 1
#if MDK_CONF_MD4 == 0
#define NO_MD4
#endif
// </e>
// <e>SHA-384
// <i>This has to be with SHA512
#define MDK_CONF_SHA384 0
#if MDK_CONF_SHA384 == 1
#define CYASSL_SHA384
#endif
// </e>
// <e>SHA-512
#define MDK_CONF_SHA512 0
#if MDK_CONF_SHA512 == 1
#define CYASSL_SHA512
#endif
// </e>
// <e>RIPEMD
#define MDK_CONF_RIPEMD 0
#if MDK_CONF_RIPEMD == 1
#define CYASSL_RIPEMD
#endif
// </e>
// <e>HMAC
#define MDK_CONF_HMAC 1
#if MDK_CONF_HMAC == 0
#define NO_HMAC
#endif
// </e>
// <e>HC128
#define MDK_CONF_HC128 0
#if MDK_CONF_HC128 == 1
#define HAVE_HC128
#endif
// </e>
// <e>RABBIT
#define MDK_CONF_RABBIT 1
#if MDK_CONF_RABBI == 0
#define NO_RABBIT
#endif
// </e>
// <e>AEAD
#define MDK_CONF_AEAD 0
#if MDK_CONF_AEAD == 1
#define HAVE_AEAD
#endif
// </e>
// <e>DES3
#define MDK_CONF_DES3 1
#if MDK_CONF_DES3 == 0
#define NO_DES3
#endif
// </e>
// <e>CAMELLIA
#define MDK_CONF_CAMELLIA 0
#if MDK_CONF_CAMELLIA == 1
#define HAVE_CAMELLIA
#endif
// </e>
// <e>DH
// <i>need this for CYASSL_SERVER, OPENSSL_EXTRA
#define MDK_CONF_DH 1
#if MDK_CONF_DH == 0
#define NO_DH
#endif
// </e>
// <e>DSA
#define MDK_CONF_DSA 1
#if MDK_CONF_DSA == 0
#define NO_DSA
#endif
// </e>
// <e>PWDBASED
#define MDK_CONF_PWDBASED 1
#if MDK_CONF_PWDBASED == 0
#define NO_PWDBASED
#endif
// </e>
// <e>ECC
#define MDK_CONF_ECC 0
#if MDK_CONF_ECC == 1
#define HAVE_ECC
#endif
// </e>
// <e>PSK
#define MDK_CONF_PSK 1
#if MDK_CONF_PSK == 0
#define NO_PSK
#endif
// </e>
// <e>AESCCM (Turn off Hardware Crypt)
#define MDK_CONF_AESCCM 0
#if MDK_CONF_AESCCM == 1
#define HAVE_AESCCM
#endif
// </e>
// <e>AESGCM (Turn off Hardware Crypt)
#define MDK_CONF_AESGCM 0
#if MDK_CONF_AESGCM == 1
#define HAVE_AESGCM
#define BUILD_AESGCM
#endif
// </e>
// <e>NTRU (need License, "crypto_ntru.h")
#define MDK_CONF_NTRU 0
#if MDK_CONF_NTRU == 1
#define HAVE_NTRU
#endif
// </e>
// </h>
// <h>Hardware Crypt (See document for usage)
// <e>Hardware RNG
#define MDK_CONF_STM32F2_RNG 0
#if MDK_CONF_STM32F2_RNG == 1
#define STM32F2_RNG
#else
#endif
// </e>
// <e>Hardware Crypt
#define MDK_CONF_STM32F2_CRYPTO 0
#if MDK_CONF_STM32F2_CRYPTO == 1
#define STM32F2_CRYPTO
#endif
// </e>
// </h>
//</h>
// <<< end of configuration section >>>

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/* settings.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* Place OS specific preprocessor flags, defines, includes here, will be
included into every file because types.h includes it */
#ifndef CTAO_CRYPT_SETTINGS_H
#define CTAO_CRYPT_SETTINGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Uncomment next line if using IPHONE */
/* #define IPHONE */
/* Uncomment next line if using ThreadX */
/* #define THREADX */
/* Uncomment next line if using Micrium ucOS */
/* #define MICRIUM */
/* Uncomment next line if using Mbed */
/* #define MBED */
/* Uncomment next line if using Microchip PIC32 ethernet starter kit */
/* #define MICROCHIP_PIC32 */
/* Uncomment next line if using Microchip TCP/IP stack, version 5 */
/* #define MICROCHIP_TCPIP_V5 */
/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */
/* #define MICROCHIP_TCPIP */
/* Uncomment next line if using PIC32MZ Crypto Engine */
/* #define CYASSL_MICROCHIP_PIC32MZ */
/* Uncomment next line if using FreeRTOS */
/* #define FREERTOS */
/* Uncomment next line if using FreeRTOS Windows Simulator */
/* #define FREERTOS_WINSIM */
/* Uncomment next line if using RTIP */
/* #define EBSNET */
/* Uncomment next line if using lwip */
/* #define CYASSL_LWIP */
/* Uncomment next line if building CyaSSL for a game console */
/* #define CYASSL_GAME_BUILD */
/* Uncomment next line if building CyaSSL for LSR */
/* #define CYASSL_LSR */
/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */
/* #define FREESCALE_MQX */
/* Uncomment next line if using STM32F2 */
/* #define CYASSL_STM32F2 */
/* Uncomment next line if using Comverge settings */
/* #define COMVERGE */
/* Uncomment next line if using QL SEP settings */
/* #define CYASSL_QL */
/* Uncomment next line if using LwIP native TCP socket settings */
/* #define HAVE_LWIP_NATIVE */
/* Uncomment next line if building for EROAD */
/* #define CYASSL_EROAD */
#include <cyassl/ctaocrypt/visibility.h>
#ifdef IPHONE
#define SIZEOF_LONG_LONG 8
#endif
#ifdef CYASSL_USER_SETTINGS
#include <user_settings.h>
#endif
#ifdef COMVERGE
#define THREADX
#define HAVE_NETX
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define NO_RSA
#define NO_SESSION_CACHE
#define HAVE_ECC
#endif
#ifdef THREADX
#define SIZEOF_LONG_LONG 8
#endif
#ifdef HAVE_NETX
#include "nx_api.h"
#endif
#if defined(HAVE_LWIP_NATIVE) /* using LwIP native TCP socket */
#define CYASSL_LWIP
#define NO_WRITEV
#define SINGLE_THREADED
#define CYASSL_USER_IO
#define NO_FILESYSTEM
#endif
#ifdef MICROCHIP_PIC32
/* #define CYASSL_MICROCHIP_PIC32MZ */
#define SIZEOF_LONG_LONG 8
#define SINGLE_THREADED
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#endif
#ifdef CYASSL_MICROCHIP_PIC32MZ
#define CYASSL_PIC32MZ_CE
#define CYASSL_PIC32MZ_CRYPT
#define HAVE_AES_ENGINE
#define CYASSL_PIC32MZ_RNG
/* #define CYASSL_PIC32MZ_HASH */
#define CYASSL_AES_COUNTER
#define HAVE_AESGCM
#define NO_BIG_INT
#endif
#ifdef MICROCHIP_TCPIP_V5
/* include timer functions */
#include "TCPIP Stack/TCPIP.h"
#endif
#ifdef MICROCHIP_TCPIP
/* include timer, NTP functions */
#ifdef MICROCHIP_MPLAB_HARMONY
#include "tcpip/tcpip.h"
#else
#include "system/system_services.h"
#include "tcpip/sntp.h"
#endif
#endif
#ifdef MBED
#define CYASSL_USER_IO
#define NO_FILESYSTEM
#define NO_CERT
#define USE_CERT_BUFFERS_1024
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define HAVE_ECC
#define NO_SESSION_CACHE
#define CYASSL_CMSIS_RTOS
#endif
#ifdef CYASSL_EROAD
#define FREESCALE_MQX
#define FREESCALE_MMCAU
#define SINGLE_THREADED
#define NO_STDIO_FILESYSTEM
#define CYASSL_LEANPSK
#define HAVE_NULL_CIPHER
#define NO_OLD_TLS
#define NO_ASN
#define NO_BIG_INT
#define NO_RSA
#define NO_DSA
#define NO_DH
#define NO_CERTS
#define NO_PWDBASED
#define NO_DES3
#define NO_MD4
#define NO_RC4
#define NO_MD5
#define NO_SESSION_CACHE
#define NO_MAIN_DRIVER
#endif
#ifdef FREERTOS_WINSIM
#define FREERTOS
#define USE_WINDOWS_API
#endif
/* Micrium will use Visual Studio for compilation but not the Win32 API */
#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \
&& !defined(EBSNET) && !defined(CYASSL_EROAD)
#define USE_WINDOWS_API
#endif
#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER)
#include <stdlib.h>
#define XMALLOC(s, h, type) malloc((s))
#define XFREE(p, h, type) free((p))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif
#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL)
#undef XMALLOC
#define XMALLOC yaXMALLOC
#undef XFREE
#define XFREE yaXFREE
#undef XREALLOC
#define XREALLOC yaXREALLOC
#endif
#ifdef FREERTOS
#ifndef NO_WRITEV
#define NO_WRITEV
#endif
#ifndef NO_SHA512
#define NO_SHA512
#endif
#ifndef NO_DH
#define NO_DH
#endif
#ifndef NO_DSA
#define NO_DSA
#endif
#ifndef NO_HC128
#define NO_HC128
#endif
#ifndef SINGLE_THREADED
#include "FreeRTOS.h"
#include "semphr.h"
#endif
#endif
#ifdef EBSNET
#include "rtip.h"
/* #define DEBUG_CYASSL */
#define NO_CYASSL_DIR /* tbd */
#if (POLLOS)
#define SINGLE_THREADED
#endif
#if (RTPLATFORM)
#if (!RTP_LITTLE_ENDIAN)
#define BIG_ENDIAN_ORDER
#endif
#else
#if (!KS_LITTLE_ENDIAN)
#define BIG_ENDIAN_ORDER
#endif
#endif
#if (WINMSP3)
#undef SIZEOF_LONG
#define SIZEOF_LONG_LONG 8
#else
#sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG
#endif
#define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC))
#define XFREE(p, h, type) (rtp_free(p))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif /* EBSNET */
#ifdef CYASSL_GAME_BUILD
#define SIZEOF_LONG_LONG 8
#if defined(__PPU) || defined(__XENON)
#define BIG_ENDIAN_ORDER
#endif
#endif
#ifdef CYASSL_LSR
#define HAVE_WEBSERVER
#define SIZEOF_LONG_LONG 8
#define CYASSL_LOW_MEMORY
#define NO_WRITEV
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define NO_DEV_RANDOM
#define NO_CYASSL_DIR
#define NO_RABBIT
#ifndef NO_FILESYSTEM
#define LSR_FS
#include "inc/hw_types.h"
#include "fs.h"
#endif
#define CYASSL_LWIP
#include <errno.h> /* for tcp errno */
#define CYASSL_SAFERTOS
#if defined(__IAR_SYSTEMS_ICC__)
/* enum uses enum */
#pragma diag_suppress=Pa089
#endif
#endif
#ifdef CYASSL_SAFERTOS
#ifndef SINGLE_THREADED
#include "SafeRTOS/semphr.h"
#endif
#include "SafeRTOS/heap.h"
#define XMALLOC(s, h, type) pvPortMalloc((s))
#define XFREE(p, h, type) vPortFree((p))
#define XREALLOC(p, n, h, t) pvPortRealloc((p), (n))
#endif
#ifdef CYASSL_LOW_MEMORY
#undef RSA_LOW_MEM
#define RSA_LOW_MEM
#undef CYASSL_SMALL_STACK
#define CYASSL_SMALL_STACK
#undef TFM_TIMING_RESISTANT
#define TFM_TIMING_RESISTANT
#endif
#ifdef FREESCALE_MQX
#define SIZEOF_LONG_LONG 8
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_RABBIT
#define NO_CYASSL_DIR
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#define FREESCALE_K70_RNGA
/* #define FREESCALE_K53_RNGB */
#include "mqx.h"
#ifndef NO_FILESYSTEM
#include "mfs.h"
#include "fio.h"
#endif
#ifndef SINGLE_THREADED
#include "mutex.h"
#endif
#define XMALLOC(s, h, t) (void *)_mem_alloc_system((s))
#define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));}
/* Note: MQX has no realloc, using fastmath above */
#endif
#ifdef CYASSL_STM32F2
#define SIZEOF_LONG_LONG 8
#define NO_DEV_RANDOM
#define NO_CYASSL_DIR
#define NO_RABBIT
#define STM32F2_RNG
#define STM32F2_CRYPTO
#define KEIL_INTRINSICS
#endif
#ifdef MICRIUM
#include "stdlib.h"
#include "net_cfg.h"
#include "ssl_cfg.h"
#include "net_secure_os.h"
#define CYASSL_TYPES
typedef CPU_INT08U byte;
typedef CPU_INT16U word16;
typedef CPU_INT32U word32;
#if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32)
#define SIZEOF_LONG 4
#undef SIZEOF_LONG_LONG
#else
#undef SIZEOF_LONG
#define SIZEOF_LONG_LONG 8
#endif
#define STRING_USER
#define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr)))
#define XSTRNCPY(pstr_dest, pstr_src, len_max) \
((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \
(CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max)))
#define XSTRNCMP(pstr_1, pstr_2, len_max) \
((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \
(CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max)))
#define XSTRSTR(pstr, pstr_srch) \
((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \
(CPU_CHAR *)(pstr_srch)))
#define XMEMSET(pmem, data_val, size) \
((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \
(CPU_SIZE_T)(size)))
#define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \
(void *)(psrc), (CPU_SIZE_T)(size)))
#define XMEMCMP(pmem_1, pmem_2, size) \
(((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \
(CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES)
#define XMEMMOVE XMEMCPY
#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
#define MICRIUM_MALLOC
#define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \
(CPU_SIZE_T)(s), (void *)0))
#define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \
(p), (void *)0))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif
#if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED)
#undef NO_FILESYSTEM
#else
#define NO_FILESYSTEM
#endif
#if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG)
#define DEBUG_CYASSL
#else
#undef DEBUG_CYASSL
#endif
#if (SSL_CFG_OPENSSL_EN == DEF_ENABLED)
#define OPENSSL_EXTRA
#else
#undef OPENSSL_EXTRA
#endif
#if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED)
#undef SINGLE_THREADED
#else
#define SINGLE_THREADED
#endif
#if (SSL_CFG_DH_EN == DEF_ENABLED)
#undef NO_DH
#else
#define NO_DH
#endif
#if (SSL_CFG_DSA_EN == DEF_ENABLED)
#undef NO_DSA
#else
#define NO_DSA
#endif
#if (SSL_CFG_PSK_EN == DEF_ENABLED)
#undef NO_PSK
#else
#define NO_PSK
#endif
#if (SSL_CFG_3DES_EN == DEF_ENABLED)
#undef NO_DES
#else
#define NO_DES
#endif
#if (SSL_CFG_AES_EN == DEF_ENABLED)
#undef NO_AES
#else
#define NO_AES
#endif
#if (SSL_CFG_RC4_EN == DEF_ENABLED)
#undef NO_RC4
#else
#define NO_RC4
#endif
#if (SSL_CFG_RABBIT_EN == DEF_ENABLED)
#undef NO_RABBIT
#else
#define NO_RABBIT
#endif
#if (SSL_CFG_HC128_EN == DEF_ENABLED)
#undef NO_HC128
#else
#define NO_HC128
#endif
#if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
#define BIG_ENDIAN_ORDER
#else
#undef BIG_ENDIAN_ORDER
#define LITTLE_ENDIAN_ORDER
#endif
#if (SSL_CFG_MD4_EN == DEF_ENABLED)
#undef NO_MD4
#else
#define NO_MD4
#endif
#if (SSL_CFG_WRITEV_EN == DEF_ENABLED)
#undef NO_WRITEV
#else
#define NO_WRITEV
#endif
#if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED)
#define NO_DEV_RANDOM
#else
#undef NO_DEV_RANDOM
#endif
#if (SSL_CFG_USER_IO_EN == DEF_ENABLED)
#define CYASSL_USER_IO
#else
#undef CYASSL_USER_IO
#endif
#if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED)
#undef LARGE_STATIC_BUFFERS
#undef STATIC_CHUNKS_ONLY
#else
#define LARGE_STATIC_BUFFERS
#define STATIC_CHUNKS_ONLY
#endif
#if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED)
#define CYASSL_DER_LOAD
#else
#undef CYASSL_DER_LOAD
#endif
#if (SSL_CFG_DTLS_EN == DEF_ENABLED)
#define CYASSL_DTLS
#else
#undef CYASSL_DTLS
#endif
#if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED)
#define CYASSL_CALLBACKS
#else
#undef CYASSL_CALLBACKS
#endif
#if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED)
#define USE_FAST_MATH
#else
#undef USE_FAST_MATH
#endif
#if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED)
#define TFM_TIMING_RESISTANT
#else
#undef TFM_TIMING_RESISTANT
#endif
#endif /* MICRIUM */
#ifdef CYASSL_QL
#ifndef CYASSL_SEP
#define CYASSL_SEP
#endif
#ifndef OPENSSL_EXTRA
#define OPENSSL_EXTRA
#endif
#ifndef SESSION_CERTS
#define SESSION_CERTS
#endif
#ifndef HAVE_AESCCM
#define HAVE_AESCCM
#endif
#ifndef ATOMIC_USER
#define ATOMIC_USER
#endif
#ifndef CYASSL_DER_LOAD
#define CYASSL_DER_LOAD
#endif
#ifndef KEEP_PEER_CERT
#define KEEP_PEER_CERT
#endif
#ifndef HAVE_ECC
#define HAVE_ECC
#endif
#ifndef SESSION_INDEX
#define SESSION_INDEX
#endif
#endif /* CYASSL_QL */
#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \
!defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY)
#define USE_CYASSL_MEMORY
#endif
#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS)
#undef KEEP_PEER_CERT
#define KEEP_PEER_CERT
#endif
/* stream ciphers except arc4 need 32bit alignment, intel ok without */
#ifndef XSTREAM_ALIGNMENT
#if defined(__x86_64__) || defined(__ia64__) || defined(__i386__)
#define NO_XSTREAM_ALIGNMENT
#else
#define XSTREAM_ALIGNMENT
#endif
#endif
/* if using hardware crypto and have alignment requirements, specify the
requirement here. The record header of SSL/TLS will prvent easy alignment.
This hint tries to help as much as possible. */
#ifndef CYASSL_GENERAL_ALIGNMENT
#ifdef CYASSL_AESNI
#define CYASSL_GENERAL_ALIGNMENT 16
#elif defined(XSTREAM_ALIGNMENT)
#define CYASSL_GENERAL_ALIGNMENT 4
#else
#define CYASSL_GENERAL_ALIGNMENT 0
#endif
#endif
#ifdef HAVE_CRL
/* not widely supported yet */
#undef NO_SKID
#define NO_SKID
#endif
/* Place any other flags or defines here */
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* CTAO_CRYPT_SETTINGS_H */

36
IDE/MDK5-ARM/Projects/CryptTest/STM32_SWO.ini
View File

@ -1,36 +0,0 @@
/******************************************************************************/
/* STM32_SWO.ini: STM32 Debugger Initialization File */
/******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>> //
/******************************************************************************/
/* This file is part of the uVision/ARM development tools. */
/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */
/* This software may only be used under the terms of a valid, current, */
/* end user licence from KEIL for a compatible version of KEIL software */
/* development tools. Nothing else gives you the right to use this software. */
/******************************************************************************/
FUNC void DebugSetup (void) {
// <h> Debug MCU Configuration
// <o1.0> DBG_SLEEP <i> Debug Sleep Mode
// <o1.1> DBG_STOP <i> Debug Stop Mode
// <o1.2> DBG_STANDBY <i> Debug Standby Mode
// <o1.5> TRACE_IOEN <i> Trace I/O Enable
// <o1.6..7> TRACE_MODE <i> Trace Mode
// <0=> Asynchronous
// <1=> Synchronous: TRACEDATA Size 1
// <2=> Synchronous: TRACEDATA Size 2
// <3=> Synchronous: TRACEDATA Size 4
// <o1.8> DBG_IWDG_STOP <i> Independant Watchdog Stopped when Core is halted
// <o1.9> DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
// <o1.10> DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
// <o1.11> DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
// <o1.12> DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
// <o1.13> DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
// <o1.14> DBG_CAN_STOP <i> CAN Stopped when Core is halted
// </h>
_WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR
}
DebugSetup(); // Debugger Setup

295
IDE/MDK5-ARM/Projects/CyaSSL-Full/RTE/CMSIS/RTX_Conf_CM.c
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@ -1,295 +0,0 @@
/*----------------------------------------------------------------------------
* RL-ARM - RTX
*----------------------------------------------------------------------------
* Name: RTX_Conf_CM.C
* Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
* Rev.: V4.73
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
#include "cmsis_os.h"
/*----------------------------------------------------------------------------
* RTX User configuration part BEGIN
*---------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
//
// <h>Thread Configuration
// =======================
//
// <o>Number of concurrent running threads <0-250>
// <i> Defines max. number of threads that will run at the same time.
// <i> Default: 6
#ifndef OS_TASKCNT
#define OS_TASKCNT 6
#endif
// <o>Default Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines default stack size for threads with osThreadDef stacksz = 0
// <i> Default: 200
#ifndef OS_STKSIZE
#define OS_STKSIZE 300
#endif
// <o>Main Thread stack size [bytes] <64-32768:8><#/4>
// <i> Defines stack size for main thread.
// <i> Default: 200
#ifndef OS_MAINSTKSIZE
#define OS_MAINSTKSIZE 1000
#endif
// <o>Number of threads with user-provided stack size <0-250>
// <i> Defines the number of threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVCNT
#define OS_PRIVCNT 0
#endif
// <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
// <i> Defines the combined stack size for threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVSTKSIZE
#define OS_PRIVSTKSIZE 6000
#endif
// <q>Check for stack overflow
// <i> Includes the stack checking code for stack overflow.
// <i> Note that additional code reduces the Kernel performance.
#ifndef OS_STKCHECK
#define OS_STKCHECK 1
#endif
// <o>Processor mode for thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_RUNPRIV
#define OS_RUNPRIV 1
#endif
// </h>
// <h>RTX Kernel Timer Tick Configuration
// ======================================
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
// <i> Use the Cortex-M SysTick timer as a time-base for RTX.
#ifndef OS_SYSTICK
#define OS_SYSTICK 1
#endif
//
// <o>Timer clock value [Hz] <1-1000000000>
// <i> Defines the timer clock value.
// <i> Default: 12000000 (12MHz)
#ifndef OS_CLOCK
#define OS_CLOCK 12000000
#endif
// <o>Timer tick value [us] <1-1000000>
// <i> Defines the timer tick value.
// <i> Default: 1000 (1ms)
#ifndef OS_TICK
#define OS_TICK 1000
#endif
// </h>
// <h>System Configuration
// =======================
//
// <e>Round-Robin Thread switching
// ===============================
//
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN
#define OS_ROBIN 1
#endif
// <o>Round-Robin Timeout [ticks] <1-1000>
// <i> Defines how long a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBINTOUT
#define OS_ROBINTOUT 5
#endif
// </e>
// <e>User Timers
// ==============
// <i> Enables user Timers
#ifndef OS_TIMERS
#define OS_TIMERS 1
#endif
// <o>Timer Thread Priority
// <1=> Low
// <2=> Below Normal <3=> Normal <4=> Above Normal
// <5=> High
// <6=> Realtime (highest)
// <i> Defines priority for Timer Thread
// <i> Default: High
#ifndef OS_TIMERPRIO
#define OS_TIMERPRIO 5
#endif
// <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines stack size for Timer thread.
// <i> Default: 200
#ifndef OS_TIMERSTKSZ
#define OS_TIMERSTKSZ 50
#endif
// <o>Timer Callback Queue size <1-32>
// <i> Number of concurrent active timer callback functions.
// <i> Default: 4
#ifndef OS_TIMERCBQS
#define OS_TIMERCBQS 4
#endif
// </e>
// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
// <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries
// <48=> 48 entries <64=> 64 entries
// <96=> 96 entries
// <i> ISR functions store requests to this buffer,
// <i> when they are called from the interrupt handler.
// <i> Default: 16 entries
#ifndef OS_FIFOSZ
#define OS_FIFOSZ 16
#endif
// </h>
//------------- <<< end of configuration section >>> -----------------------
// Standard library system mutexes
// ===============================
// Define max. number system mutexes that are used to protect
// the arm standard runtime library. For microlib they are not used.
#ifndef OS_MUTEXCNT
#define OS_MUTEXCNT 8
#endif
/*----------------------------------------------------------------------------
* RTX User configuration part END
*---------------------------------------------------------------------------*/
#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
/*----------------------------------------------------------------------------
* Global Functions
*---------------------------------------------------------------------------*/
/*--------------------------- os_idle_demon ---------------------------------*/
void os_idle_demon (void) {
/* The idle demon is a system thread, running when no other thread is */
/* ready to run. */
for (;;) {
/* HERE: include optional user code to be executed when no thread runs.*/
}
}
#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
/*--------------------------- os_tick_init ----------------------------------*/
// Initialize alternative hardware timer as RTX kernel timer
// Return: IRQ number of the alternative hardware timer
int os_tick_init (void) {
return (-1); /* Return IRQ number of timer (0..239) */
}
/*--------------------------- os_tick_val -----------------------------------*/
// Get alternative hardware timer current value (0 .. OS_TRV)
uint32_t os_tick_val (void) {
return (0);
}
/*--------------------------- os_tick_ovf -----------------------------------*/
// Get alternative hardware timer overflow flag
// Return: 1 - overflow, 0 - no overflow
uint32_t os_tick_ovf (void) {
return (0);
}
/*--------------------------- os_tick_irqack --------------------------------*/
// Acknowledge alternative hardware timer interrupt
void os_tick_irqack (void) {
/* ... */
}
#endif // (OS_SYSTICK == 0)
/*--------------------------- os_error --------------------------------------*/
/* OS Error Codes */
#define OS_ERROR_STACK_OVF 1
#define OS_ERROR_FIFO_OVF 2
#define OS_ERROR_MBX_OVF 3
extern osThreadId svcThreadGetId (void);
void os_error (uint32_t error_code) {
/* This function is called when a runtime error is detected. */
/* Parameter 'error_code' holds the runtime error code. */
/* HERE: include optional code to be executed on runtime error. */
switch (error_code) {
case OS_ERROR_STACK_OVF:
/* Stack overflow detected for the currently running task. */
/* Thread can be identified by calling svcThreadGetId(). */
break;
case OS_ERROR_FIFO_OVF:
/* ISR FIFO Queue buffer overflow detected. */
break;
case OS_ERROR_MBX_OVF:
/* Mailbox overflow detected. */
break;
}
for (;;);
}
/*----------------------------------------------------------------------------
* RTX Configuration Functions
*---------------------------------------------------------------------------*/
#include "RTX_CM_lib.h"
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

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;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f2xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 18-April-2011
;* Description : STM32F2xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x0000A000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

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/**
******************************************************************************
* @file system_stm32f2xx.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-April-2011
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F2xx devices,
* and is generated by the clock configuration tool
* "STM32f2xx_Clock_Configuration_V1.0.0.xls"
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f2xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
* in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F2xx device revision | Rev B and Y
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 120000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 120000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 240
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 5
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 3
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Enabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f2xx_system
* @{
*/
/** @addtogroup STM32F2xx_System_Private_Includes
* @{
*/
#include "stm32f2xx.h"
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Defines
* @{
*/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM322xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 25
#define PLL_N 240
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 5
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 120000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @Note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
static void SetSysClock(void)
{
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
/**
* @brief Setup the external memory controller. Called in startup_stm32f2xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f2xx.s before jump to main.
* This function configures the external SRAM mounted on STM322xG_EVAL board
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
| PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
| PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+
+-------------------+--------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR = 0x00000078;
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcc0ccccc;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xa2aa0a0a;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xf3ff0f0f;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xc00000cc;
GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xaaaa800a;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xffffc00f;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xaa000aaa;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xff000fff;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00080aaa;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000c0fff;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR = 0x00000001;
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010400;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 0;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 4;
p.FSMC_BusTurnAroundDuration = 1;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
*/
}
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::File System
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: FS_Config.c
* Purpose: File System Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>File System
// <i>Define File System global parameters
// <o>Number of open files <4-16>
// <i>Define number of files that can be
// <i>opened at the same time.
// <i>Default: 8
#define NUM_FILES 8
// <o>FAT Name Cache Size <0-1000000>
// <i>Define number of cached FAT file or directory names.
// <i>48 bytes of RAM is required for each cached name.
#define FAT_NAME_CACHE_SIZE 0
// <e>Relocate FAT Name Cache Buffer
// <i>Locate Cache Buffer at a specific address.
#define FAT_NAME_CACHE_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define the Cache buffer base address.
#define FAT_NAME_CACHE_ADDR 0x60000000
// </e>
// </h>
#include "..\RTE_Components.h"
#ifdef RTE_FileSystem_Drive_RAM
#include "FS_Config_RAM.h"
#endif
#ifdef RTE_FileSystem_Drive_NOR_0
#include "FS_Config_NOR_0.h"
#endif
#ifdef RTE_FileSystem_Drive_NOR_1
#include "FS_Config_NOR_1.h"
#endif
#ifdef RTE_FileSystem_Drive_NAND_0
#include "FS_Config_NAND_0.h"
#endif
#ifdef RTE_FileSystem_Drive_NAND_1
#include "FS_Config_NAND_1.h"
#endif
#ifdef RTE_FileSystem_Drive_MC_0
#include "FS_Config_MC_0.h"
#endif
#ifdef RTE_FileSystem_Drive_MC_1
#include "FS_Config_MC_1.h"
#endif
#ifdef RTE_FileSystem_Drive_USB_0
#include "FS_Config_USB_0.h"
#endif
#ifdef RTE_FileSystem_Drive_USB_1
#include "FS_Config_USB_1.h"
#endif
#include "fs_config.h"

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::File System:Drive
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: FS_Config_MC_0.h
* Purpose: File System Configuration for Memory Card Drive
* Rev.: V5.01
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Memory Card Drive 0
// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
#define MC0_ENABLE 1
// <o>Connect to hardware via Driver_MCI# <0-255>
// <i>Select driver control block for hardware interface
#define MC0_MCI_DRIVER 0
// <o>Connect to hardware via Driver_SPI# <0-255>
// <i>Select driver control block for hardware interface when in SPI mode
#define MC0_SPI_DRIVER 0
// <o>Memory Card Interface Mode <0=>Native <1=>SPI
// <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
// <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
// <i>When using SPI both Driver_SPI# and Driver_MCI# must be specified
// <i>since the MCI driver provides the control interface lines.
#define MC0_SPI 0
// <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Drive Cache stores data sectors and may be increased to speed-up
// <i>file read/write operations on this drive (default: 4 KB)
#define MC0_CACHE_SIZE 4
// <e>Locate Drive Cache and Drive Buffer
// <i>Some microcontrollers support DMA only in specific memory areas and
// <i>require to locate the drive buffers at a fixed address.
#define MC0_CACHE_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Set buffer base address to RAM areas that support DMA with the drive.
#define MC0_CACHE_ADDR 0x7FD00000
// </e>
// <q>Use FAT Journal
// <i>Protect File Allocation Table and Directory Entries for
// <i>fail-safe operation.
#define MC0_FAT_JOURNAL 0
// <q>Default Drive "M0:"
// <i>Use this drive when no drive letter is specified.
#define MC0_DEFAULT_DRIVE 1
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config.c
* Purpose: Network Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Definitions
// <i> Global Network System definitions
// <s.15>Local Host Name
// <i> This is the name under which embedded host can be
// <i> accessed on a local area network.
// <i> Default: "my_host"
#define NET_HOST_NAME "my_host"
// <o>Memory Pool size <1536-262144:4><#/4>
// <i> This is the size of a memory pool in bytes. Buffers for
// <i> Network packets are allocated from this memory pool.
// <i> Default: 12000 bytes
#define NET_MEM_SIZE 3000
// </h>
#include "..\RTE_Components.h"
#ifdef RTE_Network_Interface_ETH_0
#include "Net_Config_ETH_0.h"
#endif
#ifdef RTE_Network_Interface_ETH_1
#include "Net_Config_ETH_1.h"
#endif
#ifdef RTE_Network_Interface_PPP_0
#include "Net_Config_PPP_0.h"
#endif
#ifdef RTE_Network_Interface_PPP_1
#include "Net_Config_PPP_1.h"
#endif
#ifdef RTE_Network_Interface_SLIP_0
#include "Net_Config_SLIP_0.h"
#endif
#ifdef RTE_Network_Interface_SLIP_1
#include "Net_Config_SLIP_1.h"
#endif
#ifdef RTE_Network_Socket_UDP
#include "Net_Config_UDP.h"
#endif
#ifdef RTE_Network_Socket_TCP
#include "Net_Config_TCP.h"
#endif
#ifdef RTE_Network_Socket_BSD
#include "Net_Config_BSD.h"
#endif
#ifdef RTE_Network_Web_Server_RO
#include "Net_Config_HTTP_Server.h"
#endif
#ifdef RTE_Network_Web_Server_FS
#include "Net_Config_HTTP_Server.h"
#endif
#ifdef RTE_Network_Telnet_Server
#include "Net_Config_Telnet_Server.h"
#endif
#ifdef RTE_Network_TFTP_Server
#include "Net_Config_TFTP_Server.h"
#endif
#ifdef RTE_Network_TFTP_Client
#include "Net_Config_TFTP_Client.h"
#endif
#ifdef RTE_Network_FTP_Server
#include "Net_Config_FTP_Server.h"
#endif
#ifdef RTE_Network_FTP_Client
#include "Net_Config_FTP_Client.h"
#endif
#ifdef RTE_Network_DNS_Client
#include "Net_Config_DNS_Client.h"
#endif
#ifdef RTE_Network_SMTP_Client
#include "Net_Config_SMTP_Client.h"
#endif
#ifdef RTE_Network_SNMP_Agent
#include "Net_Config_SNMP_Agent.h"
#endif
#ifdef RTE_Network_SNTP_Client
#include "Net_Config_SNTP_Client.h"
#endif
#include "net_config.h"
/**
\addtogroup net_genFunc
@{
*/
/**
\fn void net_sys_error (ERROR_CODE error)
\ingroup net_cores
\brief Network system error handler.
*/
void net_sys_error (ERROR_CODE error) {
/* This function is called when a fatal error is encountered. */
/* The normal program execution is not possible anymore. */
switch (error) {
case ERR_MEM_ALLOC:
/* Out of memory */
break;
case ERR_MEM_FREE:
/* Trying to release non existing memory block */
break;
case ERR_MEM_CORRUPT:
/* Memory Link pointer Corrupted */
/* More data written than the size of allocated mem block */
break;
case ERR_MEM_LOCK:
/* Locked Memory management function (alloc/free) re-entered */
break;
case ERR_UDP_ALLOC:
/* Out of UDP Sockets */
break;
case ERR_TCP_ALLOC:
/* Out of TCP Sockets */
break;
case ERR_TCP_STATE:
/* TCP State machine in undefined state */
break;
}
/* End-less loop */
while (1);
}
/**
@}
*/

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Socket
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_BSD.h
* Purpose: Network Configuration BSD Sockets
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Berkley (BSD) Sockets
#define BSD_ENABLE 1
// <o>Number of BSD Sockets <1-20>
// <i> Number of available Berkeley Sockets
// <i> Default: 2
#define BSD_NUM_SOCKS 10
// <o>Number of Streaming Server Sockets <0-20>
// <i> Defines a number of Streaming (TCP) Server sockets,
// <i> that listen for an incoming connection from the client.
// <i> Default: 1
#define BSD_SERVER_SOCKS 1
// <o>Receive Timeout in seconds <0-600>
// <i> A timeout for socket receive in blocking mode.
// <i> Timeout value of 0 means indefinite timeout.
// <i> Default: 20
#define BSD_RECEIVE_TOUT 20
// <q>Hostname Resolver
// <i> Enable or disable Berkeley style hostname resolver.
#define BSD_HOSTNAME_ENABLE 0
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Service
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_DNS_Client.h
* Purpose: Network Configuration DNS Client
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>DNS Client
#define DNS_CLIENT_ENABLE 1
// <o>Cache Table size <5-100>
// <i> Number of cached DNS host names/IP addresses
// <i> Default: 20
#define DNS_CLIENT_TAB_SIZE 20
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Interface
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_ETH_0.h
* Purpose: Network Configuration ETH Interface
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Ethernet Network Interface 0
#define ETH0_ENABLE 1
// <o>Connect to hardware via Driver_ETH# <0-255>
// <i>Select driver control block for MAC and PHY interface
#define ETH0_DRIVER 0
// <h>MAC Address
// <i> Local Ethernet MAC Address
// <i> Value FF:FF:FF:FF:FF:FF is not allowed.
// <i> It is an ethernet Broadcast MAC address.
// <o>A0dress byte 1 <0x00-0xff:2>
// <i> LSB is an ethernet Multicast bit.
// <i> Must be 0 for local MAC address.
// <i> Default: 0x1E
#define ETH0_MAC1 0x1E
// <o>Address byte 2 <0x00-0xff>
// <i> Default: 0x30
#define ETH0_MAC2 0x30
// <o>Address byte 3 <0x00-0xff>
// <i> Default: 0x6C
#define ETH0_MAC3 0x6C
// <o>Address byte 4 <0x00-0xff>
// <i> Default: 0xA2
#define ETH0_MAC4 0xA2
// <o>Address byte 5 <0x00-0xff>
// <i> Default: 0x45
#define ETH0_MAC5 0x45
// <o>Address byte 6 <0x00-0xff>
// <i> Default: 0x5E
#define ETH0_MAC6 0x5E
// </h>
// <h>IP Address
// <i> Local Static IP Address
// <i> Value 255.255.255.255 is not allowed.
// <i> It is a Broadcast IP address.
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define ETH0_IP1 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define ETH0_IP2 168
// <o>Address byte 3 <0-255>
// <i> Default: 0
#define ETH0_IP3 11
// <o>Address byte 4 <0-255>
// <i> Default: 100
#define ETH0_IP4 101
// </h>
// <h>Subnet mask
// <i> Local Subnet mask
// <o>Mask byte 1 <0-255>
// <i> Default: 255
#define ETH0_MASK1 255
// <o>Mask byte 2 <0-255>
// <i> Default: 255
#define ETH0_MASK2 255
// <o>Mask byte 3 <0-255>
// <i> Default: 255
#define ETH0_MASK3 255
// <o>Mask byte 4 <0-255>
// <i> Default: 0
#define ETH0_MASK4 0
// </h>
// <h>Default Gateway
// <i> Default Gateway IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define ETH0_GW1 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define ETH0_GW2 168
// <o>Address byte 3 <0-255>
// <i> Default: 0
#define ETH0_GW3 11
// <o>Address byte 4 <0-255>
// <i> Default: 254
#define ETH0_GW4 1
// </h>
// <h>Primary DNS Server
// <i> Primary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define ETH0_PRI_DNS1 192
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define ETH0_PRI_DNS2 168
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define ETH0_PRI_DNS3 11
// <o>Address byte 4 <0-255>
// <i> Default: 129
#define ETH0_PRI_DNS4 1
// </h>
// <h>Secondary DNS Server
// <i> Secondary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define ETH0_SEC_DNS1 194
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define ETH0_SEC_DNS2 25
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define ETH0_SEC_DNS3 2
// <o>Address byte 4 <0-255>
// <i> Default: 130
#define ETH0_SEC_DNS4 130
// </h>
// <h>ARP Definitions
// <i> Address Resolution Protocol Definitions
// <o>Cache Table size <5-100>
// <i> Number of cached hardware/IP addresses
// <i> Default: 10
#define ETH0_ARP_TAB_SIZE 10
// <o>Cache Timeout in seconds <5-255>
// <i> A timeout for a cached hardware/IP addresses
// <i> Default: 150
#define ETH0_ARP_CACHE_TOUT 150
// <o>Number of Retries <0-20>
// <i> Number of Retries to resolve an IP address
// <i> before ARP module gives up
// <i> Default: 4
#define ETH0_ARP_MAX_RETRY 4
// <o>Resend Timeout in seconds <1-10>
// <i> A timeout to resend the ARP Request
// <i> Default: 2
#define ETH0_ARP_RESEND_TOUT 2
// <q>Send Notification on Address changes
// <i> When this option is enabled, the embedded host
// <i> will send a Gratuitous ARP notification at startup,
// <i> or when the device IP address has changed.
// <i> Default: Disabled
#define ETH0_ARP_NOTIFY 0
// </h>
// <e>IGMP Group Management
// <i> Enable or disable Internet Group Management Protocol
#define ETH0_IGMP_ENABLE 0
// <o>Membership Table size <2-50>
// <i> Number of Groups this host can join
// <i> Default: 5
#define ETH0_IGMP_TAB_SIZE 5
// </e>
// <q>NetBIOS Name Service
// <i> When this option is enabled, the embedded host can be
// <i> accessed by his name on the local LAN using NBNS protocol.
// <i> You need to modify also the number of UDP Sockets,
// <i> because NBNS protocol uses one UDP socket to run.
#define ETH0_NBNS_ENABLE 1
// <e>Dynamic Host Configuration
// <i> When this option is enabled, local IP address, Net Mask
// <i> and Default Gateway are obtained automatically from
// <i> the DHCP Server on local LAN.
// <i> You need to modify also the number of UDP Sockets,
// <i> because DHCP protocol uses one UDP socket to run.
#define ETH0_DHCP_ENABLE 0
// <s.40>Vendor Class Identifier
// <i> This value is optional. If specified, it is added
// <i> to DHCP request message, identifying vendor type.
// <i> Default: ""
#define ETH0_DHCP_VCID ""
// <q>Bootfile Name
// <i> This value is optional. If enabled, the Bootfile Name
// <i> (option 67) is also requested from DHCP server.
// <i> Default: disabled
#define ETH0_DHCP_BOOTFILE 0
// <q>NTP Servers
// <i> This value is optional. If enabled, a list of NTP Servers
// <i> (option 42) is also requested from DHCP server.
// <i> Default: disabled
#define ETH0_DHCP_NTP_SERVERS 0
// </e>
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Socket
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_TCP.h
* Purpose: Network Configuration TCP Sockets
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>TCP Sockets
#define TCP_ENABLE 1
// <o>Number of TCP Sockets <1-20>
// <i> Number of available TCP sockets
// <i> Default: 5
#define TCP_NUM_SOCKS 10
// <o>Number of Retries <0-20>
// <i> How many times TCP module will try to retransmit data
// <i> before giving up. Increase this value for high-latency
// <i> and low_throughput networks.
// <i> Default: 5
#define TCP_MAX_RETRY 5
// <o>Retry Timeout in seconds <1-10>
// <i> If data frame not acknowledged within this time frame,
// <i> TCP module will try to resend the data again.
// <i> Default: 4
#define TCP_RETRY_TOUT 4
// <o>Default Connect Timeout in seconds <1-600>
// <i> Default TCP Socket Keep Alive timeout. When it expires
// <i> with no TCP data frame send, TCP Connection is closed.
// <i> Default: 120
#define TCP_DEFAULT_TOUT 120
// <o>Maximum Segment Size <536-1460>
// <i> The Maximum Segment Size specifies the maximum
// <i> number of bytes in the TCP segment's Data field.
// <i> Default: 1460
#define TCP_MAX_SEG_SIZE 1460
// <o>Receive Window Size <536-65535>
// <i> Receive Window Size specifies the size of data,
// <i> that the socket is able to buffer in flow-control mode.
// <i> Default: 4380
#define TCP_RECEIVE_WIN_SIZE 4380
// </h>
// TCP Initial Retransmit period in seconds
#define TCP_INITIAL_RETRY_TOUT 1
// TCP SYN frame retransmit period in seconds
#define TCP_SYN_RETRY_TOUT 2
// Number of retries to establish a connection
#define TCP_CONNECT_RETRY 7

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Socket
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_UDP.h
* Purpose: Network Configuration UDP Sockets
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>UDP Sockets
#define UDP_ENABLE 1
// <o>Number of UDP Sockets <1-30>
// <i> Number of available UDP sockets
// <i> Default: 5
#define UDP_NUM_SOCKS 15
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Debug.c
* Purpose: Network Debug Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <q>Print Time Stamp
// <i> Enable printing the time-info in debug messages
#define DBG_TIME 1
// <h>TCPnet Debug Definitions
// <o>Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Dynamic Memory debug messages
#define DBG_MEM 1
// <o>Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Ethernet debug messages
#define DBG_ETH 0
// <o>PPP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off PPP debug messages
#define DBG_PPP 0
// <o>SLIP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off SLIP debug messages
#define DBG_SLIP 0
// <o>ARP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off ARP debug messages
#define DBG_ARP 0
// <o>IP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off IP debug messages
#define DBG_IP 1
// <o>ICMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off ICMP debug messages
#define DBG_ICMP 1
// <o>IGMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off IGMP debug messages
#define DBG_IGMP 1
// <o>UDP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off UDP debug messages
#define DBG_UDP 1
// <o>TCP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TCP debug messages
#define DBG_TCP 1
// <o>NBNS Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off NetBIOS Name Service debug messages
#define DBG_NBNS 1
// <o>DHCP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Dynamic Host Configuration debug messages
#define DBG_DHCP 1
// <o>DNS Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Domain Name Service debug messages
#define DBG_DNS 1
// <o>SNMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Simple Network Management debug messages
#define DBG_SNMP 1
// <o>SNTP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Simple Network Time debug messages
#define DBG_SNTP 1
// <o>BSD Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off BSD Interface debug messages
#define DBG_BSD 1
// </h>
// <h>Application Debug Definitions
// <o>HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Web Server debug messages
#define DBG_HTTP_SERVER 1
// <o>FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off FTP Server debug messages
#define DBG_FTP_SERVER 1
// <o>FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off FTP Client debug messages
#define DBG_FTP_CLIENT 1
// <o>Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Telnet Server debug messages
#define DBG_TELNET_SERVER 1
// <o>TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TFTP Server debug messages
#define DBG_TFTP_SERVER 1
// <o>TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TFTP Client debug messages
#define DBG_TFTP_CLIENT 1
// <o>SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off SMTP Client debug messages
#define DBG_SMTP_CLIENT 1
// </h>
#include "net_debug.h"
/**
\fn void net_debug_init (void)
\brief Initialize Network Debug Interface.
*/
void net_debug_init (void) {
/* Add your code to initialize the Debug output. This is usually the */
/* serial interface. The function is called at TCPnet system startup. */
/* You may need to customize also the 'putchar()' function. */
}

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/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'CyaSSL-Full'
* Target: 'CyaSSL-Full'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */
#define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */
#define RTE_Drivers_MCI0 /* Driver MCI0 */
#define RTE_Drivers_PHY_ST802RT1 /* Driver PHY ST802RT1 */
#define RTE_FileSystem_Core /* File System Core */
#define RTE_FileSystem_LFN /* File System with Long Filename support */
#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */
#define RTE_Network_Core /* Network Core */
#define RTE_Network_Debug /* Network Debug Version */
#define RTE_Network_DNS_Client /* Network DNS Client */
#define RTE_Network_Interface_ETH_0 /* Network Interface ETH 0 */
#define RTE_Network_Socket_BSD /* Network Socket BSD */
#define RTE_Network_Socket_TCP /* Network Socket TCP */
#define RTE_Network_Socket_UDP /* Network Socket UDP */
#endif /* RTE_COMPONENTS_H */

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/* config-FS.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// <<< Use Configuration Wizard in Context Menu >>>
// <h> wolfCrypt Configuration
// <h>Cert/Key Strage
// <o>Cert Storage <0=> SD Card <1=> Mem Buff (1024bytes) <2=> Mem Buff (2048bytes)
#define MDK_CONF_CERT_BUFF 0
#if MDK_CONF_CERT_BUFF== 1
#define USE_CERT_BUFFERS_1024
#elif MDK_CONF_CERT_BUFF == 2
#define USE_CERT_BUFFERS_2048
#endif
//</h>
// <h>Crypt Algrithm
// <h>MD5, SHA, SHA-256, AES, RC4, ASN, RSA
// </h>
// <e>MD2
#define MDK_CONF_MD2 0
#if MDK_CONF_MD2 == 1
#define CYASSL_MD2
#endif
// </e>
// <e>MD4
#define MDK_CONF_MD4 1
#if MDK_CONF_MD4 == 0
#define NO_MD4
#endif
// </e>
// <e>SHA-384
// <i>This has to be with SHA512
#define MDK_CONF_SHA384 0
#if MDK_CONF_SHA384 == 1
#define CYASSL_SHA384
#endif
// </e>
// <e>SHA-512
#define MDK_CONF_SHA512 0
#if MDK_CONF_SHA512 == 1
#define CYASSL_SHA512
#endif
// </e>
// <e>RIPEMD
#define MDK_CONF_RIPEMD 0
#if MDK_CONF_RIPEMD == 1
#define CYASSL_RIPEMD
#endif
// </e>
// <e>HMAC
#define MDK_CONF_HMAC 1
#if MDK_CONF_HMAC == 0
#define NO_HMAC
#endif
// </e>
// <e>HC128
#define MDK_CONF_HC128 0
#if MDK_CONF_HC128 == 1
#define HAVE_HC128
#endif
// </e>
// <e>RABBIT
#define MDK_CONF_RABBIT 1
#if MDK_CONF_RABBI == 0
#define NO_RABBIT
#endif
// </e>
// <e>AEAD
#define MDK_CONF_AEAD 0
#if MDK_CONF_AEAD == 1
#define HAVE_AEAD
#endif
// </e>
// <e>DES3
#define MDK_CONF_DES3 1
#if MDK_CONF_DES3 == 0
#define NO_DES3
#endif
// </e>
// <e>CAMELLIA
#define MDK_CONF_CAMELLIA 0
#if MDK_CONF_CAMELLIA == 1
#define HAVE_CAMELLIA
#endif
// </e>
// <e>DH
// <i>need this for CYASSL_SERVER, OPENSSL_EXTRA
#define MDK_CONF_DH 1
#if MDK_CONF_DH == 0
#define NO_DH
#endif
// </e>
// <e>DSA
#define MDK_CONF_DSA 1
#if MDK_CONF_DSA == 0
#define NO_DSA
#endif
// </e>
// <e>PWDBASED
#define MDK_CONF_PWDBASED 1
#if MDK_CONF_PWDBASED == 0
#define NO_PWDBASED
#endif
// </e>
// <e>ECC
#define MDK_CONF_ECC 0
#if MDK_CONF_ECC == 1
#define HAVE_ECC
#endif
// </e>
// <e>PSK
#define MDK_CONF_PSK 1
#if MDK_CONF_PSK == 0
#define NO_PSK
#endif
// </e>
// <e>AESCCM (Turn off Hardware Crypt)
#define MDK_CONF_AESCCM 0
#if MDK_CONF_AESCCM == 1
#define HAVE_AESCCM
#endif
// </e>
// <e>AESGCM (Turn off Hardware Crypt)
#define MDK_CONF_AESGCM 0
#if MDK_CONF_AESGCM == 1
#define HAVE_AESGCM
#define BUILD_AESGCM
#endif
// </e>
// <e>NTRU (need License, "crypto_ntru.h")
#define MDK_CONF_NTRU 0
#if MDK_CONF_NTRU == 1
#define HAVE_NTRU
#endif
// </e>
// </h>
// <h>Hardware Crypt (See document for usage)
// <e>Hardware RNG
#define MDK_CONF_STM32F2_RNG 0
#if MDK_CONF_STM32F2_RNG == 1
#define STM32F2_RNG
#else
#endif
// </e>
// <e>Hardware Crypt
#define MDK_CONF_STM32F2_CRYPTO 0
#if MDK_CONF_STM32F2_CRYPTO == 1
#define STM32F2_CRYPTO
#endif
// </e>
// </h>
//</h>
// <<< end of configuration section >>>

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/* config-RTX-TCP-FS.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/**** CyaSSL for KEIL-RL Configuration ****/
#define __CORTEX_M3__
#define CYASSL_MDK_ARM
#define NO_WRITEV
#define NO_CYASSL_DIR
#define NO_MAIN_DRIVER
#define CYASSL_DER_LOAD
#define HAVE_NULL_CIPHER
#define HAVE_KEIL_RTX
#define CYASSL_CMSIS_RTOS
#define CYASSL_KEIL_TCP_NET
// <<< Use Configuration Wizard in Context Menu >>>
// <h> CyaSSL Configuration
// <h>SSL (Included by default)
// </h>
// <e>TLS
#define MDK_CONF_TLS 1
#if MDK_CONF_TLS == 0
#define NO_TLS
#endif
// </e>
// <e>CRL
#define MDK_CONF_DER_LOAD 0
#if MDK_CONF_DER_LOAD == 1
#define CYASSL_DER_LOAD
#endif
// </e>
// <e>OpenSSL Extra
#define MDK_CONF_OPENSSL_EXTRA 1
#if MDK_CONF_OPENSSL_EXTRA == 1
#define OPENSSL_EXTRA
#endif
// </e>
//</h>
// <h>Cert/Key Generation
// <e>CertGen
#define MDK_CONF_CERT_GEN 0
#if MDK_CONF_CERT_GEN == 1
#define CYASSL_CERT_GEN
#endif
// </e>
// <e>KeyGen
#define MDK_CONF_KEY_GEN 0
#if MDK_CONF_KEY_GEN == 1
#define CYASSL_KEY_GEN
#endif
// </e>
//</h>
// <h>Others
// <e>Inline
#define MDK_CONF_INLINE 0
#if MDK_CONF_INLINE == 0
#define NO_INLINE
#endif
// </e>
// <h>Debug
// <e>Debug Message
#define MDK_CONF_DebugMessage 0
#if MDK_CONF_DebugMessage == 1
#define DEBUG_CYASSL
#endif
// </e>
// <e>Check malloc
#define MDK_CONF_CheckMalloc 1
#if MDK_CONF_CheckMalloc == 1
#define CYASSL_MALLOC_CHECK
#endif
// </e>
// </h>
// <e>ErrNo.h
#define MDK_CONF_ErrNo 0
#if MDK_CONF_ErrNo == 1
#define HAVE_ERRNO
#endif
// </e>
// <e>Error Strings
#define MDK_CONF_ErrorStrings 1
#if MDK_CONF_ErrorStrings == 0
#define NO_ERROR_STRINGS
#endif
// </e>
// <e>zlib (need "zlib.h")
#define MDK_CONF_LIBZ 0
#if MDK_CONF_LIBZ == 1
#define HAVE_LIBZ
#endif
// </e>
// <e>CAVIUM (need CAVIUM headers)
#define MDK_CONF_CAVIUM 0
#if MDK_CONF_CAVIUM == 1
#define HAVE_CAVIUM
#endif
// </e>
// <e>Small Stack
#define MDK_CONF_SmallStack 1
#if MDK_CONF_SmallStack == 0
#define NO_CYASSL_SMALL_STACK
#endif
// </e>
// <e>Use Fast Math
#define MDK_CONF_FASTMATH 0
#if MDK_CONF_FASTMATH == 1
#define USE_FAST_MATH
#endif
// </e>
// </h>
// <<< end of configuration section >>>

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/* settings.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* Place OS specific preprocessor flags, defines, includes here, will be
included into every file because types.h includes it */
#ifndef CTAO_CRYPT_SETTINGS_H
#define CTAO_CRYPT_SETTINGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Uncomment next line if using IPHONE */
/* #define IPHONE */
/* Uncomment next line if using ThreadX */
/* #define THREADX */
/* Uncomment next line if using Micrium ucOS */
/* #define MICRIUM */
/* Uncomment next line if using Mbed */
/* #define MBED */
/* Uncomment next line if using Microchip PIC32 ethernet starter kit */
/* #define MICROCHIP_PIC32 */
/* Uncomment next line if using Microchip TCP/IP stack, version 5 */
/* #define MICROCHIP_TCPIP_V5 */
/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */
/* #define MICROCHIP_TCPIP */
/* Uncomment next line if using PIC32MZ Crypto Engine */
/* #define CYASSL_MICROCHIP_PIC32MZ */
/* Uncomment next line if using FreeRTOS */
/* #define FREERTOS */
/* Uncomment next line if using FreeRTOS Windows Simulator */
/* #define FREERTOS_WINSIM */
/* Uncomment next line if using RTIP */
/* #define EBSNET */
/* Uncomment next line if using lwip */
/* #define CYASSL_LWIP */
/* Uncomment next line if building CyaSSL for a game console */
/* #define CYASSL_GAME_BUILD */
/* Uncomment next line if building CyaSSL for LSR */
/* #define CYASSL_LSR */
/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */
/* #define FREESCALE_MQX */
/* Uncomment next line if using STM32F2 */
/* #define CYASSL_STM32F2 */
/* Uncomment next line if using Comverge settings */
/* #define COMVERGE */
/* Uncomment next line if using QL SEP settings */
/* #define CYASSL_QL */
/* Uncomment next line if using LwIP native TCP socket settings */
/* #define HAVE_LWIP_NATIVE */
/* Uncomment next line if building for EROAD */
/* #define CYASSL_EROAD */
#include <cyassl/ctaocrypt/visibility.h>
#ifdef IPHONE
#define SIZEOF_LONG_LONG 8
#endif
#ifdef CYASSL_USER_SETTINGS
#include <user_settings.h>
#endif
#ifdef COMVERGE
#define THREADX
#define HAVE_NETX
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define NO_RSA
#define NO_SESSION_CACHE
#define HAVE_ECC
#endif
#ifdef THREADX
#define SIZEOF_LONG_LONG 8
#endif
#ifdef HAVE_NETX
#include "nx_api.h"
#endif
#if defined(HAVE_LWIP_NATIVE) /* using LwIP native TCP socket */
#define CYASSL_LWIP
#define NO_WRITEV
#define SINGLE_THREADED
#define CYASSL_USER_IO
#define NO_FILESYSTEM
#endif
#ifdef MICROCHIP_PIC32
/* #define CYASSL_MICROCHIP_PIC32MZ */
#define SIZEOF_LONG_LONG 8
#define SINGLE_THREADED
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#endif
#ifdef CYASSL_MICROCHIP_PIC32MZ
#define CYASSL_PIC32MZ_CE
#define CYASSL_PIC32MZ_CRYPT
#define HAVE_AES_ENGINE
#define CYASSL_PIC32MZ_RNG
/* #define CYASSL_PIC32MZ_HASH */
#define CYASSL_AES_COUNTER
#define HAVE_AESGCM
#define NO_BIG_INT
#endif
#ifdef MICROCHIP_TCPIP_V5
/* include timer functions */
#include "TCPIP Stack/TCPIP.h"
#endif
#ifdef MICROCHIP_TCPIP
/* include timer, NTP functions */
#ifdef MICROCHIP_MPLAB_HARMONY
#include "tcpip/tcpip.h"
#else
#include "system/system_services.h"
#include "tcpip/sntp.h"
#endif
#endif
#ifdef MBED
#define CYASSL_USER_IO
#define NO_FILESYSTEM
#define NO_CERT
#define USE_CERT_BUFFERS_1024
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define HAVE_ECC
#define NO_SESSION_CACHE
#define CYASSL_CMSIS_RTOS
#endif
#ifdef CYASSL_EROAD
#define FREESCALE_MQX
#define FREESCALE_MMCAU
#define SINGLE_THREADED
#define NO_STDIO_FILESYSTEM
#define CYASSL_LEANPSK
#define HAVE_NULL_CIPHER
#define NO_OLD_TLS
#define NO_ASN
#define NO_BIG_INT
#define NO_RSA
#define NO_DSA
#define NO_DH
#define NO_CERTS
#define NO_PWDBASED
#define NO_DES3
#define NO_MD4
#define NO_RC4
#define NO_MD5
#define NO_SESSION_CACHE
#define NO_MAIN_DRIVER
#endif
#ifdef FREERTOS_WINSIM
#define FREERTOS
#define USE_WINDOWS_API
#endif
/* Micrium will use Visual Studio for compilation but not the Win32 API */
#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \
&& !defined(EBSNET) && !defined(CYASSL_EROAD)
#define USE_WINDOWS_API
#endif
#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER)
#include <stdlib.h>
#define XMALLOC(s, h, type) malloc((s))
#define XFREE(p, h, type) free((p))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif
#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL)
#undef XMALLOC
#define XMALLOC yaXMALLOC
#undef XFREE
#define XFREE yaXFREE
#undef XREALLOC
#define XREALLOC yaXREALLOC
#endif
#ifdef FREERTOS
#ifndef NO_WRITEV
#define NO_WRITEV
#endif
#ifndef NO_SHA512
#define NO_SHA512
#endif
#ifndef NO_DH
#define NO_DH
#endif
#ifndef NO_DSA
#define NO_DSA
#endif
#ifndef NO_HC128
#define NO_HC128
#endif
#ifndef SINGLE_THREADED
#include "FreeRTOS.h"
#include "semphr.h"
#endif
#endif
#ifdef EBSNET
#include "rtip.h"
/* #define DEBUG_CYASSL */
#define NO_CYASSL_DIR /* tbd */
#if (POLLOS)
#define SINGLE_THREADED
#endif
#if (RTPLATFORM)
#if (!RTP_LITTLE_ENDIAN)
#define BIG_ENDIAN_ORDER
#endif
#else
#if (!KS_LITTLE_ENDIAN)
#define BIG_ENDIAN_ORDER
#endif
#endif
#if (WINMSP3)
#undef SIZEOF_LONG
#define SIZEOF_LONG_LONG 8
#else
#sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG
#endif
#define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC))
#define XFREE(p, h, type) (rtp_free(p))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif /* EBSNET */
#ifdef CYASSL_GAME_BUILD
#define SIZEOF_LONG_LONG 8
#if defined(__PPU) || defined(__XENON)
#define BIG_ENDIAN_ORDER
#endif
#endif
#ifdef CYASSL_LSR
#define HAVE_WEBSERVER
#define SIZEOF_LONG_LONG 8
#define CYASSL_LOW_MEMORY
#define NO_WRITEV
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define NO_DEV_RANDOM
#define NO_CYASSL_DIR
#define NO_RABBIT
#ifndef NO_FILESYSTEM
#define LSR_FS
#include "inc/hw_types.h"
#include "fs.h"
#endif
#define CYASSL_LWIP
#include <errno.h> /* for tcp errno */
#define CYASSL_SAFERTOS
#if defined(__IAR_SYSTEMS_ICC__)
/* enum uses enum */
#pragma diag_suppress=Pa089
#endif
#endif
#ifdef CYASSL_SAFERTOS
#ifndef SINGLE_THREADED
#include "SafeRTOS/semphr.h"
#endif
#include "SafeRTOS/heap.h"
#define XMALLOC(s, h, type) pvPortMalloc((s))
#define XFREE(p, h, type) vPortFree((p))
#define XREALLOC(p, n, h, t) pvPortRealloc((p), (n))
#endif
#ifdef CYASSL_LOW_MEMORY
#undef RSA_LOW_MEM
#define RSA_LOW_MEM
#undef CYASSL_SMALL_STACK
#define CYASSL_SMALL_STACK
#undef TFM_TIMING_RESISTANT
#define TFM_TIMING_RESISTANT
#endif
#ifdef FREESCALE_MQX
#define SIZEOF_LONG_LONG 8
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_RABBIT
#define NO_CYASSL_DIR
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#define FREESCALE_K70_RNGA
/* #define FREESCALE_K53_RNGB */
#include "mqx.h"
#ifndef NO_FILESYSTEM
#include "mfs.h"
#include "fio.h"
#endif
#ifndef SINGLE_THREADED
#include "mutex.h"
#endif
#define XMALLOC(s, h, t) (void *)_mem_alloc_system((s))
#define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));}
/* Note: MQX has no realloc, using fastmath above */
#endif
#ifdef CYASSL_STM32F2
#define SIZEOF_LONG_LONG 8
#define NO_DEV_RANDOM
#define NO_CYASSL_DIR
#define NO_RABBIT
#define STM32F2_RNG
#define STM32F2_CRYPTO
#define KEIL_INTRINSICS
#endif
#ifdef MICRIUM
#include "stdlib.h"
#include "net_cfg.h"
#include "ssl_cfg.h"
#include "net_secure_os.h"
#define CYASSL_TYPES
typedef CPU_INT08U byte;
typedef CPU_INT16U word16;
typedef CPU_INT32U word32;
#if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32)
#define SIZEOF_LONG 4
#undef SIZEOF_LONG_LONG
#else
#undef SIZEOF_LONG
#define SIZEOF_LONG_LONG 8
#endif
#define STRING_USER
#define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr)))
#define XSTRNCPY(pstr_dest, pstr_src, len_max) \
((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \
(CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max)))
#define XSTRNCMP(pstr_1, pstr_2, len_max) \
((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \
(CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max)))
#define XSTRSTR(pstr, pstr_srch) \
((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \
(CPU_CHAR *)(pstr_srch)))
#define XMEMSET(pmem, data_val, size) \
((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \
(CPU_SIZE_T)(size)))
#define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \
(void *)(psrc), (CPU_SIZE_T)(size)))
#define XMEMCMP(pmem_1, pmem_2, size) \
(((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \
(CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES)
#define XMEMMOVE XMEMCPY
#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
#define MICRIUM_MALLOC
#define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \
(CPU_SIZE_T)(s), (void *)0))
#define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \
(p), (void *)0))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif
#if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED)
#undef NO_FILESYSTEM
#else
#define NO_FILESYSTEM
#endif
#if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG)
#define DEBUG_CYASSL
#else
#undef DEBUG_CYASSL
#endif
#if (SSL_CFG_OPENSSL_EN == DEF_ENABLED)
#define OPENSSL_EXTRA
#else
#undef OPENSSL_EXTRA
#endif
#if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED)
#undef SINGLE_THREADED
#else
#define SINGLE_THREADED
#endif
#if (SSL_CFG_DH_EN == DEF_ENABLED)
#undef NO_DH
#else
#define NO_DH
#endif
#if (SSL_CFG_DSA_EN == DEF_ENABLED)
#undef NO_DSA
#else
#define NO_DSA
#endif
#if (SSL_CFG_PSK_EN == DEF_ENABLED)
#undef NO_PSK
#else
#define NO_PSK
#endif
#if (SSL_CFG_3DES_EN == DEF_ENABLED)
#undef NO_DES
#else
#define NO_DES
#endif
#if (SSL_CFG_AES_EN == DEF_ENABLED)
#undef NO_AES
#else
#define NO_AES
#endif
#if (SSL_CFG_RC4_EN == DEF_ENABLED)
#undef NO_RC4
#else
#define NO_RC4
#endif
#if (SSL_CFG_RABBIT_EN == DEF_ENABLED)
#undef NO_RABBIT
#else
#define NO_RABBIT
#endif
#if (SSL_CFG_HC128_EN == DEF_ENABLED)
#undef NO_HC128
#else
#define NO_HC128
#endif
#if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
#define BIG_ENDIAN_ORDER
#else
#undef BIG_ENDIAN_ORDER
#define LITTLE_ENDIAN_ORDER
#endif
#if (SSL_CFG_MD4_EN == DEF_ENABLED)
#undef NO_MD4
#else
#define NO_MD4
#endif
#if (SSL_CFG_WRITEV_EN == DEF_ENABLED)
#undef NO_WRITEV
#else
#define NO_WRITEV
#endif
#if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED)
#define NO_DEV_RANDOM
#else
#undef NO_DEV_RANDOM
#endif
#if (SSL_CFG_USER_IO_EN == DEF_ENABLED)
#define CYASSL_USER_IO
#else
#undef CYASSL_USER_IO
#endif
#if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED)
#undef LARGE_STATIC_BUFFERS
#undef STATIC_CHUNKS_ONLY
#else
#define LARGE_STATIC_BUFFERS
#define STATIC_CHUNKS_ONLY
#endif
#if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED)
#define CYASSL_DER_LOAD
#else
#undef CYASSL_DER_LOAD
#endif
#if (SSL_CFG_DTLS_EN == DEF_ENABLED)
#define CYASSL_DTLS
#else
#undef CYASSL_DTLS
#endif
#if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED)
#define CYASSL_CALLBACKS
#else
#undef CYASSL_CALLBACKS
#endif
#if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED)
#define USE_FAST_MATH
#else
#undef USE_FAST_MATH
#endif
#if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED)
#define TFM_TIMING_RESISTANT
#else
#undef TFM_TIMING_RESISTANT
#endif
#endif /* MICRIUM */
#ifdef CYASSL_QL
#ifndef CYASSL_SEP
#define CYASSL_SEP
#endif
#ifndef OPENSSL_EXTRA
#define OPENSSL_EXTRA
#endif
#ifndef SESSION_CERTS
#define SESSION_CERTS
#endif
#ifndef HAVE_AESCCM
#define HAVE_AESCCM
#endif
#ifndef ATOMIC_USER
#define ATOMIC_USER
#endif
#ifndef CYASSL_DER_LOAD
#define CYASSL_DER_LOAD
#endif
#ifndef KEEP_PEER_CERT
#define KEEP_PEER_CERT
#endif
#ifndef HAVE_ECC
#define HAVE_ECC
#endif
#ifndef SESSION_INDEX
#define SESSION_INDEX
#endif
#endif /* CYASSL_QL */
#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \
!defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY)
#define USE_CYASSL_MEMORY
#endif
#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS)
#undef KEEP_PEER_CERT
#define KEEP_PEER_CERT
#endif
/* stream ciphers except arc4 need 32bit alignment, intel ok without */
#ifndef XSTREAM_ALIGNMENT
#if defined(__x86_64__) || defined(__ia64__) || defined(__i386__)
#define NO_XSTREAM_ALIGNMENT
#else
#define XSTREAM_ALIGNMENT
#endif
#endif
/* if using hardware crypto and have alignment requirements, specify the
requirement here. The record header of SSL/TLS will prvent easy alignment.
This hint tries to help as much as possible. */
#ifndef CYASSL_GENERAL_ALIGNMENT
#ifdef CYASSL_AESNI
#define CYASSL_GENERAL_ALIGNMENT 16
#elif defined(XSTREAM_ALIGNMENT)
#define CYASSL_GENERAL_ALIGNMENT 4
#else
#define CYASSL_GENERAL_ALIGNMENT 0
#endif
#endif
#ifdef HAVE_CRL
/* not widely supported yet */
#undef NO_SKID
#define NO_SKID
#endif
/* Place any other flags or defines here */
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* CTAO_CRYPT_SETTINGS_H */

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/******************************************************************************/
/* STM32_SWO.ini: STM32 Debugger Initialization File */
/******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>> //
/******************************************************************************/
/* This file is part of the uVision/ARM development tools. */
/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */
/* This software may only be used under the terms of a valid, current, */
/* end user licence from KEIL for a compatible version of KEIL software */
/* development tools. Nothing else gives you the right to use this software. */
/******************************************************************************/
FUNC void DebugSetup (void) {
// <h> Debug MCU Configuration
// <o1.0> DBG_SLEEP <i> Debug Sleep Mode
// <o1.1> DBG_STOP <i> Debug Stop Mode
// <o1.2> DBG_STANDBY <i> Debug Standby Mode
// <o1.5> TRACE_IOEN <i> Trace I/O Enable
// <o1.6..7> TRACE_MODE <i> Trace Mode
// <0=> Asynchronous
// <1=> Synchronous: TRACEDATA Size 1
// <2=> Synchronous: TRACEDATA Size 2
// <3=> Synchronous: TRACEDATA Size 4
// <o1.8> DBG_IWDG_STOP <i> Independant Watchdog Stopped when Core is halted
// <o1.9> DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
// <o1.10> DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
// <o1.11> DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
// <o1.12> DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
// <o1.13> DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
// <o1.14> DBG_CAN_STOP <i> CAN Stopped when Core is halted
// </h>
_WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR
}
DebugSetup(); // Debugger Setup

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/*----------------------------------------------------------------------------
* RL-ARM - RTX
*----------------------------------------------------------------------------
* Name: RTX_Conf_CM.C
* Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
* Rev.: V4.73
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
#include "cmsis_os.h"
/*----------------------------------------------------------------------------
* RTX User configuration part BEGIN
*---------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
//
// <h>Thread Configuration
// =======================
//
// <o>Number of concurrent running threads <0-250>
// <i> Defines max. number of threads that will run at the same time.
// <i> Default: 6
#ifndef OS_TASKCNT
#define OS_TASKCNT 6
#endif
// <o>Default Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines default stack size for threads with osThreadDef stacksz = 0
// <i> Default: 200
#ifndef OS_STKSIZE
#define OS_STKSIZE 300
#endif
// <o>Main Thread stack size [bytes] <64-32768:8><#/4>
// <i> Defines stack size for main thread.
// <i> Default: 200
#ifndef OS_MAINSTKSIZE
#define OS_MAINSTKSIZE 2000
#endif
// <o>Number of threads with user-provided stack size <0-250>
// <i> Defines the number of threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVCNT
#define OS_PRIVCNT 0
#endif
// <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
// <i> Defines the combined stack size for threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVSTKSIZE
#define OS_PRIVSTKSIZE 2500
#endif
// <q>Check for stack overflow
// <i> Includes the stack checking code for stack overflow.
// <i> Note that additional code reduces the Kernel performance.
#ifndef OS_STKCHECK
#define OS_STKCHECK 1
#endif
// <o>Processor mode for thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_RUNPRIV
#define OS_RUNPRIV 1
#endif
// </h>
// <h>RTX Kernel Timer Tick Configuration
// ======================================
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
// <i> Use the Cortex-M SysTick timer as a time-base for RTX.
#ifndef OS_SYSTICK
#define OS_SYSTICK 1
#endif
//
// <o>Timer clock value [Hz] <1-1000000000>
// <i> Defines the timer clock value.
// <i> Default: 12000000 (12MHz)
#ifndef OS_CLOCK
#define OS_CLOCK 12000000
#endif
// <o>Timer tick value [us] <1-1000000>
// <i> Defines the timer tick value.
// <i> Default: 1000 (1ms)
#ifndef OS_TICK
#define OS_TICK 1000
#endif
// </h>
// <h>System Configuration
// =======================
//
// <e>Round-Robin Thread switching
// ===============================
//
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN
#define OS_ROBIN 1
#endif
// <o>Round-Robin Timeout [ticks] <1-1000>
// <i> Defines how long a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBINTOUT
#define OS_ROBINTOUT 5
#endif
// </e>
// <e>User Timers
// ==============
// <i> Enables user Timers
#ifndef OS_TIMERS
#define OS_TIMERS 1
#endif
// <o>Timer Thread Priority
// <1=> Low
// <2=> Below Normal <3=> Normal <4=> Above Normal
// <5=> High
// <6=> Realtime (highest)
// <i> Defines priority for Timer Thread
// <i> Default: High
#ifndef OS_TIMERPRIO
#define OS_TIMERPRIO 5
#endif
// <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines stack size for Timer thread.
// <i> Default: 200
#ifndef OS_TIMERSTKSZ
#define OS_TIMERSTKSZ 50
#endif
// <o>Timer Callback Queue size <1-32>
// <i> Number of concurrent active timer callback functions.
// <i> Default: 4
#ifndef OS_TIMERCBQS
#define OS_TIMERCBQS 4
#endif
// </e>
// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
// <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries
// <48=> 48 entries <64=> 64 entries
// <96=> 96 entries
// <i> ISR functions store requests to this buffer,
// <i> when they are called from the interrupt handler.
// <i> Default: 16 entries
#ifndef OS_FIFOSZ
#define OS_FIFOSZ 16
#endif
// </h>
//------------- <<< end of configuration section >>> -----------------------
// Standard library system mutexes
// ===============================
// Define max. number system mutexes that are used to protect
// the arm standard runtime library. For microlib they are not used.
#ifndef OS_MUTEXCNT
#define OS_MUTEXCNT 8
#endif
/*----------------------------------------------------------------------------
* RTX User configuration part END
*---------------------------------------------------------------------------*/
#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
/*----------------------------------------------------------------------------
* Global Functions
*---------------------------------------------------------------------------*/
/*--------------------------- os_idle_demon ---------------------------------*/
void os_idle_demon (void) {
/* The idle demon is a system thread, running when no other thread is */
/* ready to run. */
for (;;) {
/* HERE: include optional user code to be executed when no thread runs.*/
}
}
#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
/*--------------------------- os_tick_init ----------------------------------*/
// Initialize alternative hardware timer as RTX kernel timer
// Return: IRQ number of the alternative hardware timer
int os_tick_init (void) {
return (-1); /* Return IRQ number of timer (0..239) */
}
/*--------------------------- os_tick_val -----------------------------------*/
// Get alternative hardware timer current value (0 .. OS_TRV)
uint32_t os_tick_val (void) {
return (0);
}
/*--------------------------- os_tick_ovf -----------------------------------*/
// Get alternative hardware timer overflow flag
// Return: 1 - overflow, 0 - no overflow
uint32_t os_tick_ovf (void) {
return (0);
}
/*--------------------------- os_tick_irqack --------------------------------*/
// Acknowledge alternative hardware timer interrupt
void os_tick_irqack (void) {
/* ... */
}
#endif // (OS_SYSTICK == 0)
/*--------------------------- os_error --------------------------------------*/
/* OS Error Codes */
#define OS_ERROR_STACK_OVF 1
#define OS_ERROR_FIFO_OVF 2
#define OS_ERROR_MBX_OVF 3
extern osThreadId svcThreadGetId (void);
void os_error (uint32_t error_code) {
/* This function is called when a runtime error is detected. */
/* Parameter 'error_code' holds the runtime error code. */
/* HERE: include optional code to be executed on runtime error. */
switch (error_code) {
case OS_ERROR_STACK_OVF:
/* Stack overflow detected for the currently running task. */
/* Thread can be identified by calling svcThreadGetId(). */
break;
case OS_ERROR_FIFO_OVF:
/* ISR FIFO Queue buffer overflow detected. */
break;
case OS_ERROR_MBX_OVF:
/* Mailbox overflow detected. */
break;
}
for (;;);
}
/*----------------------------------------------------------------------------
* RTX Configuration Functions
*---------------------------------------------------------------------------*/
#include "RTX_CM_lib.h"
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

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;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f2xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 18-April-2011
;* Description : STM32F2xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00007000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

536
IDE/MDK5-ARM/Projects/EchoClient/RTE/Device/STM32F207IG/system_stm32f2xx.c
View File

@ -1,536 +0,0 @@
/**
******************************************************************************
* @file system_stm32f2xx.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-April-2011
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F2xx devices,
* and is generated by the clock configuration tool
* "STM32f2xx_Clock_Configuration_V1.0.0.xls"
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f2xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
* in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F2xx device revision | Rev B and Y
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 120000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 120000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 240
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 5
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 3
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Enabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f2xx_system
* @{
*/
/** @addtogroup STM32F2xx_System_Private_Includes
* @{
*/
#include "stm32f2xx.h"
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Defines
* @{
*/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM322xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 25
#define PLL_N 240
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 5
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 120000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @Note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
static void SetSysClock(void)
{
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
/**
* @brief Setup the external memory controller. Called in startup_stm32f2xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f2xx.s before jump to main.
* This function configures the external SRAM mounted on STM322xG_EVAL board
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
| PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
| PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+
+-------------------+--------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR = 0x00000078;
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcc0ccccc;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xa2aa0a0a;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xf3ff0f0f;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xc00000cc;
GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xaaaa800a;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xffffc00f;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xaa000aaa;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xff000fff;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00080aaa;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000c0fff;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR = 0x00000001;
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010400;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 0;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 4;
p.FSMC_BusTurnAroundDuration = 1;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
*/
}
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::File System
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: FS_Config.c
* Purpose: File System Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>File System
// <i>Define File System global parameters
// <o>Number of open files <4-16>
// <i>Define number of files that can be
// <i>opened at the same time.
// <i>Default: 8
#define NUM_FILES 8
// <o>FAT Name Cache Size <0-1000000>
// <i>Define number of cached FAT file or directory names.
// <i>48 bytes of RAM is required for each cached name.
#define FAT_NAME_CACHE_SIZE 0
// <e>Relocate FAT Name Cache Buffer
// <i>Locate Cache Buffer at a specific address.
#define FAT_NAME_CACHE_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define the Cache buffer base address.
#define FAT_NAME_CACHE_ADDR 0x60000000
// </e>
// </h>
#include "..\RTE_Components.h"
#ifdef RTE_FileSystem_Drive_RAM
#include "FS_Config_RAM.h"
#endif
#ifdef RTE_FileSystem_Drive_NOR_0
#include "FS_Config_NOR_0.h"
#endif
#ifdef RTE_FileSystem_Drive_NOR_1
#include "FS_Config_NOR_1.h"
#endif
#ifdef RTE_FileSystem_Drive_NAND_0
#include "FS_Config_NAND_0.h"
#endif
#ifdef RTE_FileSystem_Drive_NAND_1
#include "FS_Config_NAND_1.h"
#endif
#ifdef RTE_FileSystem_Drive_MC_0
#include "FS_Config_MC_0.h"
#endif
#ifdef RTE_FileSystem_Drive_MC_1
#include "FS_Config_MC_1.h"
#endif
#ifdef RTE_FileSystem_Drive_USB_0
#include "FS_Config_USB_0.h"
#endif
#ifdef RTE_FileSystem_Drive_USB_1
#include "FS_Config_USB_1.h"
#endif
#include "fs_config.h"

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::File System:Drive
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: FS_Config_MC_0.h
* Purpose: File System Configuration for Memory Card Drive
* Rev.: V5.01
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Memory Card Drive 0
// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
#define MC0_ENABLE 1
// <o>Connect to hardware via Driver_MCI# <0-255>
// <i>Select driver control block for hardware interface
#define MC0_MCI_DRIVER 0
// <o>Connect to hardware via Driver_SPI# <0-255>
// <i>Select driver control block for hardware interface when in SPI mode
#define MC0_SPI_DRIVER 0
// <o>Memory Card Interface Mode <0=>Native <1=>SPI
// <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
// <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
// <i>When using SPI both Driver_SPI# and Driver_MCI# must be specified
// <i>since the MCI driver provides the control interface lines.
#define MC0_SPI 0
// <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Drive Cache stores data sectors and may be increased to speed-up
// <i>file read/write operations on this drive (default: 4 KB)
#define MC0_CACHE_SIZE 4
// <e>Locate Drive Cache and Drive Buffer
// <i>Some microcontrollers support DMA only in specific memory areas and
// <i>require to locate the drive buffers at a fixed address.
#define MC0_CACHE_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Set buffer base address to RAM areas that support DMA with the drive.
#define MC0_CACHE_ADDR 0x7FD00000
// </e>
// <q>Use FAT Journal
// <i>Protect File Allocation Table and Directory Entries for
// <i>fail-safe operation.
#define MC0_FAT_JOURNAL 0
// <q>Default Drive "M0:"
// <i>Use this drive when no drive letter is specified.
#define MC0_DEFAULT_DRIVE 1
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config.c
* Purpose: Network Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Definitions
// <i> Global Network System definitions
// <s.15>Local Host Name
// <i> This is the name under which embedded host can be
// <i> accessed on a local area network.
// <i> Default: "my_host"
#define NET_HOST_NAME "my_host"
// <o>Memory Pool size <1536-262144:4><#/4>
// <i> This is the size of a memory pool in bytes. Buffers for
// <i> Network packets are allocated from this memory pool.
// <i> Default: 12000 bytes
#define NET_MEM_SIZE 3000
// </h>
#include "..\RTE_Components.h"
#ifdef RTE_Network_Interface_ETH_0
#include "Net_Config_ETH_0.h"
#endif
#ifdef RTE_Network_Interface_ETH_1
#include "Net_Config_ETH_1.h"
#endif
#ifdef RTE_Network_Interface_PPP_0
#include "Net_Config_PPP_0.h"
#endif
#ifdef RTE_Network_Interface_PPP_1
#include "Net_Config_PPP_1.h"
#endif
#ifdef RTE_Network_Interface_SLIP_0
#include "Net_Config_SLIP_0.h"
#endif
#ifdef RTE_Network_Interface_SLIP_1
#include "Net_Config_SLIP_1.h"
#endif
#ifdef RTE_Network_Socket_UDP
#include "Net_Config_UDP.h"
#endif
#ifdef RTE_Network_Socket_TCP
#include "Net_Config_TCP.h"
#endif
#ifdef RTE_Network_Socket_BSD
#include "Net_Config_BSD.h"
#endif
#ifdef RTE_Network_Web_Server_RO
#include "Net_Config_HTTP_Server.h"
#endif
#ifdef RTE_Network_Web_Server_FS
#include "Net_Config_HTTP_Server.h"
#endif
#ifdef RTE_Network_Telnet_Server
#include "Net_Config_Telnet_Server.h"
#endif
#ifdef RTE_Network_TFTP_Server
#include "Net_Config_TFTP_Server.h"
#endif
#ifdef RTE_Network_TFTP_Client
#include "Net_Config_TFTP_Client.h"
#endif
#ifdef RTE_Network_FTP_Server
#include "Net_Config_FTP_Server.h"
#endif
#ifdef RTE_Network_FTP_Client
#include "Net_Config_FTP_Client.h"
#endif
#ifdef RTE_Network_DNS_Client
#include "Net_Config_DNS_Client.h"
#endif
#ifdef RTE_Network_SMTP_Client
#include "Net_Config_SMTP_Client.h"
#endif
#ifdef RTE_Network_SNMP_Agent
#include "Net_Config_SNMP_Agent.h"
#endif
#ifdef RTE_Network_SNTP_Client
#include "Net_Config_SNTP_Client.h"
#endif
#include "net_config.h"
/**
\addtogroup net_genFunc
@{
*/
/**
\fn void net_sys_error (ERROR_CODE error)
\ingroup net_cores
\brief Network system error handler.
*/
void net_sys_error (ERROR_CODE error) {
/* This function is called when a fatal error is encountered. */
/* The normal program execution is not possible anymore. */
switch (error) {
case ERR_MEM_ALLOC:
/* Out of memory */
break;
case ERR_MEM_FREE:
/* Trying to release non existing memory block */
break;
case ERR_MEM_CORRUPT:
/* Memory Link pointer Corrupted */
/* More data written than the size of allocated mem block */
break;
case ERR_MEM_LOCK:
/* Locked Memory management function (alloc/free) re-entered */
break;
case ERR_UDP_ALLOC:
/* Out of UDP Sockets */
break;
case ERR_TCP_ALLOC:
/* Out of TCP Sockets */
break;
case ERR_TCP_STATE:
/* TCP State machine in undefined state */
break;
}
/* End-less loop */
while (1);
}
/**
@}
*/

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Socket
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_BSD.h
* Purpose: Network Configuration BSD Sockets
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Berkley (BSD) Sockets
#define BSD_ENABLE 1
// <o>Number of BSD Sockets <1-20>
// <i> Number of available Berkeley Sockets
// <i> Default: 2
#define BSD_NUM_SOCKS 7
// <o>Number of Streaming Server Sockets <0-20>
// <i> Defines a number of Streaming (TCP) Server sockets,
// <i> that listen for an incoming connection from the client.
// <i> Default: 1
#define BSD_SERVER_SOCKS 1
// <o>Receive Timeout in seconds <0-600>
// <i> A timeout for socket receive in blocking mode.
// <i> Timeout value of 0 means indefinite timeout.
// <i> Default: 20
#define BSD_RECEIVE_TOUT 20
// <q>Hostname Resolver
// <i> Enable or disable Berkeley style hostname resolver.
#define BSD_HOSTNAME_ENABLE 0
// </h>

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IDE/MDK5-ARM/Projects/EchoClient/RTE/Network/Net_Config_DNS_Client.h
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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Service
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_DNS_Client.h
* Purpose: Network Configuration DNS Client
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>DNS Client
#define DNS_CLIENT_ENABLE 1
// <o>Cache Table size <5-100>
// <i> Number of cached DNS host names/IP addresses
// <i> Default: 20
#define DNS_CLIENT_TAB_SIZE 20
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Interface
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_ETH_0.h
* Purpose: Network Configuration ETH Interface
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Ethernet Network Interface 0
#define ETH0_ENABLE 1
// <o>Connect to hardware via Driver_ETH# <0-255>
// <i>Select driver control block for MAC and PHY interface
#define ETH0_DRIVER 0
// <h>MAC Address
// <i> Local Ethernet MAC Address
// <i> Value FF:FF:FF:FF:FF:FF is not allowed.
// <i> It is an ethernet Broadcast MAC address.
// <o>Address byte 1 <0x00-0xff:2>
// <i> LSB is an ethernet Multicast bit.
// <i> Must be 0 for local MAC address.
// <i> Default: 0x1E
#define ETH0_MAC1 0x1E
// <o>Address byte 2 <0x00-0xff>
// <i> Default: 0x30
#define ETH0_MAC2 0x30
// <o>Address byte 3 <0x00-0xff>
// <i> Default: 0x6C
#define ETH0_MAC3 0x6C
// <o>Address byte 4 <0x00-0xff>
// <i> Default: 0xA2
#define ETH0_MAC4 0xA2
// <o>Address byte 5 <0x00-0xff>
// <i> Default: 0x45
#define ETH0_MAC5 0x45
// <o>Address byte 6 <0x00-0xff>
// <i> Default: 0x5E
#define ETH0_MAC6 0x5E
// </h>
// <h>IP Address
// <i> Local Static IP Address
// <i> Value 255.255.255.255 is not allowed.
// <i> It is a Broadcast IP address.
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define ETH0_IP1 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define ETH0_IP2 168
// <o>Address byte 3 <0-255>
// <i> Default: 0
#define ETH0_IP3 11
// <o>Address byte 4 <0-255>
// <i> Default: 100
#define ETH0_IP4 101
// </h>
// <h>Subnet mask
// <i> Local Subnet mask
// <o>Mask byte 1 <0-255>
// <i> Default: 255
#define ETH0_MASK1 255
// <o>Mask byte 2 <0-255>
// <i> Default: 255
#define ETH0_MASK2 255
// <o>Mask byte 3 <0-255>
// <i> Default: 255
#define ETH0_MASK3 255
// <o>Mask byte 4 <0-255>
// <i> Default: 0
#define ETH0_MASK4 0
// </h>
// <h>Default Gateway
// <i> Default Gateway IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define ETH0_GW1 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define ETH0_GW2 168
// <o>Address byte 3 <0-255>
// <i> Default: 0
#define ETH0_GW3 11
// <o>Address byte 4 <0-255>
// <i> Default: 254
#define ETH0_GW4 1
// </h>
// <h>Primary DNS Server
// <i> Primary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define ETH0_PRI_DNS1 192
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define ETH0_PRI_DNS2 168
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define ETH0_PRI_DNS3 11
// <o>Address byte 4 <0-255>
// <i> Default: 129
#define ETH0_PRI_DNS4 1
// </h>
// <h>Secondary DNS Server
// <i> Secondary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define ETH0_SEC_DNS1 194
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define ETH0_SEC_DNS2 25
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define ETH0_SEC_DNS3 2
// <o>Address byte 4 <0-255>
// <i> Default: 130
#define ETH0_SEC_DNS4 130
// </h>
// <h>ARP Definitions
// <i> Address Resolution Protocol Definitions
// <o>Cache Table size <5-100>
// <i> Number of cached hardware/IP addresses
// <i> Default: 10
#define ETH0_ARP_TAB_SIZE 10
// <o>Cache Timeout in seconds <5-255>
// <i> A timeout for a cached hardware/IP addresses
// <i> Default: 150
#define ETH0_ARP_CACHE_TOUT 150
// <o>Number of Retries <0-20>
// <i> Number of Retries to resolve an IP address
// <i> before ARP module gives up
// <i> Default: 4
#define ETH0_ARP_MAX_RETRY 4
// <o>Resend Timeout in seconds <1-10>
// <i> A timeout to resend the ARP Request
// <i> Default: 2
#define ETH0_ARP_RESEND_TOUT 2
// <q>Send Notification on Address changes
// <i> When this option is enabled, the embedded host
// <i> will send a Gratuitous ARP notification at startup,
// <i> or when the device IP address has changed.
// <i> Default: Disabled
#define ETH0_ARP_NOTIFY 0
// </h>
// <e>IGMP Group Management
// <i> Enable or disable Internet Group Management Protocol
#define ETH0_IGMP_ENABLE 0
// <o>Membership Table size <2-50>
// <i> Number of Groups this host can join
// <i> Default: 5
#define ETH0_IGMP_TAB_SIZE 5
// </e>
// <q>NetBIOS Name Service
// <i> When this option is enabled, the embedded host can be
// <i> accessed by his name on the local LAN using NBNS protocol.
// <i> You need to modify also the number of UDP Sockets,
// <i> because NBNS protocol uses one UDP socket to run.
#define ETH0_NBNS_ENABLE 0
// <e>Dynamic Host Configuration
// <i> When this option is enabled, local IP address, Net Mask
// <i> and Default Gateway are obtained automatically from
// <i> the DHCP Server on local LAN.
// <i> You need to modify also the number of UDP Sockets,
// <i> because DHCP protocol uses one UDP socket to run.
#define ETH0_DHCP_ENABLE 1
// <s.40>Vendor Class Identifier
// <i> This value is optional. If specified, it is added
// <i> to DHCP request message, identifying vendor type.
// <i> Default: ""
#define ETH0_DHCP_VCID ""
// <q>Bootfile Name
// <i> This value is optional. If enabled, the Bootfile Name
// <i> (option 67) is also requested from DHCP server.
// <i> Default: disabled
#define ETH0_DHCP_BOOTFILE 0
// <q>NTP Servers
// <i> This value is optional. If enabled, a list of NTP Servers
// <i> (option 42) is also requested from DHCP server.
// <i> Default: disabled
#define ETH0_DHCP_NTP_SERVERS 0
// </e>
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Socket
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_TCP.h
* Purpose: Network Configuration TCP Sockets
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>TCP Sockets
#define TCP_ENABLE 1
// <o>Number of TCP Sockets <1-20>
// <i> Number of available TCP sockets
// <i> Default: 5
#define TCP_NUM_SOCKS 10
// <o>Number of Retries <0-20>
// <i> How many times TCP module will try to retransmit data
// <i> before giving up. Increase this value for high-latency
// <i> and low_throughput networks.
// <i> Default: 5
#define TCP_MAX_RETRY 5
// <o>Retry Timeout in seconds <1-10>
// <i> If data frame not acknowledged within this time frame,
// <i> TCP module will try to resend the data again.
// <i> Default: 4
#define TCP_RETRY_TOUT 4
// <o>Default Connect Timeout in seconds <1-600>
// <i> Default TCP Socket Keep Alive timeout. When it expires
// <i> with no TCP data frame send, TCP Connection is closed.
// <i> Default: 120
#define TCP_DEFAULT_TOUT 120
// <o>Maximum Segment Size <536-1460>
// <i> The Maximum Segment Size specifies the maximum
// <i> number of bytes in the TCP segment's Data field.
// <i> Default: 1460
#define TCP_MAX_SEG_SIZE 1460
// <o>Receive Window Size <536-65535>
// <i> Receive Window Size specifies the size of data,
// <i> that the socket is able to buffer in flow-control mode.
// <i> Default: 4380
#define TCP_RECEIVE_WIN_SIZE 4380
// </h>
// TCP Initial Retransmit period in seconds
#define TCP_INITIAL_RETRY_TOUT 1
// TCP SYN frame retransmit period in seconds
#define TCP_SYN_RETRY_TOUT 2
// Number of retries to establish a connection
#define TCP_CONNECT_RETRY 7

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Socket
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_UDP.h
* Purpose: Network Configuration UDP Sockets
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>UDP Sockets
#define UDP_ENABLE 1
// <o>Number of UDP Sockets <1-20>
// <i> Number of available UDP sockets
// <i> Default: 5
#define UDP_NUM_SOCKS 15
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Debug.c
* Purpose: Network Debug Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <q>Print Time Stamp
// <i> Enable printing the time-info in debug messages
#define DBG_TIME 1
// <h>TCPnet Debug Definitions
// <o>Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Dynamic Memory debug messages
#define DBG_MEM 1
// <o>Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Ethernet debug messages
#define DBG_ETH 0
// <o>PPP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off PPP debug messages
#define DBG_PPP 0
// <o>SLIP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off SLIP debug messages
#define DBG_SLIP 0
// <o>ARP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off ARP debug messages
#define DBG_ARP 0
// <o>IP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off IP debug messages
#define DBG_IP 1
// <o>ICMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off ICMP debug messages
#define DBG_ICMP 1
// <o>IGMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off IGMP debug messages
#define DBG_IGMP 1
// <o>UDP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off UDP debug messages
#define DBG_UDP 1
// <o>TCP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TCP debug messages
#define DBG_TCP 2
// <o>NBNS Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off NetBIOS Name Service debug messages
#define DBG_NBNS 1
// <o>DHCP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Dynamic Host Configuration debug messages
#define DBG_DHCP 1
// <o>DNS Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Domain Name Service debug messages
#define DBG_DNS 1
// <o>SNMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Simple Network Management debug messages
#define DBG_SNMP 1
// <o>SNTP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Simple Network Time debug messages
#define DBG_SNTP 1
// <o>BSD Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off BSD Interface debug messages
#define DBG_BSD 1
// </h>
// <h>Application Debug Definitions
// <o>HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Web Server debug messages
#define DBG_HTTP_SERVER 1
// <o>FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off FTP Server debug messages
#define DBG_FTP_SERVER 1
// <o>FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off FTP Client debug messages
#define DBG_FTP_CLIENT 1
// <o>Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Telnet Server debug messages
#define DBG_TELNET_SERVER 1
// <o>TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TFTP Server debug messages
#define DBG_TFTP_SERVER 1
// <o>TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TFTP Client debug messages
#define DBG_TFTP_CLIENT 1
// <o>SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off SMTP Client debug messages
#define DBG_SMTP_CLIENT 1
// </h>
#include "net_debug.h"
/**
\fn void net_debug_init (void)
\brief Initialize Network Debug Interface.
*/
void net_debug_init (void) {
/* Add your code to initialize the Debug output. This is usually the */
/* serial interface. The function is called at TCPnet system startup. */
/* You may need to customize also the 'putchar()' function. */
}

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/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'EchoClient'
* Target: 'EchoClient'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */
#define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */
#define RTE_Drivers_MCI0 /* Driver MCI0 */
#define RTE_Drivers_PHY_ST802RT1 /* Driver PHY ST802RT1 */
#define RTE_FileSystem_Core /* File System Core */
#define RTE_FileSystem_LFN /* File System with Long Filename support */
#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */
#define RTE_Network_Core /* Network Core */
#define RTE_Network_Debug /* Network Debug Version */
#define RTE_Network_DNS_Client /* Network DNS Client */
#define RTE_Network_Interface_ETH_0 /* Network Interface ETH 0 */
#define RTE_Network_Socket_BSD /* Network Socket BSD */
#define RTE_Network_Socket_TCP /* Network Socket TCP */
#define RTE_Network_Socket_UDP /* Network Socket UDP */
#endif /* RTE_COMPONENTS_H */

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/* config-FS.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// <<< Use Configuration Wizard in Context Menu >>>
// <h> wolfCrypt Configuration
// <h>Cert/Key Strage
// <o>Cert Storage <0=> SD Card <1=> Mem Buff (1024bytes) <2=> Mem Buff (2048bytes)
#define MDK_CONF_CERT_BUFF 0
#if MDK_CONF_CERT_BUFF== 1
#define USE_CERT_BUFFERS_1024
#elif MDK_CONF_CERT_BUFF == 2
#define USE_CERT_BUFFERS_2048
#endif
//</h>
// <h>Crypt Algrithm
// <h>MD5, SHA, SHA-256, AES, RC4, ASN, RSA
// </h>
// <e>MD2
#define MDK_CONF_MD2 0
#if MDK_CONF_MD2 == 1
#define CYASSL_MD2
#endif
// </e>
// <e>MD4
#define MDK_CONF_MD4 1
#if MDK_CONF_MD4 == 0
#define NO_MD4
#endif
// </e>
// <e>SHA-384
// <i>This has to be with SHA512
#define MDK_CONF_SHA384 0
#if MDK_CONF_SHA384 == 1
#define CYASSL_SHA384
#endif
// </e>
// <e>SHA-512
#define MDK_CONF_SHA512 0
#if MDK_CONF_SHA512 == 1
#define CYASSL_SHA512
#endif
// </e>
// <e>RIPEMD
#define MDK_CONF_RIPEMD 0
#if MDK_CONF_RIPEMD == 1
#define CYASSL_RIPEMD
#endif
// </e>
// <e>HMAC
#define MDK_CONF_HMAC 1
#if MDK_CONF_HMAC == 0
#define NO_HMAC
#endif
// </e>
// <e>HC128
#define MDK_CONF_HC128 0
#if MDK_CONF_HC128 == 1
#define HAVE_HC128
#endif
// </e>
// <e>RABBIT
#define MDK_CONF_RABBIT 1
#if MDK_CONF_RABBI == 0
#define NO_RABBIT
#endif
// </e>
// <e>AEAD
#define MDK_CONF_AEAD 0
#if MDK_CONF_AEAD == 1
#define HAVE_AEAD
#endif
// </e>
// <e>DES3
#define MDK_CONF_DES3 1
#if MDK_CONF_DES3 == 0
#define NO_DES3
#endif
// </e>
// <e>CAMELLIA
#define MDK_CONF_CAMELLIA 0
#if MDK_CONF_CAMELLIA == 1
#define HAVE_CAMELLIA
#endif
// </e>
// <e>DH
// <i>need this for CYASSL_SERVER, OPENSSL_EXTRA
#define MDK_CONF_DH 1
#if MDK_CONF_DH == 0
#define NO_DH
#endif
// </e>
// <e>DSA
#define MDK_CONF_DSA 1
#if MDK_CONF_DSA == 0
#define NO_DSA
#endif
// </e>
// <e>PWDBASED
#define MDK_CONF_PWDBASED 1
#if MDK_CONF_PWDBASED == 0
#define NO_PWDBASED
#endif
// </e>
// <e>ECC
#define MDK_CONF_ECC 0
#if MDK_CONF_ECC == 1
#define HAVE_ECC
#endif
// </e>
// <e>PSK
#define MDK_CONF_PSK 1
#if MDK_CONF_PSK == 0
#define NO_PSK
#endif
// </e>
// <e>AESCCM (Turn off Hardware Crypt)
#define MDK_CONF_AESCCM 0
#if MDK_CONF_AESCCM == 1
#define HAVE_AESCCM
#endif
// </e>
// <e>AESGCM (Turn off Hardware Crypt)
#define MDK_CONF_AESGCM 0
#if MDK_CONF_AESGCM == 1
#define HAVE_AESGCM
#define BUILD_AESGCM
#endif
// </e>
// <e>NTRU (need License, "crypto_ntru.h")
#define MDK_CONF_NTRU 0
#if MDK_CONF_NTRU == 1
#define HAVE_NTRU
#endif
// </e>
// </h>
// <h>Hardware Crypt (See document for usage)
// <e>Hardware RNG
#define MDK_CONF_STM32F2_RNG 0
#if MDK_CONF_STM32F2_RNG == 1
#define STM32F2_RNG
#else
#endif
// </e>
// <e>Hardware Crypt
#define MDK_CONF_STM32F2_CRYPTO 0
#if MDK_CONF_STM32F2_CRYPTO == 1
#define STM32F2_CRYPTO
#endif
// </e>
// </h>
//</h>
// <<< end of configuration section >>>

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/* config-RTX-TCP-FS.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/**** CyaSSL for KEIL-RL Configuration ****/
#define __CORTEX_M3__
#define CYASSL_MDK_ARM
#define NO_WRITEV
#define NO_CYASSL_DIR
#define NO_MAIN_DRIVER
#define CYASSL_DER_LOAD
#define HAVE_NULL_CIPHER
#define HAVE_KEIL_RTX
#define CYASSL_CMSIS_RTOS
#define CYASSL_KEIL_TCP_NET
// <<< Use Configuration Wizard in Context Menu >>>
// <h> CyaSSL Configuration
// <h>SSL (Included by default)
// </h>
// <e>TLS
#define MDK_CONF_TLS 1
#if MDK_CONF_TLS == 0
#define NO_TLS
#endif
// </e>
// <e>CRL
#define MDK_CONF_DER_LOAD 0
#if MDK_CONF_DER_LOAD == 1
#define CYASSL_DER_LOAD
#endif
// </e>
// <e>OpenSSL Extra
#define MDK_CONF_OPENSSL_EXTRA 1
#if MDK_CONF_OPENSSL_EXTRA == 1
#define OPENSSL_EXTRA
#endif
// </e>
//</h>
// <h>Cert/Key Generation
// <e>CertGen
#define MDK_CONF_CERT_GEN 0
#if MDK_CONF_CERT_GEN == 1
#define CYASSL_CERT_GEN
#endif
// </e>
// <e>KeyGen
#define MDK_CONF_KEY_GEN 0
#if MDK_CONF_KEY_GEN == 1
#define CYASSL_KEY_GEN
#endif
// </e>
//</h>
// <h>Others
// <e>Inline
#define MDK_CONF_INLINE 0
#if MDK_CONF_INLINE == 0
#define NO_INLINE
#endif
// </e>
// <h>Debug
// <e>Debug Message
#define MDK_CONF_DebugMessage 0
#if MDK_CONF_DebugMessage == 1
#define DEBUG_CYASSL
#endif
// </e>
// <e>Check malloc
#define MDK_CONF_CheckMalloc 1
#if MDK_CONF_CheckMalloc == 1
#define CYASSL_MALLOC_CHECK
#endif
// </e>
// </h>
// <e>ErrNo.h
#define MDK_CONF_ErrNo 0
#if MDK_CONF_ErrNo == 1
#define HAVE_ERRNO
#endif
// </e>
// <e>Error Strings
#define MDK_CONF_ErrorStrings 1
#if MDK_CONF_ErrorStrings == 0
#define NO_ERROR_STRINGS
#endif
// </e>
// <e>zlib (need "zlib.h")
#define MDK_CONF_LIBZ 0
#if MDK_CONF_LIBZ == 1
#define HAVE_LIBZ
#endif
// </e>
// <e>CAVIUM (need CAVIUM headers)
#define MDK_CONF_CAVIUM 0
#if MDK_CONF_CAVIUM == 1
#define HAVE_CAVIUM
#endif
// </e>
// <e>Small Stack
#define MDK_CONF_SmallStack 1
#if MDK_CONF_SmallStack == 0
#define NO_CYASSL_SMALL_STACK
#endif
// </e>
// <e>Use Fast Math
#define MDK_CONF_FASTMATH 0
#if MDK_CONF_FASTMATH == 1
#define USE_FAST_MATH
#endif
// </e>
// </h>
// <<< end of configuration section >>>

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/* settings.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* Place OS specific preprocessor flags, defines, includes here, will be
included into every file because types.h includes it */
#ifndef CTAO_CRYPT_SETTINGS_H
#define CTAO_CRYPT_SETTINGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Uncomment next line if using IPHONE */
/* #define IPHONE */
/* Uncomment next line if using ThreadX */
/* #define THREADX */
/* Uncomment next line if using Micrium ucOS */
/* #define MICRIUM */
/* Uncomment next line if using Mbed */
/* #define MBED */
/* Uncomment next line if using Microchip PIC32 ethernet starter kit */
/* #define MICROCHIP_PIC32 */
/* Uncomment next line if using Microchip TCP/IP stack, version 5 */
/* #define MICROCHIP_TCPIP_V5 */
/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */
/* #define MICROCHIP_TCPIP */
/* Uncomment next line if using FreeRTOS */
/* #define FREERTOS */
/* Uncomment next line if using FreeRTOS Windows Simulator */
/* #define FREERTOS_WINSIM */
/* Uncomment next line if using RTIP */
/* #define EBSNET */
/* Uncomment next line if using lwip */
/* #define CYASSL_LWIP */
/* Uncomment next line if building CyaSSL for a game console */
/* #define CYASSL_GAME_BUILD */
/* Uncomment next line if building CyaSSL for LSR */
/* #define CYASSL_LSR */
/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */
/* #define FREESCALE_MQX */
/* Uncomment next line if using STM32F2 */
/* #define CYASSL_STM32F2 */
/* Uncomment next line if using Comverge settings */
/* #define COMVERGE */
/* Uncomment next line if using QL SEP settings */
/* #define CYASSL_QL */
#include <cyassl/ctaocrypt/visibility.h>
#ifdef IPHONE
#define SIZEOF_LONG_LONG 8
#endif
#ifdef COMVERGE
#define THREADX
#define HAVE_NETX
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define NO_RSA
#define NO_SESSION_CACHE
#define HAVE_ECC
#endif
#ifdef THREADX
#define SIZEOF_LONG_LONG 8
#endif
#ifdef HAVE_NETX
#include "nx_api.h"
#endif
#ifdef MICROCHIP_PIC32
#define SIZEOF_LONG_LONG 8
#define SINGLE_THREADED
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#endif
#ifdef MICROCHIP_TCPIP_V5
/* include timer functions */
#include "TCPIP Stack/TCPIP.h"
#endif
#ifdef MICROCHIP_TCPIP
/* include timer, NTP functions */
#include "system/system_services.h"
#ifdef MICROCHIP_MPLAB_HARMONY
#include "tcpip/tcpip.h"
#else
#include "tcpip/sntp.h"
#endif
#endif
#ifdef MBED
#define SINGLE_THREADED
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#endif /* MBED */
#ifdef CYASSL_TYTO
#include "rand.h"
#define FREERTOS
#define NO_FILESYSTEM
#define CYASSL_USER_IO
#define NO_DEV_RANDOM
#define HAVE_ECC
#define HAVE_ECC_ENCRYPT
#define ECC_SHAMIR
#define HAVE_HKDF
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#define FP_MAX_BITS 512
#define NO_OLD_TLS
#define NO_MD4
#define NO_RABBIT
#define NO_HC128
#define NO_RSA
#define NO_DSA
#define NO_PWDBASED
#define NO_PSK
#endif
#ifdef FREERTOS_WINSIM
#define FREERTOS
#define USE_WINDOWS_API
#endif
/* Micrium will use Visual Studio for compilation but not the Win32 API */
#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \
&& !defined(EBSNET)
#define USE_WINDOWS_API
#endif
#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER)
#include <stdlib.h>
#define XMALLOC(s, h, type) malloc((s))
#define XFREE(p, h, type) free((p))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif
#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL)
#undef XMALLOC
#define XMALLOC yaXMALLOC
#undef XFREE
#define XFREE yaXFREE
#undef XREALLOC
#define XREALLOC yaXREALLOC
#endif
#ifdef FREERTOS
#ifndef NO_WRITEV
#define NO_WRITEV
#endif
#ifndef NO_SHA512
#define NO_SHA512
#endif
#ifndef NO_DH
#define NO_DH
#endif
#ifndef NO_DSA
#define NO_DSA
#endif
#ifndef NO_HC128
#define NO_HC128
#endif
#ifndef SINGLE_THREADED
#include "FreeRTOS.h"
#include "semphr.h"
#endif
#endif
#ifdef EBSNET
#include "rtip.h"
/* #define DEBUG_CYASSL */
#define NO_CYASSL_DIR /* tbd */
#if (POLLOS)
#define SINGLE_THREADED
#endif
#if (RTPLATFORM)
#if (!RTP_LITTLE_ENDIAN)
#define BIG_ENDIAN_ORDER
#endif
#else
#if (!KS_LITTLE_ENDIAN)
#define BIG_ENDIAN_ORDER
#endif
#endif
#if (WINMSP3)
#undef SIZEOF_LONG
#define SIZEOF_LONG_LONG 8
#else
#sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG
#endif
#define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC))
#define XFREE(p, h, type) (rtp_free(p))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif /* EBSNET */
#ifdef CYASSL_GAME_BUILD
#define SIZEOF_LONG_LONG 8
#if defined(__PPU) || defined(__XENON)
#define BIG_ENDIAN_ORDER
#endif
#endif
#ifdef CYASSL_LSR
#define HAVE_WEBSERVER
#define SIZEOF_LONG_LONG 8
#define CYASSL_LOW_MEMORY
#define NO_WRITEV
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define NO_DEV_RANDOM
#define NO_CYASSL_DIR
#define NO_RABBIT
#ifndef NO_FILESYSTEM
#define LSR_FS
#include "inc/hw_types.h"
#include "fs.h"
#endif
#define CYASSL_LWIP
#include <errno.h> /* for tcp errno */
#define CYASSL_SAFERTOS
#if defined(__IAR_SYSTEMS_ICC__)
/* enum uses enum */
#pragma diag_suppress=Pa089
#endif
#endif
#ifdef CYASSL_SAFERTOS
#ifndef SINGLE_THREADED
#include "SafeRTOS/semphr.h"
#endif
#include "SafeRTOS/heap.h"
#define XMALLOC(s, h, type) pvPortMalloc((s))
#define XFREE(p, h, type) vPortFree((p))
#define XREALLOC(p, n, h, t) pvPortRealloc((p), (n))
#endif
#ifdef CYASSL_LOW_MEMORY
#undef RSA_LOW_MEM
#define RSA_LOW_MEM
#undef CYASSL_SMALL_STACK
#define CYASSL_SMALL_STACK
#undef TFM_TIMING_RESISTANT
#define TFM_TIMING_RESISTANT
#endif
#ifdef FREESCALE_MQX
#define SIZEOF_LONG_LONG 8
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_RABBIT
#define NO_CYASSL_DIR
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#define FREESCALE_K70_RNGA
/* #define FREESCALE_K53_RNGB */
#include "mqx.h"
#ifndef NO_FILESYSTEM
#include "mfs.h"
#include "fio.h"
#endif
#ifndef SINGLE_THREADED
#include "mutex.h"
#endif
#define XMALLOC(s, h, t) (void *)_mem_alloc_system((s))
#define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));}
/* Note: MQX has no realloc, using fastmath above */
#endif
#ifdef CYASSL_STM32F2
#define SIZEOF_LONG_LONG 8
#define NO_DEV_RANDOM
#define NO_CYASSL_DIR
#define NO_RABBIT
#define STM32F2_RNG
#define STM32F2_CRYPTO
#define KEIL_INTRINSICS
#endif
#ifdef MICRIUM
#include "stdlib.h"
#include "net_cfg.h"
#include "ssl_cfg.h"
#include "net_secure_os.h"
#define CYASSL_TYPES
typedef CPU_INT08U byte;
typedef CPU_INT16U word16;
typedef CPU_INT32U word32;
#if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32)
#define SIZEOF_LONG 4
#undef SIZEOF_LONG_LONG
#else
#undef SIZEOF_LONG
#define SIZEOF_LONG_LONG 8
#endif
#define STRING_USER
#define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr)))
#define XSTRNCPY(pstr_dest, pstr_src, len_max) \
((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \
(CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max)))
#define XSTRNCMP(pstr_1, pstr_2, len_max) \
((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \
(CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max)))
#define XSTRSTR(pstr, pstr_srch) \
((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \
(CPU_CHAR *)(pstr_srch)))
#define XMEMSET(pmem, data_val, size) \
((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \
(CPU_SIZE_T)(size)))
#define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \
(void *)(psrc), (CPU_SIZE_T)(size)))
#define XMEMCMP(pmem_1, pmem_2, size) \
(((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \
(CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES)
#define XMEMMOVE XMEMCPY
#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
#define MICRIUM_MALLOC
#define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \
(CPU_SIZE_T)(s), (void *)0))
#define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \
(p), (void *)0))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif
#if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED)
#undef NO_FILESYSTEM
#else
#define NO_FILESYSTEM
#endif
#if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG)
#define DEBUG_CYASSL
#else
#undef DEBUG_CYASSL
#endif
#if (SSL_CFG_OPENSSL_EN == DEF_ENABLED)
#define OPENSSL_EXTRA
#else
#undef OPENSSL_EXTRA
#endif
#if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED)
#undef SINGLE_THREADED
#else
#define SINGLE_THREADED
#endif
#if (SSL_CFG_DH_EN == DEF_ENABLED)
#undef NO_DH
#else
#define NO_DH
#endif
#if (SSL_CFG_DSA_EN == DEF_ENABLED)
#undef NO_DSA
#else
#define NO_DSA
#endif
#if (SSL_CFG_PSK_EN == DEF_ENABLED)
#undef NO_PSK
#else
#define NO_PSK
#endif
#if (SSL_CFG_3DES_EN == DEF_ENABLED)
#undef NO_DES
#else
#define NO_DES
#endif
#if (SSL_CFG_AES_EN == DEF_ENABLED)
#undef NO_AES
#else
#define NO_AES
#endif
#if (SSL_CFG_RC4_EN == DEF_ENABLED)
#undef NO_RC4
#else
#define NO_RC4
#endif
#if (SSL_CFG_RABBIT_EN == DEF_ENABLED)
#undef NO_RABBIT
#else
#define NO_RABBIT
#endif
#if (SSL_CFG_HC128_EN == DEF_ENABLED)
#undef NO_HC128
#else
#define NO_HC128
#endif
#if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
#define BIG_ENDIAN_ORDER
#else
#undef BIG_ENDIAN_ORDER
#define LITTLE_ENDIAN_ORDER
#endif
#if (SSL_CFG_MD4_EN == DEF_ENABLED)
#undef NO_MD4
#else
#define NO_MD4
#endif
#if (SSL_CFG_WRITEV_EN == DEF_ENABLED)
#undef NO_WRITEV
#else
#define NO_WRITEV
#endif
#if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED)
#define NO_DEV_RANDOM
#else
#undef NO_DEV_RANDOM
#endif
#if (SSL_CFG_USER_IO_EN == DEF_ENABLED)
#define CYASSL_USER_IO
#else
#undef CYASSL_USER_IO
#endif
#if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED)
#undef LARGE_STATIC_BUFFERS
#undef STATIC_CHUNKS_ONLY
#else
#define LARGE_STATIC_BUFFERS
#define STATIC_CHUNKS_ONLY
#endif
#if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED)
#define CYASSL_DER_LOAD
#else
#undef CYASSL_DER_LOAD
#endif
#if (SSL_CFG_DTLS_EN == DEF_ENABLED)
#define CYASSL_DTLS
#else
#undef CYASSL_DTLS
#endif
#if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED)
#define CYASSL_CALLBACKS
#else
#undef CYASSL_CALLBACKS
#endif
#if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED)
#define USE_FAST_MATH
#else
#undef USE_FAST_MATH
#endif
#if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED)
#define TFM_TIMING_RESISTANT
#else
#undef TFM_TIMING_RESISTANT
#endif
#endif /* MICRIUM */
#ifdef CYASSL_QL
#ifndef CYASSL_SEP
#define CYASSL_SEP
#endif
#ifndef OPENSSL_EXTRA
#define OPENSSL_EXTRA
#endif
#ifndef SESSION_CERTS
#define SESSION_CERTS
#endif
#ifndef HAVE_AESCCM
#define HAVE_AESCCM
#endif
#ifndef ATOMIC_USER
#define ATOMIC_USER
#endif
#ifndef CYASSL_DER_LOAD
#define CYASSL_DER_LOAD
#endif
#ifndef KEEP_PEER_CERT
#define KEEP_PEER_CERT
#endif
#ifndef HAVE_ECC
#define HAVE_ECC
#endif
#ifndef SESSION_INDEX
#define SESSION_INDEX
#endif
#endif /* CYASSL_QL */
#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \
!defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY)
#define USE_CYASSL_MEMORY
#endif
#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS)
#undef KEEP_PEER_CERT
#define KEEP_PEER_CERT
#endif
/* stream ciphers except arc4 need 32bit alignment, intel ok without */
#ifndef XSTREAM_ALIGNMENT
#if defined(__x86_64__) || defined(__ia64__) || defined(__i386__)
#define NO_XSTREAM_ALIGNMENT
#else
#define XSTREAM_ALIGNMENT
#endif
#endif
/* if using hardware crypto and have alignment requirements, specify the
requirement here. The record header of SSL/TLS will prvent easy alignment.
This hint tries to help as much as possible. */
#ifndef CYASSL_GENERAL_ALIGNMENT
#ifdef CYASSL_AESNI
#define CYASSL_GENERAL_ALIGNMENT 16
#elif defined(XSTREAM_ALIGNMENT)
#define CYASSL_GENERAL_ALIGNMENT 4
#else
#define CYASSL_GENERAL_ALIGNMENT 0
#endif
#endif
#ifdef HAVE_CRL
/* not widely supported yet */
#undef NO_SKID
#define NO_SKID
#endif
/* Place any other flags or defines here */
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* CTAO_CRYPT_SETTINGS_H */

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IDE/MDK5-ARM/Projects/EchoClient/STM32_SWO.ini
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/******************************************************************************/
/* STM32_SWO.ini: STM32 Debugger Initialization File */
/******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>> //
/******************************************************************************/
/* This file is part of the uVision/ARM development tools. */
/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */
/* This software may only be used under the terms of a valid, current, */
/* end user licence from KEIL for a compatible version of KEIL software */
/* development tools. Nothing else gives you the right to use this software. */
/******************************************************************************/
FUNC void DebugSetup (void) {
// <h> Debug MCU Configuration
// <o1.0> DBG_SLEEP <i> Debug Sleep Mode
// <o1.1> DBG_STOP <i> Debug Stop Mode
// <o1.2> DBG_STANDBY <i> Debug Standby Mode
// <o1.5> TRACE_IOEN <i> Trace I/O Enable
// <o1.6..7> TRACE_MODE <i> Trace Mode
// <0=> Asynchronous
// <1=> Synchronous: TRACEDATA Size 1
// <2=> Synchronous: TRACEDATA Size 2
// <3=> Synchronous: TRACEDATA Size 4
// <o1.8> DBG_IWDG_STOP <i> Independant Watchdog Stopped when Core is halted
// <o1.9> DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
// <o1.10> DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
// <o1.11> DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
// <o1.12> DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
// <o1.13> DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
// <o1.14> DBG_CAN_STOP <i> CAN Stopped when Core is halted
// </h>
_WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR
}
DebugSetup(); // Debugger Setup

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/*----------------------------------------------------------------------------
* RL-ARM - RTX
*----------------------------------------------------------------------------
* Name: RTX_Conf_CM.C
* Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
* Rev.: V4.73
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
#include "cmsis_os.h"
/*----------------------------------------------------------------------------
* RTX User configuration part BEGIN
*---------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
//
// <h>Thread Configuration
// =======================
//
// <o>Number of concurrent running threads <0-250>
// <i> Defines max. number of threads that will run at the same time.
// <i> Default: 6
#ifndef OS_TASKCNT
#define OS_TASKCNT 6
#endif
// <o>Default Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines default stack size for threads with osThreadDef stacksz = 0
// <i> Default: 200
#ifndef OS_STKSIZE
#define OS_STKSIZE 300
#endif
// <o>Main Thread stack size [bytes] <64-32768:8><#/4>
// <i> Defines stack size for main thread.
// <i> Default: 200
#ifndef OS_MAINSTKSIZE
#define OS_MAINSTKSIZE 2000
#endif
// <o>Number of threads with user-provided stack size <0-250>
// <i> Defines the number of threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVCNT
#define OS_PRIVCNT 0
#endif
// <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
// <i> Defines the combined stack size for threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVSTKSIZE
#define OS_PRIVSTKSIZE 2500
#endif
// <q>Check for stack overflow
// <i> Includes the stack checking code for stack overflow.
// <i> Note that additional code reduces the Kernel performance.
#ifndef OS_STKCHECK
#define OS_STKCHECK 1
#endif
// <o>Processor mode for thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_RUNPRIV
#define OS_RUNPRIV 1
#endif
// </h>
// <h>RTX Kernel Timer Tick Configuration
// ======================================
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
// <i> Use the Cortex-M SysTick timer as a time-base for RTX.
#ifndef OS_SYSTICK
#define OS_SYSTICK 1
#endif
//
// <o>Timer clock value [Hz] <1-1000000000>
// <i> Defines the timer clock value.
// <i> Default: 12000000 (12MHz)
#ifndef OS_CLOCK
#define OS_CLOCK 12000000
#endif
// <o>Timer tick value [us] <1-1000000>
// <i> Defines the timer tick value.
// <i> Default: 1000 (1ms)
#ifndef OS_TICK
#define OS_TICK 1000
#endif
// </h>
// <h>System Configuration
// =======================
//
// <e>Round-Robin Thread switching
// ===============================
//
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN
#define OS_ROBIN 1
#endif
// <o>Round-Robin Timeout [ticks] <1-1000>
// <i> Defines how long a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBINTOUT
#define OS_ROBINTOUT 5
#endif
// </e>
// <e>User Timers
// ==============
// <i> Enables user Timers
#ifndef OS_TIMERS
#define OS_TIMERS 1
#endif
// <o>Timer Thread Priority
// <1=> Low
// <2=> Below Normal <3=> Normal <4=> Above Normal
// <5=> High
// <6=> Realtime (highest)
// <i> Defines priority for Timer Thread
// <i> Default: High
#ifndef OS_TIMERPRIO
#define OS_TIMERPRIO 5
#endif
// <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines stack size for Timer thread.
// <i> Default: 200
#ifndef OS_TIMERSTKSZ
#define OS_TIMERSTKSZ 50
#endif
// <o>Timer Callback Queue size <1-32>
// <i> Number of concurrent active timer callback functions.
// <i> Default: 4
#ifndef OS_TIMERCBQS
#define OS_TIMERCBQS 4
#endif
// </e>
// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
// <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries
// <48=> 48 entries <64=> 64 entries
// <96=> 96 entries
// <i> ISR functions store requests to this buffer,
// <i> when they are called from the interrupt handler.
// <i> Default: 16 entries
#ifndef OS_FIFOSZ
#define OS_FIFOSZ 16
#endif
// </h>
//------------- <<< end of configuration section >>> -----------------------
// Standard library system mutexes
// ===============================
// Define max. number system mutexes that are used to protect
// the arm standard runtime library. For microlib they are not used.
#ifndef OS_MUTEXCNT
#define OS_MUTEXCNT 8
#endif
/*----------------------------------------------------------------------------
* RTX User configuration part END
*---------------------------------------------------------------------------*/
#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
/*----------------------------------------------------------------------------
* Global Functions
*---------------------------------------------------------------------------*/
/*--------------------------- os_idle_demon ---------------------------------*/
void os_idle_demon (void) {
/* The idle demon is a system thread, running when no other thread is */
/* ready to run. */
for (;;) {
/* HERE: include optional user code to be executed when no thread runs.*/
}
}
#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
/*--------------------------- os_tick_init ----------------------------------*/
// Initialize alternative hardware timer as RTX kernel timer
// Return: IRQ number of the alternative hardware timer
int os_tick_init (void) {
return (-1); /* Return IRQ number of timer (0..239) */
}
/*--------------------------- os_tick_val -----------------------------------*/
// Get alternative hardware timer current value (0 .. OS_TRV)
uint32_t os_tick_val (void) {
return (0);
}
/*--------------------------- os_tick_ovf -----------------------------------*/
// Get alternative hardware timer overflow flag
// Return: 1 - overflow, 0 - no overflow
uint32_t os_tick_ovf (void) {
return (0);
}
/*--------------------------- os_tick_irqack --------------------------------*/
// Acknowledge alternative hardware timer interrupt
void os_tick_irqack (void) {
/* ... */
}
#endif // (OS_SYSTICK == 0)
/*--------------------------- os_error --------------------------------------*/
/* OS Error Codes */
#define OS_ERROR_STACK_OVF 1
#define OS_ERROR_FIFO_OVF 2
#define OS_ERROR_MBX_OVF 3
extern osThreadId svcThreadGetId (void);
void os_error (uint32_t error_code) {
/* This function is called when a runtime error is detected. */
/* Parameter 'error_code' holds the runtime error code. */
/* HERE: include optional code to be executed on runtime error. */
switch (error_code) {
case OS_ERROR_STACK_OVF:
/* Stack overflow detected for the currently running task. */
/* Thread can be identified by calling svcThreadGetId(). */
break;
case OS_ERROR_FIFO_OVF:
/* ISR FIFO Queue buffer overflow detected. */
break;
case OS_ERROR_MBX_OVF:
/* Mailbox overflow detected. */
break;
}
for (;;);
}
/*----------------------------------------------------------------------------
* RTX Configuration Functions
*---------------------------------------------------------------------------*/
#include "RTX_CM_lib.h"
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

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IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/RTE_Device.h
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IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/startup_stm32f2xx.s
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;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f2xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 18-April-2011
;* Description : STM32F2xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00002000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00007000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

536
IDE/MDK5-ARM/Projects/EchoServer/RTE/Device/STM32F207IG/system_stm32f2xx.c
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@ -1,536 +0,0 @@
/**
******************************************************************************
* @file system_stm32f2xx.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-April-2011
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F2xx devices,
* and is generated by the clock configuration tool
* "STM32f2xx_Clock_Configuration_V1.0.0.xls"
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f2xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
* in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F2xx device revision | Rev B and Y
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 120000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 120000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 240
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 5
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 3
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Enabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f2xx_system
* @{
*/
/** @addtogroup STM32F2xx_System_Private_Includes
* @{
*/
#include "stm32f2xx.h"
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Defines
* @{
*/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM322xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 25
#define PLL_N 240
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 5
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 120000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @Note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
static void SetSysClock(void)
{
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
/**
* @brief Setup the external memory controller. Called in startup_stm32f2xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f2xx.s before jump to main.
* This function configures the external SRAM mounted on STM322xG_EVAL board
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
| PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
| PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+
+-------------------+--------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR = 0x00000078;
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcc0ccccc;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xa2aa0a0a;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xf3ff0f0f;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xc00000cc;
GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xaaaa800a;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xffffc00f;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xaa000aaa;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xff000fff;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00080aaa;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000c0fff;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR = 0x00000001;
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010400;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 0;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 4;
p.FSMC_BusTurnAroundDuration = 1;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
*/
}
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

72
IDE/MDK5-ARM/Projects/EchoServer/RTE/File_System/FS_Config.c
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@ -1,72 +0,0 @@
/*------------------------------------------------------------------------------
* MDK Middleware - Component ::File System
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: FS_Config.c
* Purpose: File System Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>File System
// <i>Define File System global parameters
// <o>Number of open files <4-16>
// <i>Define number of files that can be
// <i>opened at the same time.
// <i>Default: 8
#define NUM_FILES 8
// <o>FAT Name Cache Size <0-1000000>
// <i>Define number of cached FAT file or directory names.
// <i>48 bytes of RAM is required for each cached name.
#define FAT_NAME_CACHE_SIZE 0
// <e>Relocate FAT Name Cache Buffer
// <i>Locate Cache Buffer at a specific address.
#define FAT_NAME_CACHE_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define the Cache buffer base address.
#define FAT_NAME_CACHE_ADDR 0x60000000
// </e>
// </h>
#include "..\RTE_Components.h"
#ifdef RTE_FileSystem_Drive_RAM
#include "FS_Config_RAM.h"
#endif
#ifdef RTE_FileSystem_Drive_NOR_0
#include "FS_Config_NOR_0.h"
#endif
#ifdef RTE_FileSystem_Drive_NOR_1
#include "FS_Config_NOR_1.h"
#endif
#ifdef RTE_FileSystem_Drive_NAND_0
#include "FS_Config_NAND_0.h"
#endif
#ifdef RTE_FileSystem_Drive_NAND_1
#include "FS_Config_NAND_1.h"
#endif
#ifdef RTE_FileSystem_Drive_MC_0
#include "FS_Config_MC_0.h"
#endif
#ifdef RTE_FileSystem_Drive_MC_1
#include "FS_Config_MC_1.h"
#endif
#ifdef RTE_FileSystem_Drive_USB_0
#include "FS_Config_USB_0.h"
#endif
#ifdef RTE_FileSystem_Drive_USB_1
#include "FS_Config_USB_1.h"
#endif
#include "fs_config.h"

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::File System:Drive
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: FS_Config_MC_0.h
* Purpose: File System Configuration for Memory Card Drive
* Rev.: V5.01
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Memory Card Drive 0
// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
#define MC0_ENABLE 1
// <o>Connect to hardware via Driver_MCI# <0-255>
// <i>Select driver control block for hardware interface
#define MC0_MCI_DRIVER 0
// <o>Connect to hardware via Driver_SPI# <0-255>
// <i>Select driver control block for hardware interface when in SPI mode
#define MC0_SPI_DRIVER 0
// <o>Memory Card Interface Mode <0=>Native <1=>SPI
// <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
// <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
// <i>When using SPI both Driver_SPI# and Driver_MCI# must be specified
// <i>since the MCI driver provides the control interface lines.
#define MC0_SPI 0
// <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Drive Cache stores data sectors and may be increased to speed-up
// <i>file read/write operations on this drive (default: 4 KB)
#define MC0_CACHE_SIZE 4
// <e>Locate Drive Cache and Drive Buffer
// <i>Some microcontrollers support DMA only in specific memory areas and
// <i>require to locate the drive buffers at a fixed address.
#define MC0_CACHE_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Set buffer base address to RAM areas that support DMA with the drive.
#define MC0_CACHE_ADDR 0x7FD00000
// </e>
// <q>Use FAT Journal
// <i>Protect File Allocation Table and Directory Entries for
// <i>fail-safe operation.
#define MC0_FAT_JOURNAL 0
// <q>Default Drive "M0:"
// <i>Use this drive when no drive letter is specified.
#define MC0_DEFAULT_DRIVE 1
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config.c
* Purpose: Network Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Definitions
// <i> Global Network System definitions
// <s.15>Local Host Name
// <i> This is the name under which embedded host can be
// <i> accessed on a local area network.
// <i> Default: "my_host"
#define NET_HOST_NAME "my_host"
// <o>Memory Pool size <1536-262144:4><#/4>
// <i> This is the size of a memory pool in bytes. Buffers for
// <i> Network packets are allocated from this memory pool.
// <i> Default: 12000 bytes
#define NET_MEM_SIZE 3000
// </h>
#include "..\RTE_Components.h"
#ifdef RTE_Network_Interface_ETH_0
#include "Net_Config_ETH_0.h"
#endif
#ifdef RTE_Network_Interface_ETH_1
#include "Net_Config_ETH_1.h"
#endif
#ifdef RTE_Network_Interface_PPP_0
#include "Net_Config_PPP_0.h"
#endif
#ifdef RTE_Network_Interface_PPP_1
#include "Net_Config_PPP_1.h"
#endif
#ifdef RTE_Network_Interface_SLIP_0
#include "Net_Config_SLIP_0.h"
#endif
#ifdef RTE_Network_Interface_SLIP_1
#include "Net_Config_SLIP_1.h"
#endif
#ifdef RTE_Network_Socket_UDP
#include "Net_Config_UDP.h"
#endif
#ifdef RTE_Network_Socket_TCP
#include "Net_Config_TCP.h"
#endif
#ifdef RTE_Network_Socket_BSD
#include "Net_Config_BSD.h"
#endif
#ifdef RTE_Network_Web_Server_RO
#include "Net_Config_HTTP_Server.h"
#endif
#ifdef RTE_Network_Web_Server_FS
#include "Net_Config_HTTP_Server.h"
#endif
#ifdef RTE_Network_Telnet_Server
#include "Net_Config_Telnet_Server.h"
#endif
#ifdef RTE_Network_TFTP_Server
#include "Net_Config_TFTP_Server.h"
#endif
#ifdef RTE_Network_TFTP_Client
#include "Net_Config_TFTP_Client.h"
#endif
#ifdef RTE_Network_FTP_Server
#include "Net_Config_FTP_Server.h"
#endif
#ifdef RTE_Network_FTP_Client
#include "Net_Config_FTP_Client.h"
#endif
#ifdef RTE_Network_DNS_Client
#include "Net_Config_DNS_Client.h"
#endif
#ifdef RTE_Network_SMTP_Client
#include "Net_Config_SMTP_Client.h"
#endif
#ifdef RTE_Network_SNMP_Agent
#include "Net_Config_SNMP_Agent.h"
#endif
#ifdef RTE_Network_SNTP_Client
#include "Net_Config_SNTP_Client.h"
#endif
#include "net_config.h"
/**
\addtogroup net_genFunc
@{
*/
/**
\fn void net_sys_error (ERROR_CODE error)
\ingroup net_cores
\brief Network system error handler.
*/
void net_sys_error (ERROR_CODE error) {
/* This function is called when a fatal error is encountered. */
/* The normal program execution is not possible anymore. */
switch (error) {
case ERR_MEM_ALLOC:
/* Out of memory */
break;
case ERR_MEM_FREE:
/* Trying to release non existing memory block */
break;
case ERR_MEM_CORRUPT:
/* Memory Link pointer Corrupted */
/* More data written than the size of allocated mem block */
break;
case ERR_MEM_LOCK:
/* Locked Memory management function (alloc/free) re-entered */
break;
case ERR_UDP_ALLOC:
/* Out of UDP Sockets */
break;
case ERR_TCP_ALLOC:
/* Out of TCP Sockets */
break;
case ERR_TCP_STATE:
/* TCP State machine in undefined state */
break;
}
/* End-less loop */
while (1);
}
/**
@}
*/

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Socket
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_BSD.h
* Purpose: Network Configuration BSD Sockets
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Berkley (BSD) Sockets
#define BSD_ENABLE 1
// <o>Number of BSD Sockets <1-20>
// <i> Number of available Berkeley Sockets
// <i> Default: 2
#define BSD_NUM_SOCKS 15
// <o>Number of Streaming Server Sockets <0-20>
// <i> Defines a number of Streaming (TCP) Server sockets,
// <i> that listen for an incoming connection from the client.
// <i> Default: 1
#define BSD_SERVER_SOCKS 1
// <o>Receive Timeout in seconds <0-600>
// <i> A timeout for socket receive in blocking mode.
// <i> Timeout value of 0 means indefinite timeout.
// <i> Default: 20
#define BSD_RECEIVE_TOUT 20
// <q>Hostname Resolver
// <i> Enable or disable Berkeley style hostname resolver.
#define BSD_HOSTNAME_ENABLE 0
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Service
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_DNS_Client.h
* Purpose: Network Configuration DNS Client
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>DNS Client
#define DNS_CLIENT_ENABLE 1
// <o>Cache Table size <5-100>
// <i> Number of cached DNS host names/IP addresses
// <i> Default: 20
#define DNS_CLIENT_TAB_SIZE 20
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Interface
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_ETH_0.h
* Purpose: Network Configuration ETH Interface
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Ethernet Network Interface 0
#define ETH0_ENABLE 1
// <o>Connect to hardware via Driver_ETH# <0-255>
// <i>Select driver control block for MAC and PHY interface
#define ETH0_DRIVER 0
// <h>MAC Address
// <i> Local Ethernet MAC Address
// <i> Value FF:FF:FF:FF:FF:FF is not allowed.
// <i> It is an ethernet Broadcast MAC address.
// <o>Address byte 1 <0x00-0xff:2>
// <i> LSB is an ethernet Multicast bit.
// <i> Must be 0 for local MAC address.
// <i> Default: 0x1E
#define ETH0_MAC1 0x1E
// <o>Address byte 2 <0x00-0xff>
// <i> Default: 0x30
#define ETH0_MAC2 0x30
// <o>Address byte 3 <0x00-0xff>
// <i> Default: 0x6C
#define ETH0_MAC3 0x6C
// <o>Address byte 4 <0x00-0xff>
// <i> Default: 0xA2
#define ETH0_MAC4 0xA2
// <o>Address byte 5 <0x00-0xff>
// <i> Default: 0x45
#define ETH0_MAC5 0x45
// <o>Address byte 6 <0x00-0xff>
// <i> Default: 0x5E
#define ETH0_MAC6 0x5E
// </h>
// <h>IP Address
// <i> Local Static IP Address
// <i> Value 255.255.255.255 is not allowed.
// <i> It is a Broadcast IP address.
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define ETH0_IP1 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define ETH0_IP2 168
// <o>Address byte 3 <0-255>
// <i> Default: 0
#define ETH0_IP3 11
// <o>Address byte 4 <0-255>
// <i> Default: 100
#define ETH0_IP4 101
// </h>
// <h>Subnet mask
// <i> Local Subnet mask
// <o>Mask byte 1 <0-255>
// <i> Default: 255
#define ETH0_MASK1 255
// <o>Mask byte 2 <0-255>
// <i> Default: 255
#define ETH0_MASK2 255
// <o>Mask byte 3 <0-255>
// <i> Default: 255
#define ETH0_MASK3 255
// <o>Mask byte 4 <0-255>
// <i> Default: 0
#define ETH0_MASK4 0
// </h>
// <h>Default Gateway
// <i> Default Gateway IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define ETH0_GW1 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define ETH0_GW2 168
// <o>Address byte 3 <0-255>
// <i> Default: 0
#define ETH0_GW3 11
// <o>Address byte 4 <0-255>
// <i> Default: 254
#define ETH0_GW4 1
// </h>
// <h>Primary DNS Server
// <i> Primary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define ETH0_PRI_DNS1 192
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define ETH0_PRI_DNS2 168
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define ETH0_PRI_DNS3 11
// <o>Address byte 4 <0-255>
// <i> Default: 129
#define ETH0_PRI_DNS4 1
// </h>
// <h>Secondary DNS Server
// <i> Secondary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define ETH0_SEC_DNS1 194
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define ETH0_SEC_DNS2 25
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define ETH0_SEC_DNS3 2
// <o>Address byte 4 <0-255>
// <i> Default: 130
#define ETH0_SEC_DNS4 130
// </h>
// <h>ARP Definitions
// <i> Address Resolution Protocol Definitions
// <o>Cache Table size <5-100>
// <i> Number of cached hardware/IP addresses
// <i> Default: 10
#define ETH0_ARP_TAB_SIZE 10
// <o>Cache Timeout in seconds <5-255>
// <i> A timeout for a cached hardware/IP addresses
// <i> Default: 150
#define ETH0_ARP_CACHE_TOUT 150
// <o>Number of Retries <0-20>
// <i> Number of Retries to resolve an IP address
// <i> before ARP module gives up
// <i> Default: 4
#define ETH0_ARP_MAX_RETRY 4
// <o>Resend Timeout in seconds <1-10>
// <i> A timeout to resend the ARP Request
// <i> Default: 2
#define ETH0_ARP_RESEND_TOUT 2
// <q>Send Notification on Address changes
// <i> When this option is enabled, the embedded host
// <i> will send a Gratuitous ARP notification at startup,
// <i> or when the device IP address has changed.
// <i> Default: Disabled
#define ETH0_ARP_NOTIFY 0
// </h>
// <e>IGMP Group Management
// <i> Enable or disable Internet Group Management Protocol
#define ETH0_IGMP_ENABLE 0
// <o>Membership Table size <2-50>
// <i> Number of Groups this host can join
// <i> Default: 5
#define ETH0_IGMP_TAB_SIZE 5
// </e>
// <q>NetBIOS Name Service
// <i> When this option is enabled, the embedded host can be
// <i> accessed by his name on the local LAN using NBNS protocol.
// <i> You need to modify also the number of UDP Sockets,
// <i> because NBNS protocol uses one UDP socket to run.
#define ETH0_NBNS_ENABLE 1
// <e>Dynamic Host Configuration
// <i> When this option is enabled, local IP address, Net Mask
// <i> and Default Gateway are obtained automatically from
// <i> the DHCP Server on local LAN.
// <i> You need to modify also the number of UDP Sockets,
// <i> because DHCP protocol uses one UDP socket to run.
#define ETH0_DHCP_ENABLE 0
// <s.40>Vendor Class Identifier
// <i> This value is optional. If specified, it is added
// <i> to DHCP request message, identifying vendor type.
// <i> Default: ""
#define ETH0_DHCP_VCID ""
// <q>Bootfile Name
// <i> This value is optional. If enabled, the Bootfile Name
// <i> (option 67) is also requested from DHCP server.
// <i> Default: disabled
#define ETH0_DHCP_BOOTFILE 0
// <q>NTP Servers
// <i> This value is optional. If enabled, a list of NTP Servers
// <i> (option 42) is also requested from DHCP server.
// <i> Default: disabled
#define ETH0_DHCP_NTP_SERVERS 0
// </e>
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Socket
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_TCP.h
* Purpose: Network Configuration TCP Sockets
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>TCP Sockets
#define TCP_ENABLE 1
// <o>Number of TCP Sockets <1-20>
// <i> Number of available TCP sockets
// <i> Default: 5
#define TCP_NUM_SOCKS 15
// <o>Number of Retries <0-20>
// <i> How many times TCP module will try to retransmit data
// <i> before giving up. Increase this value for high-latency
// <i> and low_throughput networks.
// <i> Default: 5
#define TCP_MAX_RETRY 5
// <o>Retry Timeout in seconds <1-10>
// <i> If data frame not acknowledged within this time frame,
// <i> TCP module will try to resend the data again.
// <i> Default: 4
#define TCP_RETRY_TOUT 4
// <o>Default Connect Timeout in seconds <1-600>
// <i> Default TCP Socket Keep Alive timeout. When it expires
// <i> with no TCP data frame send, TCP Connection is closed.
// <i> Default: 120
#define TCP_DEFAULT_TOUT 120
// <o>Maximum Segment Size <536-1460>
// <i> The Maximum Segment Size specifies the maximum
// <i> number of bytes in the TCP segment's Data field.
// <i> Default: 1460
#define TCP_MAX_SEG_SIZE 1460
// <o>Receive Window Size <536-65535>
// <i> Receive Window Size specifies the size of data,
// <i> that the socket is able to buffer in flow-control mode.
// <i> Default: 4380
#define TCP_RECEIVE_WIN_SIZE 4380
// </h>
// TCP Initial Retransmit period in seconds
#define TCP_INITIAL_RETRY_TOUT 1
// TCP SYN frame retransmit period in seconds
#define TCP_SYN_RETRY_TOUT 2
// Number of retries to establish a connection
#define TCP_CONNECT_RETRY 7

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Socket
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_UDP.h
* Purpose: Network Configuration UDP Sockets
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>UDP Sockets
#define UDP_ENABLE 1
// <o>Number of UDP Sockets <1-20>
// <i> Number of available UDP sockets
// <i> Default: 5
#define UDP_NUM_SOCKS 20
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Debug.c
* Purpose: Network Debug Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <q>Print Time Stamp
// <i> Enable printing the time-info in debug messages
#define DBG_TIME 1
// <h>TCPnet Debug Definitions
// <o>Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Dynamic Memory debug messages
#define DBG_MEM 1
// <o>Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Ethernet debug messages
#define DBG_ETH 0
// <o>PPP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off PPP debug messages
#define DBG_PPP 0
// <o>SLIP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off SLIP debug messages
#define DBG_SLIP 0
// <o>ARP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off ARP debug messages
#define DBG_ARP 0
// <o>IP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off IP debug messages
#define DBG_IP 1
// <o>ICMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off ICMP debug messages
#define DBG_ICMP 1
// <o>IGMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off IGMP debug messages
#define DBG_IGMP 1
// <o>UDP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off UDP debug messages
#define DBG_UDP 1
// <o>TCP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TCP debug messages
#define DBG_TCP 1
// <o>NBNS Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off NetBIOS Name Service debug messages
#define DBG_NBNS 1
// <o>DHCP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Dynamic Host Configuration debug messages
#define DBG_DHCP 1
// <o>DNS Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Domain Name Service debug messages
#define DBG_DNS 1
// <o>SNMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Simple Network Management debug messages
#define DBG_SNMP 1
// <o>SNTP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Simple Network Time debug messages
#define DBG_SNTP 1
// <o>BSD Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off BSD Interface debug messages
#define DBG_BSD 1
// </h>
// <h>Application Debug Definitions
// <o>HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Web Server debug messages
#define DBG_HTTP_SERVER 1
// <o>FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off FTP Server debug messages
#define DBG_FTP_SERVER 1
// <o>FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off FTP Client debug messages
#define DBG_FTP_CLIENT 1
// <o>Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Telnet Server debug messages
#define DBG_TELNET_SERVER 1
// <o>TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TFTP Server debug messages
#define DBG_TFTP_SERVER 1
// <o>TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TFTP Client debug messages
#define DBG_TFTP_CLIENT 1
// <o>SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off SMTP Client debug messages
#define DBG_SMTP_CLIENT 1
// </h>
#include "net_debug.h"
/**
\fn void net_debug_init (void)
\brief Initialize Network Debug Interface.
*/
void net_debug_init (void) {
/* Add your code to initialize the Debug output. This is usually the */
/* serial interface. The function is called at TCPnet system startup. */
/* You may need to customize also the 'putchar()' function. */
}

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/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'EchoServer'
* Target: 'EchoServer'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */
#define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */
#define RTE_Drivers_MCI0 /* Driver MCI0 */
#define RTE_Drivers_PHY_ST802RT1 /* Driver PHY ST802RT1 */
#define RTE_FileSystem_Core /* File System Core */
#define RTE_FileSystem_LFN /* File System with Long Filename support */
#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */
#define RTE_Network_Core /* Network Core */
#define RTE_Network_Debug /* Network Debug Version */
#define RTE_Network_DNS_Client /* Network DNS Client */
#define RTE_Network_Interface_ETH_0 /* Network Interface ETH 0 */
#define RTE_Network_Socket_BSD /* Network Socket BSD */
#define RTE_Network_Socket_TCP /* Network Socket TCP */
#define RTE_Network_Socket_UDP /* Network Socket UDP */
#endif /* RTE_COMPONENTS_H */

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/* config-FS.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// <<< Use Configuration Wizard in Context Menu >>>
// <h> wolfCrypt Configuration
// <h>Cert/Key Strage
// <o>Cert Storage <0=> SD Card <1=> Mem Buff (1024bytes) <2=> Mem Buff (2048bytes)
#define MDK_CONF_CERT_BUFF 0
#if MDK_CONF_CERT_BUFF== 1
#define USE_CERT_BUFFERS_1024
#elif MDK_CONF_CERT_BUFF == 2
#define USE_CERT_BUFFERS_2048
#endif
//</h>
// <h>Crypt Algrithm
// <h>MD5, SHA, SHA-256, AES, RC4, ASN, RSA
// </h>
// <e>MD2
#define MDK_CONF_MD2 0
#if MDK_CONF_MD2 == 1
#define CYASSL_MD2
#endif
// </e>
// <e>MD4
#define MDK_CONF_MD4 1
#if MDK_CONF_MD4 == 0
#define NO_MD4
#endif
// </e>
// <e>SHA-384
// <i>This has to be with SHA512
#define MDK_CONF_SHA384 0
#if MDK_CONF_SHA384 == 1
#define CYASSL_SHA384
#endif
// </e>
// <e>SHA-512
#define MDK_CONF_SHA512 0
#if MDK_CONF_SHA512 == 1
#define CYASSL_SHA512
#endif
// </e>
// <e>RIPEMD
#define MDK_CONF_RIPEMD 0
#if MDK_CONF_RIPEMD == 1
#define CYASSL_RIPEMD
#endif
// </e>
// <e>HMAC
#define MDK_CONF_HMAC 1
#if MDK_CONF_HMAC == 0
#define NO_HMAC
#endif
// </e>
// <e>HC128
#define MDK_CONF_HC128 0
#if MDK_CONF_HC128 == 1
#define HAVE_HC128
#endif
// </e>
// <e>RABBIT
#define MDK_CONF_RABBIT 1
#if MDK_CONF_RABBI == 0
#define NO_RABBIT
#endif
// </e>
// <e>AEAD
#define MDK_CONF_AEAD 0
#if MDK_CONF_AEAD == 1
#define HAVE_AEAD
#endif
// </e>
// <e>DES3
#define MDK_CONF_DES3 1
#if MDK_CONF_DES3 == 0
#define NO_DES3
#endif
// </e>
// <e>CAMELLIA
#define MDK_CONF_CAMELLIA 0
#if MDK_CONF_CAMELLIA == 1
#define HAVE_CAMELLIA
#endif
// </e>
// <e>DH
// <i>need this for CYASSL_SERVER, OPENSSL_EXTRA
#define MDK_CONF_DH 1
#if MDK_CONF_DH == 0
#define NO_DH
#endif
// </e>
// <e>DSA
#define MDK_CONF_DSA 1
#if MDK_CONF_DSA == 0
#define NO_DSA
#endif
// </e>
// <e>PWDBASED
#define MDK_CONF_PWDBASED 1
#if MDK_CONF_PWDBASED == 0
#define NO_PWDBASED
#endif
// </e>
// <e>ECC
#define MDK_CONF_ECC 0
#if MDK_CONF_ECC == 1
#define HAVE_ECC
#endif
// </e>
// <e>PSK
#define MDK_CONF_PSK 1
#if MDK_CONF_PSK == 0
#define NO_PSK
#endif
// </e>
// <e>AESCCM (Turn off Hardware Crypt)
#define MDK_CONF_AESCCM 0
#if MDK_CONF_AESCCM == 1
#define HAVE_AESCCM
#endif
// </e>
// <e>AESGCM (Turn off Hardware Crypt)
#define MDK_CONF_AESGCM 0
#if MDK_CONF_AESGCM == 1
#define HAVE_AESGCM
#define BUILD_AESGCM
#endif
// </e>
// <e>NTRU (need License, "crypto_ntru.h")
#define MDK_CONF_NTRU 0
#if MDK_CONF_NTRU == 1
#define HAVE_NTRU
#endif
// </e>
// </h>
// <h>Hardware Crypt (See document for usage)
// <e>Hardware RNG
#define MDK_CONF_STM32F2_RNG 0
#if MDK_CONF_STM32F2_RNG == 1
#define STM32F2_RNG
#else
#endif
// </e>
// <e>Hardware Crypt
#define MDK_CONF_STM32F2_CRYPTO 0
#if MDK_CONF_STM32F2_CRYPTO == 1
#define STM32F2_CRYPTO
#endif
// </e>
// </h>
//</h>
// <<< end of configuration section >>>

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/* config-RTX-TCP-FS.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/**** CyaSSL for KEIL-RL Configuration ****/
#define __CORTEX_M3__
#define CYASSL_MDK_ARM
#define NO_WRITEV
#define NO_CYASSL_DIR
#define NO_MAIN_DRIVER
#define CYASSL_DER_LOAD
#define HAVE_NULL_CIPHER
#define HAVE_KEIL_RTX
#define CYASSL_CMSIS_RTOS
#define CYASSL_KEIL_TCP_NET
// <<< Use Configuration Wizard in Context Menu >>>
// <h> CyaSSL Configuration
// <h>SSL (Included by default)
// </h>
// <e>TLS
#define MDK_CONF_TLS 1
#if MDK_CONF_TLS == 0
#define NO_TLS
#endif
// </e>
// <e>CRL
#define MDK_CONF_DER_LOAD 0
#if MDK_CONF_DER_LOAD == 1
#define CYASSL_DER_LOAD
#endif
// </e>
// <e>OpenSSL Extra
#define MDK_CONF_OPENSSL_EXTRA 1
#if MDK_CONF_OPENSSL_EXTRA == 1
#define OPENSSL_EXTRA
#endif
// </e>
//</h>
// <h>Cert/Key Generation
// <e>CertGen
#define MDK_CONF_CERT_GEN 0
#if MDK_CONF_CERT_GEN == 1
#define CYASSL_CERT_GEN
#endif
// </e>
// <e>KeyGen
#define MDK_CONF_KEY_GEN 0
#if MDK_CONF_KEY_GEN == 1
#define CYASSL_KEY_GEN
#endif
// </e>
//</h>
// <h>Others
// <e>Inline
#define MDK_CONF_INLINE 0
#if MDK_CONF_INLINE == 0
#define NO_INLINE
#endif
// </e>
// <h>Debug
// <e>Debug Message
#define MDK_CONF_DebugMessage 0
#if MDK_CONF_DebugMessage == 1
#define DEBUG_CYASSL
#endif
// </e>
// <e>Check malloc
#define MDK_CONF_CheckMalloc 1
#if MDK_CONF_CheckMalloc == 1
#define CYASSL_MALLOC_CHECK
#endif
// </e>
// </h>
// <e>ErrNo.h
#define MDK_CONF_ErrNo 0
#if MDK_CONF_ErrNo == 1
#define HAVE_ERRNO
#endif
// </e>
// <e>Error Strings
#define MDK_CONF_ErrorStrings 1
#if MDK_CONF_ErrorStrings == 0
#define NO_ERROR_STRINGS
#endif
// </e>
// <e>zlib (need "zlib.h")
#define MDK_CONF_LIBZ 0
#if MDK_CONF_LIBZ == 1
#define HAVE_LIBZ
#endif
// </e>
// <e>CAVIUM (need CAVIUM headers)
#define MDK_CONF_CAVIUM 0
#if MDK_CONF_CAVIUM == 1
#define HAVE_CAVIUM
#endif
// </e>
// <e>Small Stack
#define MDK_CONF_SmallStack 1
#if MDK_CONF_SmallStack == 0
#define NO_CYASSL_SMALL_STACK
#endif
// </e>
// <e>Use Fast Math
#define MDK_CONF_FASTMATH 0
#if MDK_CONF_FASTMATH == 1
#define USE_FAST_MATH
#endif
// </e>
// </h>
// <<< end of configuration section >>>

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/* settings.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* Place OS specific preprocessor flags, defines, includes here, will be
included into every file because types.h includes it */
#ifndef CTAO_CRYPT_SETTINGS_H
#define CTAO_CRYPT_SETTINGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Uncomment next line if using IPHONE */
/* #define IPHONE */
/* Uncomment next line if using ThreadX */
/* #define THREADX */
/* Uncomment next line if using Micrium ucOS */
/* #define MICRIUM */
/* Uncomment next line if using Mbed */
/* #define MBED */
/* Uncomment next line if using Microchip PIC32 ethernet starter kit */
/* #define MICROCHIP_PIC32 */
/* Uncomment next line if using Microchip TCP/IP stack, version 5 */
/* #define MICROCHIP_TCPIP_V5 */
/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */
/* #define MICROCHIP_TCPIP */
/* Uncomment next line if using FreeRTOS */
/* #define FREERTOS */
/* Uncomment next line if using FreeRTOS Windows Simulator */
/* #define FREERTOS_WINSIM */
/* Uncomment next line if using RTIP */
/* #define EBSNET */
/* Uncomment next line if using lwip */
/* #define CYASSL_LWIP */
/* Uncomment next line if building CyaSSL for a game console */
/* #define CYASSL_GAME_BUILD */
/* Uncomment next line if building CyaSSL for LSR */
/* #define CYASSL_LSR */
/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */
/* #define FREESCALE_MQX */
/* Uncomment next line if using STM32F2 */
/* #define CYASSL_STM32F2 */
/* Uncomment next line if using Comverge settings */
/* #define COMVERGE */
/* Uncomment next line if using QL SEP settings */
/* #define CYASSL_QL */
#include <cyassl/ctaocrypt/visibility.h>
#ifdef IPHONE
#define SIZEOF_LONG_LONG 8
#endif
#ifdef COMVERGE
#define THREADX
#define HAVE_NETX
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define NO_RSA
#define NO_SESSION_CACHE
#define HAVE_ECC
#endif
#ifdef THREADX
#define SIZEOF_LONG_LONG 8
#endif
#ifdef HAVE_NETX
#include "nx_api.h"
#endif
#ifdef MICROCHIP_PIC32
#define SIZEOF_LONG_LONG 8
#define SINGLE_THREADED
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#endif
#ifdef MICROCHIP_TCPIP_V5
/* include timer functions */
#include "TCPIP Stack/TCPIP.h"
#endif
#ifdef MICROCHIP_TCPIP
/* include timer, NTP functions */
#include "system/system_services.h"
#ifdef MICROCHIP_MPLAB_HARMONY
#include "tcpip/tcpip.h"
#else
#include "tcpip/sntp.h"
#endif
#endif
#ifdef MBED
#define SINGLE_THREADED
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#endif /* MBED */
#ifdef CYASSL_TYTO
#include "rand.h"
#define FREERTOS
#define NO_FILESYSTEM
#define CYASSL_USER_IO
#define NO_DEV_RANDOM
#define HAVE_ECC
#define HAVE_ECC_ENCRYPT
#define ECC_SHAMIR
#define HAVE_HKDF
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#define FP_MAX_BITS 512
#define NO_OLD_TLS
#define NO_MD4
#define NO_RABBIT
#define NO_HC128
#define NO_RSA
#define NO_DSA
#define NO_PWDBASED
#define NO_PSK
#endif
#ifdef FREERTOS_WINSIM
#define FREERTOS
#define USE_WINDOWS_API
#endif
/* Micrium will use Visual Studio for compilation but not the Win32 API */
#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \
&& !defined(EBSNET)
#define USE_WINDOWS_API
#endif
#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER)
#include <stdlib.h>
#define XMALLOC(s, h, type) malloc((s))
#define XFREE(p, h, type) free((p))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif
#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL)
#undef XMALLOC
#define XMALLOC yaXMALLOC
#undef XFREE
#define XFREE yaXFREE
#undef XREALLOC
#define XREALLOC yaXREALLOC
#endif
#ifdef FREERTOS
#ifndef NO_WRITEV
#define NO_WRITEV
#endif
#ifndef NO_SHA512
#define NO_SHA512
#endif
#ifndef NO_DH
#define NO_DH
#endif
#ifndef NO_DSA
#define NO_DSA
#endif
#ifndef NO_HC128
#define NO_HC128
#endif
#ifndef SINGLE_THREADED
#include "FreeRTOS.h"
#include "semphr.h"
#endif
#endif
#ifdef EBSNET
#include "rtip.h"
/* #define DEBUG_CYASSL */
#define NO_CYASSL_DIR /* tbd */
#if (POLLOS)
#define SINGLE_THREADED
#endif
#if (RTPLATFORM)
#if (!RTP_LITTLE_ENDIAN)
#define BIG_ENDIAN_ORDER
#endif
#else
#if (!KS_LITTLE_ENDIAN)
#define BIG_ENDIAN_ORDER
#endif
#endif
#if (WINMSP3)
#undef SIZEOF_LONG
#define SIZEOF_LONG_LONG 8
#else
#sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG
#endif
#define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC))
#define XFREE(p, h, type) (rtp_free(p))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif /* EBSNET */
#ifdef CYASSL_GAME_BUILD
#define SIZEOF_LONG_LONG 8
#if defined(__PPU) || defined(__XENON)
#define BIG_ENDIAN_ORDER
#endif
#endif
#ifdef CYASSL_LSR
#define HAVE_WEBSERVER
#define SIZEOF_LONG_LONG 8
#define CYASSL_LOW_MEMORY
#define NO_WRITEV
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define NO_DEV_RANDOM
#define NO_CYASSL_DIR
#define NO_RABBIT
#ifndef NO_FILESYSTEM
#define LSR_FS
#include "inc/hw_types.h"
#include "fs.h"
#endif
#define CYASSL_LWIP
#include <errno.h> /* for tcp errno */
#define CYASSL_SAFERTOS
#if defined(__IAR_SYSTEMS_ICC__)
/* enum uses enum */
#pragma diag_suppress=Pa089
#endif
#endif
#ifdef CYASSL_SAFERTOS
#ifndef SINGLE_THREADED
#include "SafeRTOS/semphr.h"
#endif
#include "SafeRTOS/heap.h"
#define XMALLOC(s, h, type) pvPortMalloc((s))
#define XFREE(p, h, type) vPortFree((p))
#define XREALLOC(p, n, h, t) pvPortRealloc((p), (n))
#endif
#ifdef CYASSL_LOW_MEMORY
#undef RSA_LOW_MEM
#define RSA_LOW_MEM
#undef CYASSL_SMALL_STACK
#define CYASSL_SMALL_STACK
#undef TFM_TIMING_RESISTANT
#define TFM_TIMING_RESISTANT
#endif
#ifdef FREESCALE_MQX
#define SIZEOF_LONG_LONG 8
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_RABBIT
#define NO_CYASSL_DIR
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#define FREESCALE_K70_RNGA
/* #define FREESCALE_K53_RNGB */
#include "mqx.h"
#ifndef NO_FILESYSTEM
#include "mfs.h"
#include "fio.h"
#endif
#ifndef SINGLE_THREADED
#include "mutex.h"
#endif
#define XMALLOC(s, h, t) (void *)_mem_alloc_system((s))
#define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));}
/* Note: MQX has no realloc, using fastmath above */
#endif
#ifdef CYASSL_STM32F2
#define SIZEOF_LONG_LONG 8
#define NO_DEV_RANDOM
#define NO_CYASSL_DIR
#define NO_RABBIT
#define STM32F2_RNG
#define STM32F2_CRYPTO
#define KEIL_INTRINSICS
#endif
#ifdef MICRIUM
#include "stdlib.h"
#include "net_cfg.h"
#include "ssl_cfg.h"
#include "net_secure_os.h"
#define CYASSL_TYPES
typedef CPU_INT08U byte;
typedef CPU_INT16U word16;
typedef CPU_INT32U word32;
#if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32)
#define SIZEOF_LONG 4
#undef SIZEOF_LONG_LONG
#else
#undef SIZEOF_LONG
#define SIZEOF_LONG_LONG 8
#endif
#define STRING_USER
#define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr)))
#define XSTRNCPY(pstr_dest, pstr_src, len_max) \
((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \
(CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max)))
#define XSTRNCMP(pstr_1, pstr_2, len_max) \
((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \
(CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max)))
#define XSTRSTR(pstr, pstr_srch) \
((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \
(CPU_CHAR *)(pstr_srch)))
#define XMEMSET(pmem, data_val, size) \
((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \
(CPU_SIZE_T)(size)))
#define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \
(void *)(psrc), (CPU_SIZE_T)(size)))
#define XMEMCMP(pmem_1, pmem_2, size) \
(((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \
(CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES)
#define XMEMMOVE XMEMCPY
#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
#define MICRIUM_MALLOC
#define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \
(CPU_SIZE_T)(s), (void *)0))
#define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \
(p), (void *)0))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif
#if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED)
#undef NO_FILESYSTEM
#else
#define NO_FILESYSTEM
#endif
#if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG)
#define DEBUG_CYASSL
#else
#undef DEBUG_CYASSL
#endif
#if (SSL_CFG_OPENSSL_EN == DEF_ENABLED)
#define OPENSSL_EXTRA
#else
#undef OPENSSL_EXTRA
#endif
#if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED)
#undef SINGLE_THREADED
#else
#define SINGLE_THREADED
#endif
#if (SSL_CFG_DH_EN == DEF_ENABLED)
#undef NO_DH
#else
#define NO_DH
#endif
#if (SSL_CFG_DSA_EN == DEF_ENABLED)
#undef NO_DSA
#else
#define NO_DSA
#endif
#if (SSL_CFG_PSK_EN == DEF_ENABLED)
#undef NO_PSK
#else
#define NO_PSK
#endif
#if (SSL_CFG_3DES_EN == DEF_ENABLED)
#undef NO_DES
#else
#define NO_DES
#endif
#if (SSL_CFG_AES_EN == DEF_ENABLED)
#undef NO_AES
#else
#define NO_AES
#endif
#if (SSL_CFG_RC4_EN == DEF_ENABLED)
#undef NO_RC4
#else
#define NO_RC4
#endif
#if (SSL_CFG_RABBIT_EN == DEF_ENABLED)
#undef NO_RABBIT
#else
#define NO_RABBIT
#endif
#if (SSL_CFG_HC128_EN == DEF_ENABLED)
#undef NO_HC128
#else
#define NO_HC128
#endif
#if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
#define BIG_ENDIAN_ORDER
#else
#undef BIG_ENDIAN_ORDER
#define LITTLE_ENDIAN_ORDER
#endif
#if (SSL_CFG_MD4_EN == DEF_ENABLED)
#undef NO_MD4
#else
#define NO_MD4
#endif
#if (SSL_CFG_WRITEV_EN == DEF_ENABLED)
#undef NO_WRITEV
#else
#define NO_WRITEV
#endif
#if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED)
#define NO_DEV_RANDOM
#else
#undef NO_DEV_RANDOM
#endif
#if (SSL_CFG_USER_IO_EN == DEF_ENABLED)
#define CYASSL_USER_IO
#else
#undef CYASSL_USER_IO
#endif
#if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED)
#undef LARGE_STATIC_BUFFERS
#undef STATIC_CHUNKS_ONLY
#else
#define LARGE_STATIC_BUFFERS
#define STATIC_CHUNKS_ONLY
#endif
#if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED)
#define CYASSL_DER_LOAD
#else
#undef CYASSL_DER_LOAD
#endif
#if (SSL_CFG_DTLS_EN == DEF_ENABLED)
#define CYASSL_DTLS
#else
#undef CYASSL_DTLS
#endif
#if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED)
#define CYASSL_CALLBACKS
#else
#undef CYASSL_CALLBACKS
#endif
#if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED)
#define USE_FAST_MATH
#else
#undef USE_FAST_MATH
#endif
#if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED)
#define TFM_TIMING_RESISTANT
#else
#undef TFM_TIMING_RESISTANT
#endif
#endif /* MICRIUM */
#ifdef CYASSL_QL
#ifndef CYASSL_SEP
#define CYASSL_SEP
#endif
#ifndef OPENSSL_EXTRA
#define OPENSSL_EXTRA
#endif
#ifndef SESSION_CERTS
#define SESSION_CERTS
#endif
#ifndef HAVE_AESCCM
#define HAVE_AESCCM
#endif
#ifndef ATOMIC_USER
#define ATOMIC_USER
#endif
#ifndef CYASSL_DER_LOAD
#define CYASSL_DER_LOAD
#endif
#ifndef KEEP_PEER_CERT
#define KEEP_PEER_CERT
#endif
#ifndef HAVE_ECC
#define HAVE_ECC
#endif
#ifndef SESSION_INDEX
#define SESSION_INDEX
#endif
#endif /* CYASSL_QL */
#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \
!defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY)
#define USE_CYASSL_MEMORY
#endif
#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS)
#undef KEEP_PEER_CERT
#define KEEP_PEER_CERT
#endif
/* stream ciphers except arc4 need 32bit alignment, intel ok without */
#ifndef XSTREAM_ALIGNMENT
#if defined(__x86_64__) || defined(__ia64__) || defined(__i386__)
#define NO_XSTREAM_ALIGNMENT
#else
#define XSTREAM_ALIGNMENT
#endif
#endif
/* if using hardware crypto and have alignment requirements, specify the
requirement here. The record header of SSL/TLS will prvent easy alignment.
This hint tries to help as much as possible. */
#ifndef CYASSL_GENERAL_ALIGNMENT
#ifdef CYASSL_AESNI
#define CYASSL_GENERAL_ALIGNMENT 16
#elif defined(XSTREAM_ALIGNMENT)
#define CYASSL_GENERAL_ALIGNMENT 4
#else
#define CYASSL_GENERAL_ALIGNMENT 0
#endif
#endif
#ifdef HAVE_CRL
/* not widely supported yet */
#undef NO_SKID
#define NO_SKID
#endif
/* Place any other flags or defines here */
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* CTAO_CRYPT_SETTINGS_H */

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IDE/MDK5-ARM/Projects/EchoServer/STM32_SWO.ini
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@ -1,36 +0,0 @@
/******************************************************************************/
/* STM32_SWO.ini: STM32 Debugger Initialization File */
/******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>> //
/******************************************************************************/
/* This file is part of the uVision/ARM development tools. */
/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */
/* This software may only be used under the terms of a valid, current, */
/* end user licence from KEIL for a compatible version of KEIL software */
/* development tools. Nothing else gives you the right to use this software. */
/******************************************************************************/
FUNC void DebugSetup (void) {
// <h> Debug MCU Configuration
// <o1.0> DBG_SLEEP <i> Debug Sleep Mode
// <o1.1> DBG_STOP <i> Debug Stop Mode
// <o1.2> DBG_STANDBY <i> Debug Standby Mode
// <o1.5> TRACE_IOEN <i> Trace I/O Enable
// <o1.6..7> TRACE_MODE <i> Trace Mode
// <0=> Asynchronous
// <1=> Synchronous: TRACEDATA Size 1
// <2=> Synchronous: TRACEDATA Size 2
// <3=> Synchronous: TRACEDATA Size 4
// <o1.8> DBG_IWDG_STOP <i> Independant Watchdog Stopped when Core is halted
// <o1.9> DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
// <o1.10> DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
// <o1.11> DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
// <o1.12> DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
// <o1.13> DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
// <o1.14> DBG_CAN_STOP <i> CAN Stopped when Core is halted
// </h>
_WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR
}
DebugSetup(); // Debugger Setup

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IDE/MDK5-ARM/Projects/SimpleClient/RTE/CMSIS/RTX_Conf_CM.c
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/*----------------------------------------------------------------------------
* RL-ARM - RTX
*----------------------------------------------------------------------------
* Name: RTX_Conf_CM.C
* Purpose: Configuration of CMSIS RTX Kernel for Cortex-M
* Rev.: V4.73
*----------------------------------------------------------------------------
*
* Copyright (c) 1999-2009 KEIL, 2009-2013 ARM Germany GmbH
* All rights reserved.
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* - Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without
* specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*---------------------------------------------------------------------------*/
#include "cmsis_os.h"
/*----------------------------------------------------------------------------
* RTX User configuration part BEGIN
*---------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
//
// <h>Thread Configuration
// =======================
//
// <o>Number of concurrent running threads <0-250>
// <i> Defines max. number of threads that will run at the same time.
// <i> Default: 6
#ifndef OS_TASKCNT
#define OS_TASKCNT 6
#endif
// <o>Default Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines default stack size for threads with osThreadDef stacksz = 0
// <i> Default: 200
#ifndef OS_STKSIZE
#define OS_STKSIZE 300
#endif
// <o>Main Thread stack size [bytes] <64-32768:8><#/4>
// <i> Defines stack size for main thread.
// <i> Default: 200
#ifndef OS_MAINSTKSIZE
#define OS_MAINSTKSIZE 2000
#endif
// <o>Number of threads with user-provided stack size <0-250>
// <i> Defines the number of threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVCNT
#define OS_PRIVCNT 0
#endif
// <o>Total stack size [bytes] for threads with user-provided stack size <0-1048576:8><#/4>
// <i> Defines the combined stack size for threads with user-provided stack size.
// <i> Default: 0
#ifndef OS_PRIVSTKSIZE
#define OS_PRIVSTKSIZE 2500
#endif
// <q>Check for stack overflow
// <i> Includes the stack checking code for stack overflow.
// <i> Note that additional code reduces the Kernel performance.
#ifndef OS_STKCHECK
#define OS_STKCHECK 1
#endif
// <o>Processor mode for thread execution
// <0=> Unprivileged mode
// <1=> Privileged mode
// <i> Default: Privileged mode
#ifndef OS_RUNPRIV
#define OS_RUNPRIV 1
#endif
// </h>
// <h>RTX Kernel Timer Tick Configuration
// ======================================
// <q> Use Cortex-M SysTick timer as RTX Kernel Timer
// <i> Use the Cortex-M SysTick timer as a time-base for RTX.
#ifndef OS_SYSTICK
#define OS_SYSTICK 1
#endif
//
// <o>Timer clock value [Hz] <1-1000000000>
// <i> Defines the timer clock value.
// <i> Default: 12000000 (12MHz)
#ifndef OS_CLOCK
#define OS_CLOCK 12000000
#endif
// <o>Timer tick value [us] <1-1000000>
// <i> Defines the timer tick value.
// <i> Default: 1000 (1ms)
#ifndef OS_TICK
#define OS_TICK 1000
#endif
// </h>
// <h>System Configuration
// =======================
//
// <e>Round-Robin Thread switching
// ===============================
//
// <i> Enables Round-Robin Thread switching.
#ifndef OS_ROBIN
#define OS_ROBIN 1
#endif
// <o>Round-Robin Timeout [ticks] <1-1000>
// <i> Defines how long a thread will execute before a thread switch.
// <i> Default: 5
#ifndef OS_ROBINTOUT
#define OS_ROBINTOUT 5
#endif
// </e>
// <e>User Timers
// ==============
// <i> Enables user Timers
#ifndef OS_TIMERS
#define OS_TIMERS 1
#endif
// <o>Timer Thread Priority
// <1=> Low
// <2=> Below Normal <3=> Normal <4=> Above Normal
// <5=> High
// <6=> Realtime (highest)
// <i> Defines priority for Timer Thread
// <i> Default: High
#ifndef OS_TIMERPRIO
#define OS_TIMERPRIO 5
#endif
// <o>Timer Thread stack size [bytes] <64-4096:8><#/4>
// <i> Defines stack size for Timer thread.
// <i> Default: 200
#ifndef OS_TIMERSTKSZ
#define OS_TIMERSTKSZ 50
#endif
// <o>Timer Callback Queue size <1-32>
// <i> Number of concurrent active timer callback functions.
// <i> Default: 4
#ifndef OS_TIMERCBQS
#define OS_TIMERCBQS 4
#endif
// </e>
// <o>ISR FIFO Queue size<4=> 4 entries <8=> 8 entries
// <12=> 12 entries <16=> 16 entries
// <24=> 24 entries <32=> 32 entries
// <48=> 48 entries <64=> 64 entries
// <96=> 96 entries
// <i> ISR functions store requests to this buffer,
// <i> when they are called from the interrupt handler.
// <i> Default: 16 entries
#ifndef OS_FIFOSZ
#define OS_FIFOSZ 16
#endif
// </h>
//------------- <<< end of configuration section >>> -----------------------
// Standard library system mutexes
// ===============================
// Define max. number system mutexes that are used to protect
// the arm standard runtime library. For microlib they are not used.
#ifndef OS_MUTEXCNT
#define OS_MUTEXCNT 8
#endif
/*----------------------------------------------------------------------------
* RTX User configuration part END
*---------------------------------------------------------------------------*/
#define OS_TRV ((uint32_t)(((double)OS_CLOCK*(double)OS_TICK)/1E6)-1)
/*----------------------------------------------------------------------------
* Global Functions
*---------------------------------------------------------------------------*/
/*--------------------------- os_idle_demon ---------------------------------*/
void os_idle_demon (void) {
/* The idle demon is a system thread, running when no other thread is */
/* ready to run. */
for (;;) {
/* HERE: include optional user code to be executed when no thread runs.*/
}
}
#if (OS_SYSTICK == 0) // Functions for alternative timer as RTX kernel timer
/*--------------------------- os_tick_init ----------------------------------*/
// Initialize alternative hardware timer as RTX kernel timer
// Return: IRQ number of the alternative hardware timer
int os_tick_init (void) {
return (-1); /* Return IRQ number of timer (0..239) */
}
/*--------------------------- os_tick_val -----------------------------------*/
// Get alternative hardware timer current value (0 .. OS_TRV)
uint32_t os_tick_val (void) {
return (0);
}
/*--------------------------- os_tick_ovf -----------------------------------*/
// Get alternative hardware timer overflow flag
// Return: 1 - overflow, 0 - no overflow
uint32_t os_tick_ovf (void) {
return (0);
}
/*--------------------------- os_tick_irqack --------------------------------*/
// Acknowledge alternative hardware timer interrupt
void os_tick_irqack (void) {
/* ... */
}
#endif // (OS_SYSTICK == 0)
/*--------------------------- os_error --------------------------------------*/
/* OS Error Codes */
#define OS_ERROR_STACK_OVF 1
#define OS_ERROR_FIFO_OVF 2
#define OS_ERROR_MBX_OVF 3
extern osThreadId svcThreadGetId (void);
void os_error (uint32_t error_code) {
/* This function is called when a runtime error is detected. */
/* Parameter 'error_code' holds the runtime error code. */
/* HERE: include optional code to be executed on runtime error. */
switch (error_code) {
case OS_ERROR_STACK_OVF:
/* Stack overflow detected for the currently running task. */
/* Thread can be identified by calling svcThreadGetId(). */
break;
case OS_ERROR_FIFO_OVF:
/* ISR FIFO Queue buffer overflow detected. */
break;
case OS_ERROR_MBX_OVF:
/* Mailbox overflow detected. */
break;
}
for (;;);
}
/*----------------------------------------------------------------------------
* RTX Configuration Functions
*---------------------------------------------------------------------------*/
#include "RTX_CM_lib.h"
/*----------------------------------------------------------------------------
* end of file
*---------------------------------------------------------------------------*/

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IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/RTE_Device.h
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IDE/MDK5-ARM/Projects/SimpleClient/RTE/Device/STM32F207IG/startup_stm32f2xx.s
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;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
;* File Name : startup_stm32f2xx.s
;* Author : MCD Application Team
;* Version : V1.0.0
;* Date : 18-April-2011
;* Description : STM32F2xx devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM3 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00007000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window WatchDog
DCD PVD_IRQHandler ; PVD through EXTI Line detection
DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_IRQHandler ; EXTI Line0
DCD EXTI1_IRQHandler ; EXTI Line1
DCD EXTI2_IRQHandler ; EXTI Line2
DCD EXTI3_IRQHandler ; EXTI Line3
DCD EXTI4_IRQHandler ; EXTI Line4
DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s
DCD CAN1_TX_IRQHandler ; CAN1 TX
DCD CAN1_RX0_IRQHandler ; CAN1 RX0
DCD CAN1_RX1_IRQHandler ; CAN1 RX1
DCD CAN1_SCE_IRQHandler ; CAN1 SCE
DCD EXTI9_5_IRQHandler ; External Line[9:5]s
DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD TIM4_IRQHandler ; TIM4
DCD I2C1_EV_IRQHandler ; I2C1 Event
DCD I2C1_ER_IRQHandler ; I2C1 Error
DCD I2C2_EV_IRQHandler ; I2C2 Event
DCD I2C2_ER_IRQHandler ; I2C2 Error
DCD SPI1_IRQHandler ; SPI1
DCD SPI2_IRQHandler ; SPI2
DCD USART1_IRQHandler ; USART1
DCD USART2_IRQHandler ; USART2
DCD USART3_IRQHandler ; USART3
DCD EXTI15_10_IRQHandler ; External Line[15:10]s
DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12
DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13
DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14
DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare
DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
DCD FSMC_IRQHandler ; FSMC
DCD SDIO_IRQHandler ; SDIO
DCD TIM5_IRQHandler ; TIM5
DCD SPI3_IRQHandler ; SPI3
DCD UART4_IRQHandler ; UART4
DCD UART5_IRQHandler ; UART5
DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
DCD TIM7_IRQHandler ; TIM7
DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
DCD ETH_IRQHandler ; Ethernet
DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line
DCD CAN2_TX_IRQHandler ; CAN2 TX
DCD CAN2_RX0_IRQHandler ; CAN2 RX0
DCD CAN2_RX1_IRQHandler ; CAN2 RX1
DCD CAN2_SCE_IRQHandler ; CAN2 SCE
DCD OTG_FS_IRQHandler ; USB OTG FS
DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
DCD USART6_IRQHandler ; USART6
DCD I2C3_EV_IRQHandler ; I2C3 event
DCD I2C3_ER_IRQHandler ; I2C3 error
DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out
DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In
DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI
DCD OTG_HS_IRQHandler ; USB OTG HS
DCD DCMI_IRQHandler ; DCMI
DCD CRYP_IRQHandler ; CRYP crypto
DCD HASH_RNG_IRQHandler ; Hash and Rng
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT TAMP_STAMP_IRQHandler [WEAK]
EXPORT RTC_WKUP_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_IRQHandler [WEAK]
EXPORT EXTI1_IRQHandler [WEAK]
EXPORT EXTI2_IRQHandler [WEAK]
EXPORT EXTI3_IRQHandler [WEAK]
EXPORT EXTI4_IRQHandler [WEAK]
EXPORT DMA1_Stream0_IRQHandler [WEAK]
EXPORT DMA1_Stream1_IRQHandler [WEAK]
EXPORT DMA1_Stream2_IRQHandler [WEAK]
EXPORT DMA1_Stream3_IRQHandler [WEAK]
EXPORT DMA1_Stream4_IRQHandler [WEAK]
EXPORT DMA1_Stream5_IRQHandler [WEAK]
EXPORT DMA1_Stream6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT CAN1_TX_IRQHandler [WEAK]
EXPORT CAN1_RX0_IRQHandler [WEAK]
EXPORT CAN1_RX1_IRQHandler [WEAK]
EXPORT CAN1_SCE_IRQHandler [WEAK]
EXPORT EXTI9_5_IRQHandler [WEAK]
EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK]
EXPORT TIM1_UP_TIM10_IRQHandler [WEAK]
EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM4_IRQHandler [WEAK]
EXPORT I2C1_EV_IRQHandler [WEAK]
EXPORT I2C1_ER_IRQHandler [WEAK]
EXPORT I2C2_EV_IRQHandler [WEAK]
EXPORT I2C2_ER_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
EXPORT USART2_IRQHandler [WEAK]
EXPORT USART3_IRQHandler [WEAK]
EXPORT EXTI15_10_IRQHandler [WEAK]
EXPORT RTC_Alarm_IRQHandler [WEAK]
EXPORT OTG_FS_WKUP_IRQHandler [WEAK]
EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK]
EXPORT TIM8_UP_TIM13_IRQHandler [WEAK]
EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK]
EXPORT TIM8_CC_IRQHandler [WEAK]
EXPORT DMA1_Stream7_IRQHandler [WEAK]
EXPORT FSMC_IRQHandler [WEAK]
EXPORT SDIO_IRQHandler [WEAK]
EXPORT TIM5_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT TIM6_DAC_IRQHandler [WEAK]
EXPORT TIM7_IRQHandler [WEAK]
EXPORT DMA2_Stream0_IRQHandler [WEAK]
EXPORT DMA2_Stream1_IRQHandler [WEAK]
EXPORT DMA2_Stream2_IRQHandler [WEAK]
EXPORT DMA2_Stream3_IRQHandler [WEAK]
EXPORT DMA2_Stream4_IRQHandler [WEAK]
EXPORT ETH_IRQHandler [WEAK]
EXPORT ETH_WKUP_IRQHandler [WEAK]
EXPORT CAN2_TX_IRQHandler [WEAK]
EXPORT CAN2_RX0_IRQHandler [WEAK]
EXPORT CAN2_RX1_IRQHandler [WEAK]
EXPORT CAN2_SCE_IRQHandler [WEAK]
EXPORT OTG_FS_IRQHandler [WEAK]
EXPORT DMA2_Stream5_IRQHandler [WEAK]
EXPORT DMA2_Stream6_IRQHandler [WEAK]
EXPORT DMA2_Stream7_IRQHandler [WEAK]
EXPORT USART6_IRQHandler [WEAK]
EXPORT I2C3_EV_IRQHandler [WEAK]
EXPORT I2C3_ER_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK]
EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK]
EXPORT OTG_HS_WKUP_IRQHandler [WEAK]
EXPORT OTG_HS_IRQHandler [WEAK]
EXPORT DCMI_IRQHandler [WEAK]
EXPORT CRYP_IRQHandler [WEAK]
EXPORT HASH_RNG_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
TAMP_STAMP_IRQHandler
RTC_WKUP_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_IRQHandler
EXTI1_IRQHandler
EXTI2_IRQHandler
EXTI3_IRQHandler
EXTI4_IRQHandler
DMA1_Stream0_IRQHandler
DMA1_Stream1_IRQHandler
DMA1_Stream2_IRQHandler
DMA1_Stream3_IRQHandler
DMA1_Stream4_IRQHandler
DMA1_Stream5_IRQHandler
DMA1_Stream6_IRQHandler
ADC_IRQHandler
CAN1_TX_IRQHandler
CAN1_RX0_IRQHandler
CAN1_RX1_IRQHandler
CAN1_SCE_IRQHandler
EXTI9_5_IRQHandler
TIM1_BRK_TIM9_IRQHandler
TIM1_UP_TIM10_IRQHandler
TIM1_TRG_COM_TIM11_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM4_IRQHandler
I2C1_EV_IRQHandler
I2C1_ER_IRQHandler
I2C2_EV_IRQHandler
I2C2_ER_IRQHandler
SPI1_IRQHandler
SPI2_IRQHandler
USART1_IRQHandler
USART2_IRQHandler
USART3_IRQHandler
EXTI15_10_IRQHandler
RTC_Alarm_IRQHandler
OTG_FS_WKUP_IRQHandler
TIM8_BRK_TIM12_IRQHandler
TIM8_UP_TIM13_IRQHandler
TIM8_TRG_COM_TIM14_IRQHandler
TIM8_CC_IRQHandler
DMA1_Stream7_IRQHandler
FSMC_IRQHandler
SDIO_IRQHandler
TIM5_IRQHandler
SPI3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
TIM6_DAC_IRQHandler
TIM7_IRQHandler
DMA2_Stream0_IRQHandler
DMA2_Stream1_IRQHandler
DMA2_Stream2_IRQHandler
DMA2_Stream3_IRQHandler
DMA2_Stream4_IRQHandler
ETH_IRQHandler
ETH_WKUP_IRQHandler
CAN2_TX_IRQHandler
CAN2_RX0_IRQHandler
CAN2_RX1_IRQHandler
CAN2_SCE_IRQHandler
OTG_FS_IRQHandler
DMA2_Stream5_IRQHandler
DMA2_Stream6_IRQHandler
DMA2_Stream7_IRQHandler
USART6_IRQHandler
I2C3_EV_IRQHandler
I2C3_ER_IRQHandler
OTG_HS_EP1_OUT_IRQHandler
OTG_HS_EP1_IN_IRQHandler
OTG_HS_WKUP_IRQHandler
OTG_HS_IRQHandler
DCMI_IRQHandler
CRYP_IRQHandler
HASH_RNG_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END
;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****

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@ -1,536 +0,0 @@
/**
******************************************************************************
* @file system_stm32f2xx.c
* @author MCD Application Team
* @version V1.0.0
* @date 18-April-2011
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
* This file contains the system clock configuration for STM32F2xx devices,
* and is generated by the clock configuration tool
* "STM32f2xx_Clock_Configuration_V1.0.0.xls"
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
* and Divider factors, AHB/APBx prescalers and Flash settings),
* depending on the configuration made in the clock xls tool.
* This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f2xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (16 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f2xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. If the system clock source selected by user fails to startup, the SystemInit()
* function will do nothing and HSI still used as system clock source. User can
* add some code to deal with this issue inside the SetSysClock() function.
*
* 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
* in "stm32f2xx.h" file. When HSE is used as system clock source, directly or
* through PLL, and you are using different crystal you have to adapt the HSE
* value to your own configuration.
*
* 5. This file configures the system clock as follows:
*=============================================================================
*=============================================================================
* Supported STM32F2xx device revision | Rev B and Y
*-----------------------------------------------------------------------------
* System Clock source | PLL (HSE)
*-----------------------------------------------------------------------------
* SYSCLK(Hz) | 120000000
*-----------------------------------------------------------------------------
* HCLK(Hz) | 120000000
*-----------------------------------------------------------------------------
* AHB Prescaler | 1
*-----------------------------------------------------------------------------
* APB1 Prescaler | 4
*-----------------------------------------------------------------------------
* APB2 Prescaler | 2
*-----------------------------------------------------------------------------
* HSE Frequency(Hz) | 25000000
*-----------------------------------------------------------------------------
* PLL_M | 25
*-----------------------------------------------------------------------------
* PLL_N | 240
*-----------------------------------------------------------------------------
* PLL_P | 2
*-----------------------------------------------------------------------------
* PLL_Q | 5
*-----------------------------------------------------------------------------
* PLLI2S_N | NA
*-----------------------------------------------------------------------------
* PLLI2S_R | NA
*-----------------------------------------------------------------------------
* I2S input clock | NA
*-----------------------------------------------------------------------------
* VDD(V) | 3.3
*-----------------------------------------------------------------------------
* Flash Latency(WS) | 3
*-----------------------------------------------------------------------------
* Prefetch Buffer | ON
*-----------------------------------------------------------------------------
* Instruction cache | ON
*-----------------------------------------------------------------------------
* Data cache | ON
*-----------------------------------------------------------------------------
* Require 48MHz for USB OTG FS, | Enabled
* SDIO and RNG clock |
*-----------------------------------------------------------------------------
*=============================================================================
******************************************************************************
* @attention
*
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*
* <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2>
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f2xx_system
* @{
*/
/** @addtogroup STM32F2xx_System_Private_Includes
* @{
*/
#include "stm32f2xx.h"
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Defines
* @{
*/
/*!< Uncomment the following line if you need to use external SRAM mounted
on STM322xG_EVAL board as data memory */
/* #define DATA_IN_ExtSRAM */
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
#define PLL_M 25
#define PLL_N 240
/* SYSCLK = PLL_VCO / PLL_P */
#define PLL_P 2
/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */
#define PLL_Q 5
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Variables
* @{
*/
uint32_t SystemCoreClock = 120000000;
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes
* @{
*/
static void SetSysClock(void);
#ifdef DATA_IN_ExtSRAM
static void SystemInit_ExtMemCtl(void);
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/** @addtogroup STM32F2xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system
* Initialize the Embedded Flash Interface, the PLL and update the
* SystemFrequency variable.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
/* Reset CFGR register */
RCC->CFGR = 0x00000000;
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset PLLCFGR register */
RCC->PLLCFGR = 0x24003010;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
#ifdef DATA_IN_ExtSRAM
SystemInit_ExtMemCtl();
#endif /* DATA_IN_ExtSRAM */
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings ----------------------------------*/
SetSysClock();
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
#endif
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate(void)
{
uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case 0x00: /* HSI used as system clock source */
SystemCoreClock = HSI_VALUE;
break;
case 0x04: /* HSE used as system clock source */
SystemCoreClock = HSE_VALUE;
break;
case 0x08: /* PLL used as system clock source */
/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
SYSCLK = PLL_VCO / PLL_P
*/
pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
if (pllsource != 0)
{
/* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
else
{
/* HSI used as PLL clock source */
pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
}
pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
SystemCoreClock = pllvco/pllp;
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK frequency --------------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @Note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
static void SetSysClock(void)
{
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
/* Enable HSE */
RCC->CR |= ((uint32_t)RCC_CR_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CR & RCC_CR_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CR & RCC_CR_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK / 1*/
RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
/* PCLK2 = HCLK / 2*/
RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
/* PCLK1 = HCLK / 4*/
RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
/* Configure the main PLL */
RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
/* Enable the main PLL */
RCC->CR |= RCC_CR_PLLON;
/* Wait till the main PLL is ready */
while((RCC->CR & RCC_CR_PLLRDY) == 0)
{
}
/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS;
/* Select the main PLL as system clock source */
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
RCC->CFGR |= RCC_CFGR_SW_PLL;
/* Wait till the main PLL is used as system clock source */
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
{
}
}
else
{ /* If HSE fails to start-up, the application will have wrong clock
configuration. User can add here some code to deal with this error */
}
}
/**
* @brief Setup the external memory controller. Called in startup_stm32f2xx.s
* before jump to __main
* @param None
* @retval None
*/
#ifdef DATA_IN_ExtSRAM
/**
* @brief Setup the external memory controller.
* Called in startup_stm32f2xx.s before jump to main.
* This function configures the external SRAM mounted on STM322xG_EVAL board
* This SRAM will be used as program data memory (including heap and stack).
* @param None
* @retval None
*/
void SystemInit_ExtMemCtl(void)
{
/*-- GPIOs Configuration -----------------------------------------------------*/
/*
+-------------------+--------------------+------------------+------------------+
+ SRAM pins assignment +
+-------------------+--------------------+------------------+------------------+
| PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 |
| PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 |
| PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 |
| PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 |
| PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 |
| PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 |
| PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 |
| PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+
| PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 |
| PD14 <-> FSMC_D0 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 |
| PD15 <-> FSMC_D1 | PE15 <-> FSMC_D12 |------------------+
+-------------------+--------------------+
*/
/* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
RCC->AHB1ENR = 0x00000078;
/* Connect PDx pins to FSMC Alternate function */
GPIOD->AFR[0] = 0x00cc00cc;
GPIOD->AFR[1] = 0xcc0ccccc;
/* Configure PDx pins in Alternate function mode */
GPIOD->MODER = 0xa2aa0a0a;
/* Configure PDx pins speed to 100 MHz */
GPIOD->OSPEEDR = 0xf3ff0f0f;
/* Configure PDx pins Output type to push-pull */
GPIOD->OTYPER = 0x00000000;
/* No pull-up, pull-down for PDx pins */
GPIOD->PUPDR = 0x00000000;
/* Connect PEx pins to FSMC Alternate function */
GPIOE->AFR[0] = 0xc00000cc;
GPIOE->AFR[1] = 0xcccccccc;
/* Configure PEx pins in Alternate function mode */
GPIOE->MODER = 0xaaaa800a;
/* Configure PEx pins speed to 100 MHz */
GPIOE->OSPEEDR = 0xffffc00f;
/* Configure PEx pins Output type to push-pull */
GPIOE->OTYPER = 0x00000000;
/* No pull-up, pull-down for PEx pins */
GPIOE->PUPDR = 0x00000000;
/* Connect PFx pins to FSMC Alternate function */
GPIOF->AFR[0] = 0x00cccccc;
GPIOF->AFR[1] = 0xcccc0000;
/* Configure PFx pins in Alternate function mode */
GPIOF->MODER = 0xaa000aaa;
/* Configure PFx pins speed to 100 MHz */
GPIOF->OSPEEDR = 0xff000fff;
/* Configure PFx pins Output type to push-pull */
GPIOF->OTYPER = 0x00000000;
/* No pull-up, pull-down for PFx pins */
GPIOF->PUPDR = 0x00000000;
/* Connect PGx pins to FSMC Alternate function */
GPIOG->AFR[0] = 0x00cccccc;
GPIOG->AFR[1] = 0x000000c0;
/* Configure PGx pins in Alternate function mode */
GPIOG->MODER = 0x00080aaa;
/* Configure PGx pins speed to 100 MHz */
GPIOG->OSPEEDR = 0x000c0fff;
/* Configure PGx pins Output type to push-pull */
GPIOG->OTYPER = 0x00000000;
/* No pull-up, pull-down for PGx pins */
GPIOG->PUPDR = 0x00000000;
/*-- FSMC Configuration ------------------------------------------------------*/
/* Enable the FSMC interface clock */
RCC->AHB3ENR = 0x00000001;
/* Configure and enable Bank1_SRAM2 */
FSMC_Bank1->BTCR[2] = 0x00001015;
FSMC_Bank1->BTCR[3] = 0x00010400;
FSMC_Bank1E->BWTR[2] = 0x0fffffff;
/*
Bank1_SRAM2 is configured as follow:
p.FSMC_AddressSetupTime = 0;
p.FSMC_AddressHoldTime = 0;
p.FSMC_DataSetupTime = 4;
p.FSMC_BusTurnAroundDuration = 1;
p.FSMC_CLKDivision = 0;
p.FSMC_DataLatency = 0;
p.FSMC_AccessMode = FSMC_AccessMode_A;
FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
*/
}
#endif /* DATA_IN_ExtSRAM */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::File System
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: FS_Config.c
* Purpose: File System Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>File System
// <i>Define File System global parameters
// <o>Number of open files <4-16>
// <i>Define number of files that can be
// <i>opened at the same time.
// <i>Default: 8
#define NUM_FILES 8
// <o>FAT Name Cache Size <0-1000000>
// <i>Define number of cached FAT file or directory names.
// <i>48 bytes of RAM is required for each cached name.
#define FAT_NAME_CACHE_SIZE 0
// <e>Relocate FAT Name Cache Buffer
// <i>Locate Cache Buffer at a specific address.
#define FAT_NAME_CACHE_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Define the Cache buffer base address.
#define FAT_NAME_CACHE_ADDR 0x60000000
// </e>
// </h>
#include "..\RTE_Components.h"
#ifdef RTE_FileSystem_Drive_RAM
#include "FS_Config_RAM.h"
#endif
#ifdef RTE_FileSystem_Drive_NOR_0
#include "FS_Config_NOR_0.h"
#endif
#ifdef RTE_FileSystem_Drive_NOR_1
#include "FS_Config_NOR_1.h"
#endif
#ifdef RTE_FileSystem_Drive_NAND_0
#include "FS_Config_NAND_0.h"
#endif
#ifdef RTE_FileSystem_Drive_NAND_1
#include "FS_Config_NAND_1.h"
#endif
#ifdef RTE_FileSystem_Drive_MC_0
#include "FS_Config_MC_0.h"
#endif
#ifdef RTE_FileSystem_Drive_MC_1
#include "FS_Config_MC_1.h"
#endif
#ifdef RTE_FileSystem_Drive_USB_0
#include "FS_Config_USB_0.h"
#endif
#ifdef RTE_FileSystem_Drive_USB_1
#include "FS_Config_USB_1.h"
#endif
#include "fs_config.h"

57
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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::File System:Drive
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: FS_Config_MC_0.h
* Purpose: File System Configuration for Memory Card Drive
* Rev.: V5.01
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Memory Card Drive 0
// <i>Configuration for SD/SDHC/MMC Memory Card assigned to drive letter "M0:"
#define MC0_ENABLE 1
// <o>Connect to hardware via Driver_MCI# <0-255>
// <i>Select driver control block for hardware interface
#define MC0_MCI_DRIVER 0
// <o>Connect to hardware via Driver_SPI# <0-255>
// <i>Select driver control block for hardware interface when in SPI mode
#define MC0_SPI_DRIVER 0
// <o>Memory Card Interface Mode <0=>Native <1=>SPI
// <i>Native uses a SD Bus with up to 8 data lines, CLK, and CMD
// <i>SPI uses 2 data lines (MOSI and MISO), SCLK and CS
// <i>When using SPI both Driver_SPI# and Driver_MCI# must be specified
// <i>since the MCI driver provides the control interface lines.
#define MC0_SPI 0
// <o>Drive Cache Size <0=>OFF <1=>1 KB <2=>2 KB <4=>4 KB
// <8=>8 KB <16=>16 KB <32=>32 KB
// <i>Drive Cache stores data sectors and may be increased to speed-up
// <i>file read/write operations on this drive (default: 4 KB)
#define MC0_CACHE_SIZE 4
// <e>Locate Drive Cache and Drive Buffer
// <i>Some microcontrollers support DMA only in specific memory areas and
// <i>require to locate the drive buffers at a fixed address.
#define MC0_CACHE_RELOC 0
// <o>Base address <0x0000-0xFFFFFE00:0x200>
// <i>Set buffer base address to RAM areas that support DMA with the drive.
#define MC0_CACHE_ADDR 0x7FD00000
// </e>
// <q>Use FAT Journal
// <i>Protect File Allocation Table and Directory Entries for
// <i>fail-safe operation.
#define MC0_FAT_JOURNAL 0
// <q>Default Drive "M0:"
// <i>Use this drive when no drive letter is specified.
#define MC0_DEFAULT_DRIVE 1
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config.c
* Purpose: Network Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>System Definitions
// <i> Global Network System definitions
// <s.15>Local Host Name
// <i> This is the name under which embedded host can be
// <i> accessed on a local area network.
// <i> Default: "my_host"
#define NET_HOST_NAME "my_host"
// <o>Memory Pool size <1536-262144:4><#/4>
// <i> This is the size of a memory pool in bytes. Buffers for
// <i> Network packets are allocated from this memory pool.
// <i> Default: 12000 bytes
#define NET_MEM_SIZE 3000
// </h>
#include "..\RTE_Components.h"
#ifdef RTE_Network_Interface_ETH_0
#include "Net_Config_ETH_0.h"
#endif
#ifdef RTE_Network_Interface_ETH_1
#include "Net_Config_ETH_1.h"
#endif
#ifdef RTE_Network_Interface_PPP_0
#include "Net_Config_PPP_0.h"
#endif
#ifdef RTE_Network_Interface_PPP_1
#include "Net_Config_PPP_1.h"
#endif
#ifdef RTE_Network_Interface_SLIP_0
#include "Net_Config_SLIP_0.h"
#endif
#ifdef RTE_Network_Interface_SLIP_1
#include "Net_Config_SLIP_1.h"
#endif
#ifdef RTE_Network_Socket_UDP
#include "Net_Config_UDP.h"
#endif
#ifdef RTE_Network_Socket_TCP
#include "Net_Config_TCP.h"
#endif
#ifdef RTE_Network_Socket_BSD
#include "Net_Config_BSD.h"
#endif
#ifdef RTE_Network_Web_Server_RO
#include "Net_Config_HTTP_Server.h"
#endif
#ifdef RTE_Network_Web_Server_FS
#include "Net_Config_HTTP_Server.h"
#endif
#ifdef RTE_Network_Telnet_Server
#include "Net_Config_Telnet_Server.h"
#endif
#ifdef RTE_Network_TFTP_Server
#include "Net_Config_TFTP_Server.h"
#endif
#ifdef RTE_Network_TFTP_Client
#include "Net_Config_TFTP_Client.h"
#endif
#ifdef RTE_Network_FTP_Server
#include "Net_Config_FTP_Server.h"
#endif
#ifdef RTE_Network_FTP_Client
#include "Net_Config_FTP_Client.h"
#endif
#ifdef RTE_Network_DNS_Client
#include "Net_Config_DNS_Client.h"
#endif
#ifdef RTE_Network_SMTP_Client
#include "Net_Config_SMTP_Client.h"
#endif
#ifdef RTE_Network_SNMP_Agent
#include "Net_Config_SNMP_Agent.h"
#endif
#ifdef RTE_Network_SNTP_Client
#include "Net_Config_SNTP_Client.h"
#endif
#include "net_config.h"
/**
\addtogroup net_genFunc
@{
*/
/**
\fn void net_sys_error (ERROR_CODE error)
\ingroup net_cores
\brief Network system error handler.
*/
void net_sys_error (ERROR_CODE error) {
/* This function is called when a fatal error is encountered. */
/* The normal program execution is not possible anymore. */
switch (error) {
case ERR_MEM_ALLOC:
/* Out of memory */
break;
case ERR_MEM_FREE:
/* Trying to release non existing memory block */
break;
case ERR_MEM_CORRUPT:
/* Memory Link pointer Corrupted */
/* More data written than the size of allocated mem block */
break;
case ERR_MEM_LOCK:
/* Locked Memory management function (alloc/free) re-entered */
break;
case ERR_UDP_ALLOC:
/* Out of UDP Sockets */
break;
case ERR_TCP_ALLOC:
/* Out of TCP Sockets */
break;
case ERR_TCP_STATE:
/* TCP State machine in undefined state */
break;
}
/* End-less loop */
while (1);
}
/**
@}
*/

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Socket
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_BSD.h
* Purpose: Network Configuration BSD Sockets
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Berkley (BSD) Sockets
#define BSD_ENABLE 1
// <o>Number of BSD Sockets <1-20>
// <i> Number of available Berkeley Sockets
// <i> Default: 2
#define BSD_NUM_SOCKS 7
// <o>Number of Streaming Server Sockets <0-20>
// <i> Defines a number of Streaming (TCP) Server sockets,
// <i> that listen for an incoming connection from the client.
// <i> Default: 1
#define BSD_SERVER_SOCKS 1
// <o>Receive Timeout in seconds <0-600>
// <i> A timeout for socket receive in blocking mode.
// <i> Timeout value of 0 means indefinite timeout.
// <i> Default: 20
#define BSD_RECEIVE_TOUT 20
// <q>Hostname Resolver
// <i> Enable or disable Berkeley style hostname resolver.
#define BSD_HOSTNAME_ENABLE 0
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Service
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_DNS_Client.h
* Purpose: Network Configuration DNS Client
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>DNS Client
#define DNS_CLIENT_ENABLE 1
// <o>Cache Table size <5-100>
// <i> Number of cached DNS host names/IP addresses
// <i> Default: 20
#define DNS_CLIENT_TAB_SIZE 20
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Interface
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_ETH_0.h
* Purpose: Network Configuration ETH Interface
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>Ethernet Network Interface 0
#define ETH0_ENABLE 1
// <o>Connect to hardware via Driver_ETH# <0-255>
// <i>Select driver control block for MAC and PHY interface
#define ETH0_DRIVER 0
// <h>MAC Address
// <i> Local Ethernet MAC Address
// <i> Value FF:FF:FF:FF:FF:FF is not allowed.
// <i> It is an ethernet Broadcast MAC address.
// <o>Address byte 1 <0x00-0xff:2>
// <i> LSB is an ethernet Multicast bit.
// <i> Must be 0 for local MAC address.
// <i> Default: 0x1E
#define ETH0_MAC1 0x1E
// <o>Address byte 2 <0x00-0xff>
// <i> Default: 0x30
#define ETH0_MAC2 0x30
// <o>Address byte 3 <0x00-0xff>
// <i> Default: 0x6C
#define ETH0_MAC3 0x6C
// <o>Address byte 4 <0x00-0xff>
// <i> Default: 0xA2
#define ETH0_MAC4 0xA2
// <o>Address byte 5 <0x00-0xff>
// <i> Default: 0x45
#define ETH0_MAC5 0x45
// <o>Address byte 6 <0x00-0xff>
// <i> Default: 0x5E
#define ETH0_MAC6 0x5E
// </h>
// <h>IP Address
// <i> Local Static IP Address
// <i> Value 255.255.255.255 is not allowed.
// <i> It is a Broadcast IP address.
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define ETH0_IP1 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define ETH0_IP2 168
// <o>Address byte 3 <0-255>
// <i> Default: 0
#define ETH0_IP3 0
// <o>Address byte 4 <0-255>
// <i> Default: 100
#define ETH0_IP4 100
// </h>
// <h>Subnet mask
// <i> Local Subnet mask
// <o>Mask byte 1 <0-255>
// <i> Default: 255
#define ETH0_MASK1 255
// <o>Mask byte 2 <0-255>
// <i> Default: 255
#define ETH0_MASK2 255
// <o>Mask byte 3 <0-255>
// <i> Default: 255
#define ETH0_MASK3 255
// <o>Mask byte 4 <0-255>
// <i> Default: 0
#define ETH0_MASK4 0
// </h>
// <h>Default Gateway
// <i> Default Gateway IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 192
#define ETH0_GW1 192
// <o>Address byte 2 <0-255>
// <i> Default: 168
#define ETH0_GW2 168
// <o>Address byte 3 <0-255>
// <i> Default: 0
#define ETH0_GW3 0
// <o>Address byte 4 <0-255>
// <i> Default: 254
#define ETH0_GW4 254
// </h>
// <h>Primary DNS Server
// <i> Primary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define ETH0_PRI_DNS1 194
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define ETH0_PRI_DNS2 25
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define ETH0_PRI_DNS3 2
// <o>Address byte 4 <0-255>
// <i> Default: 129
#define ETH0_PRI_DNS4 129
// </h>
// <h>Secondary DNS Server
// <i> Secondary DNS Server IP Address
// <o>Address byte 1 <0-255>
// <i> Default: 194
#define ETH0_SEC_DNS1 194
// <o>Address byte 2 <0-255>
// <i> Default: 25
#define ETH0_SEC_DNS2 25
// <o>Address byte 3 <0-255>
// <i> Default: 2
#define ETH0_SEC_DNS3 2
// <o>Address byte 4 <0-255>
// <i> Default: 130
#define ETH0_SEC_DNS4 130
// </h>
// <h>ARP Definitions
// <i> Address Resolution Protocol Definitions
// <o>Cache Table size <5-100>
// <i> Number of cached hardware/IP addresses
// <i> Default: 10
#define ETH0_ARP_TAB_SIZE 10
// <o>Cache Timeout in seconds <5-255>
// <i> A timeout for a cached hardware/IP addresses
// <i> Default: 150
#define ETH0_ARP_CACHE_TOUT 150
// <o>Number of Retries <0-20>
// <i> Number of Retries to resolve an IP address
// <i> before ARP module gives up
// <i> Default: 4
#define ETH0_ARP_MAX_RETRY 4
// <o>Resend Timeout in seconds <1-10>
// <i> A timeout to resend the ARP Request
// <i> Default: 2
#define ETH0_ARP_RESEND_TOUT 2
// <q>Send Notification on Address changes
// <i> When this option is enabled, the embedded host
// <i> will send a Gratuitous ARP notification at startup,
// <i> or when the device IP address has changed.
// <i> Default: Disabled
#define ETH0_ARP_NOTIFY 0
// </h>
// <e>IGMP Group Management
// <i> Enable or disable Internet Group Management Protocol
#define ETH0_IGMP_ENABLE 0
// <o>Membership Table size <2-50>
// <i> Number of Groups this host can join
// <i> Default: 5
#define ETH0_IGMP_TAB_SIZE 5
// </e>
// <q>NetBIOS Name Service
// <i> When this option is enabled, the embedded host can be
// <i> accessed by his name on the local LAN using NBNS protocol.
// <i> You need to modify also the number of UDP Sockets,
// <i> because NBNS protocol uses one UDP socket to run.
#define ETH0_NBNS_ENABLE 1
// <e>Dynamic Host Configuration
// <i> When this option is enabled, local IP address, Net Mask
// <i> and Default Gateway are obtained automatically from
// <i> the DHCP Server on local LAN.
// <i> You need to modify also the number of UDP Sockets,
// <i> because DHCP protocol uses one UDP socket to run.
#define ETH0_DHCP_ENABLE 1
// <s.40>Vendor Class Identifier
// <i> This value is optional. If specified, it is added
// <i> to DHCP request message, identifying vendor type.
// <i> Default: ""
#define ETH0_DHCP_VCID ""
// <q>Bootfile Name
// <i> This value is optional. If enabled, the Bootfile Name
// <i> (option 67) is also requested from DHCP server.
// <i> Default: disabled
#define ETH0_DHCP_BOOTFILE 0
// <q>NTP Servers
// <i> This value is optional. If enabled, a list of NTP Servers
// <i> (option 42) is also requested from DHCP server.
// <i> Default: disabled
#define ETH0_DHCP_NTP_SERVERS 0
// </e>
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Socket
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_TCP.h
* Purpose: Network Configuration TCP Sockets
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>TCP Sockets
#define TCP_ENABLE 1
// <o>Number of TCP Sockets <1-20>
// <i> Number of available TCP sockets
// <i> Default: 5
#define TCP_NUM_SOCKS 10
// <o>Number of Retries <0-20>
// <i> How many times TCP module will try to retransmit data
// <i> before giving up. Increase this value for high-latency
// <i> and low_throughput networks.
// <i> Default: 5
#define TCP_MAX_RETRY 5
// <o>Retry Timeout in seconds <1-10>
// <i> If data frame not acknowledged within this time frame,
// <i> TCP module will try to resend the data again.
// <i> Default: 4
#define TCP_RETRY_TOUT 4
// <o>Default Connect Timeout in seconds <1-600>
// <i> Default TCP Socket Keep Alive timeout. When it expires
// <i> with no TCP data frame send, TCP Connection is closed.
// <i> Default: 120
#define TCP_DEFAULT_TOUT 120
// <o>Maximum Segment Size <536-1460>
// <i> The Maximum Segment Size specifies the maximum
// <i> number of bytes in the TCP segment's Data field.
// <i> Default: 1460
#define TCP_MAX_SEG_SIZE 1460
// <o>Receive Window Size <536-65535>
// <i> Receive Window Size specifies the size of data,
// <i> that the socket is able to buffer in flow-control mode.
// <i> Default: 4380
#define TCP_RECEIVE_WIN_SIZE 4380
// </h>
// TCP Initial Retransmit period in seconds
#define TCP_INITIAL_RETRY_TOUT 1
// TCP SYN frame retransmit period in seconds
#define TCP_SYN_RETRY_TOUT 2
// Number of retries to establish a connection
#define TCP_CONNECT_RETRY 7

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network:Socket
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Config_UDP.h
* Purpose: Network Configuration UDP Sockets
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <h>UDP Sockets
#define UDP_ENABLE 1
// <o>Number of UDP Sockets <1-20>
// <i> Number of available UDP sockets
// <i> Default: 5
#define UDP_NUM_SOCKS 10
// </h>

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/*------------------------------------------------------------------------------
* MDK Middleware - Component ::Network
* Copyright (c) 2004-2013 ARM Germany GmbH. All rights reserved.
*------------------------------------------------------------------------------
* Name: Net_Debug.c
* Purpose: Network Debug Configuration
* Rev.: V5.00
*----------------------------------------------------------------------------*/
//-------- <<< Use Configuration Wizard in Context Menu >>> --------------------
// <q>Print Time Stamp
// <i> Enable printing the time-info in debug messages
#define DBG_TIME 1
// <h>TCPnet Debug Definitions
// <o>Memory Management Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Dynamic Memory debug messages
#define DBG_MEM 1
// <o>Ethernet Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Ethernet debug messages
#define DBG_ETH 0
// <o>PPP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off PPP debug messages
#define DBG_PPP 0
// <o>SLIP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off SLIP debug messages
#define DBG_SLIP 0
// <o>ARP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off ARP debug messages
#define DBG_ARP 0
// <o>IP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off IP debug messages
#define DBG_IP 1
// <o>ICMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off ICMP debug messages
#define DBG_ICMP 1
// <o>IGMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off IGMP debug messages
#define DBG_IGMP 1
// <o>UDP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off UDP debug messages
#define DBG_UDP 1
// <o>TCP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TCP debug messages
#define DBG_TCP 1
// <o>NBNS Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off NetBIOS Name Service debug messages
#define DBG_NBNS 1
// <o>DHCP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Dynamic Host Configuration debug messages
#define DBG_DHCP 1
// <o>DNS Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Domain Name Service debug messages
#define DBG_DNS 1
// <o>SNMP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Simple Network Management debug messages
#define DBG_SNMP 1
// <o>SNTP Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Simple Network Time debug messages
#define DBG_SNTP 1
// <o>BSD Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off BSD Interface debug messages
#define DBG_BSD 1
// </h>
// <h>Application Debug Definitions
// <o>HTTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Web Server debug messages
#define DBG_HTTP_SERVER 1
// <o>FTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off FTP Server debug messages
#define DBG_FTP_SERVER 1
// <o>FTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off FTP Client debug messages
#define DBG_FTP_CLIENT 1
// <o>Telnet Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off Telnet Server debug messages
#define DBG_TELNET_SERVER 1
// <o>TFTP Server Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TFTP Server debug messages
#define DBG_TFTP_SERVER 1
// <o>TFTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off TFTP Client debug messages
#define DBG_TFTP_CLIENT 1
// <o>SMTP Client Debug <0=> Off <1=> Errors only <2=> Full debug
// <i> Turn On/Off SMTP Client debug messages
#define DBG_SMTP_CLIENT 1
// </h>
#include "net_debug.h"
/**
\fn void net_debug_init (void)
\brief Initialize Network Debug Interface.
*/
void net_debug_init (void) {
/* Add your code to initialize the Debug output. This is usually the */
/* serial interface. The function is called at TCPnet system startup. */
/* You may need to customize also the 'putchar()' function. */
}

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/*
* Auto generated Run-Time-Environment Component Configuration File
* *** Do not modify ! ***
*
* Project: 'simpleClient'
* Target: 'SimpleClient'
*/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#define RTE_DEVICE_STARTUP_STM32F2xx /* Device Startup for STM32F2 */
#define RTE_Drivers_ETH_MAC0 /* Driver ETH_MAC0 */
#define RTE_Drivers_MCI0 /* Driver MCI0 */
#define RTE_Drivers_PHY_ST802RT1 /* Driver PHY ST802RT1 */
#define RTE_FileSystem_Core /* File System Core */
#define RTE_FileSystem_LFN /* File System with Long Filename support */
#define RTE_FileSystem_Drive_MC_0 /* File System Memory Card Drive 0 */
#define RTE_Network_Core /* Network Core */
#define RTE_Network_Debug /* Network Debug Version */
#define RTE_Network_DNS_Client /* Network DNS Client */
#define RTE_Network_Interface_ETH_0 /* Network Interface ETH 0 */
#define RTE_Network_Socket_BSD /* Network Socket BSD */
#define RTE_Network_Socket_TCP /* Network Socket TCP */
#define RTE_Network_Socket_UDP /* Network Socket UDP */
#endif /* RTE_COMPONENTS_H */

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/* config-FS.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// <<< Use Configuration Wizard in Context Menu >>>
// <h> wolfCrypt Configuration
// <h>Cert/Key Strage
// <o>Cert Storage <0=> SD Card <1=> Mem Buff (1024bytes) <2=> Mem Buff (2048bytes)
#define MDK_CONF_CERT_BUFF 0
#if MDK_CONF_CERT_BUFF== 1
#define USE_CERT_BUFFERS_1024
#elif MDK_CONF_CERT_BUFF == 2
#define USE_CERT_BUFFERS_2048
#endif
//</h>
// <h>Crypt Algrithm
// <h>MD5, SHA, SHA-256, AES, RC4, ASN, RSA
// </h>
// <e>MD2
#define MDK_CONF_MD2 0
#if MDK_CONF_MD2 == 1
#define CYASSL_MD2
#endif
// </e>
// <e>MD4
#define MDK_CONF_MD4 1
#if MDK_CONF_MD4 == 0
#define NO_MD4
#endif
// </e>
// <e>SHA-384
// <i>This has to be with SHA512
#define MDK_CONF_SHA384 0
#if MDK_CONF_SHA384 == 1
#define CYASSL_SHA384
#endif
// </e>
// <e>SHA-512
#define MDK_CONF_SHA512 0
#if MDK_CONF_SHA512 == 1
#define CYASSL_SHA512
#endif
// </e>
// <e>RIPEMD
#define MDK_CONF_RIPEMD 0
#if MDK_CONF_RIPEMD == 1
#define CYASSL_RIPEMD
#endif
// </e>
// <e>HMAC
#define MDK_CONF_HMAC 1
#if MDK_CONF_HMAC == 0
#define NO_HMAC
#endif
// </e>
// <e>HC128
#define MDK_CONF_HC128 0
#if MDK_CONF_HC128 == 1
#define HAVE_HC128
#endif
// </e>
// <e>RABBIT
#define MDK_CONF_RABBIT 1
#if MDK_CONF_RABBI == 0
#define NO_RABBIT
#endif
// </e>
// <e>AEAD
#define MDK_CONF_AEAD 0
#if MDK_CONF_AEAD == 1
#define HAVE_AEAD
#endif
// </e>
// <e>DES3
#define MDK_CONF_DES3 1
#if MDK_CONF_DES3 == 0
#define NO_DES3
#endif
// </e>
// <e>CAMELLIA
#define MDK_CONF_CAMELLIA 0
#if MDK_CONF_CAMELLIA == 1
#define HAVE_CAMELLIA
#endif
// </e>
// <e>DH
// <i>need this for CYASSL_SERVER, OPENSSL_EXTRA
#define MDK_CONF_DH 1
#if MDK_CONF_DH == 0
#define NO_DH
#endif
// </e>
// <e>DSA
#define MDK_CONF_DSA 1
#if MDK_CONF_DSA == 0
#define NO_DSA
#endif
// </e>
// <e>PWDBASED
#define MDK_CONF_PWDBASED 1
#if MDK_CONF_PWDBASED == 0
#define NO_PWDBASED
#endif
// </e>
// <e>ECC
#define MDK_CONF_ECC 0
#if MDK_CONF_ECC == 1
#define HAVE_ECC
#endif
// </e>
// <e>PSK
#define MDK_CONF_PSK 1
#if MDK_CONF_PSK == 0
#define NO_PSK
#endif
// </e>
// <e>AESCCM (Turn off Hardware Crypt)
#define MDK_CONF_AESCCM 0
#if MDK_CONF_AESCCM == 1
#define HAVE_AESCCM
#endif
// </e>
// <e>AESGCM (Turn off Hardware Crypt)
#define MDK_CONF_AESGCM 0
#if MDK_CONF_AESGCM == 1
#define HAVE_AESGCM
#define BUILD_AESGCM
#endif
// </e>
// <e>NTRU (need License, "crypto_ntru.h")
#define MDK_CONF_NTRU 0
#if MDK_CONF_NTRU == 1
#define HAVE_NTRU
#endif
// </e>
// </h>
// <h>Hardware Crypt (See document for usage)
// <e>Hardware RNG
#define MDK_CONF_STM32F2_RNG 0
#if MDK_CONF_STM32F2_RNG == 1
#define STM32F2_RNG
#else
#endif
// </e>
// <e>Hardware Crypt
#define MDK_CONF_STM32F2_CRYPTO 0
#if MDK_CONF_STM32F2_CRYPTO == 1
#define STM32F2_CRYPTO
#endif
// </e>
// </h>
//</h>
// <<< end of configuration section >>>

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/* config-RTX-TCP-FS.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/**** CyaSSL for KEIL-RL Configuration ****/
#define __CORTEX_M3__
#define CYASSL_MDK_ARM
#define NO_WRITEV
#define NO_CYASSL_DIR
#define NO_MAIN_DRIVER
#define CYASSL_DER_LOAD
#define HAVE_NULL_CIPHER
#define HAVE_KEIL_RTX
#define CYASSL_CMSIS_RTOS
#define CYASSL_KEIL_TCP_NET
// <<< Use Configuration Wizard in Context Menu >>>
// <h> CyaSSL Configuration
// <h>SSL (Included by default)
// </h>
// <e>TLS
#define MDK_CONF_TLS 1
#if MDK_CONF_TLS == 0
#define NO_TLS
#endif
// </e>
// <e>CRL
#define MDK_CONF_DER_LOAD 0
#if MDK_CONF_DER_LOAD == 1
#define CYASSL_DER_LOAD
#endif
// </e>
// <e>OpenSSL Extra
#define MDK_CONF_OPENSSL_EXTRA 1
#if MDK_CONF_OPENSSL_EXTRA == 1
#define OPENSSL_EXTRA
#endif
// </e>
//</h>
// <h>Cert/Key Generation
// <e>CertGen
#define MDK_CONF_CERT_GEN 0
#if MDK_CONF_CERT_GEN == 1
#define CYASSL_CERT_GEN
#endif
// </e>
// <e>KeyGen
#define MDK_CONF_KEY_GEN 0
#if MDK_CONF_KEY_GEN == 1
#define CYASSL_KEY_GEN
#endif
// </e>
//</h>
// <h>Others
// <e>Inline
#define MDK_CONF_INLINE 0
#if MDK_CONF_INLINE == 0
#define NO_INLINE
#endif
// </e>
// <h>Debug
// <e>Debug Message
#define MDK_CONF_DebugMessage 0
#if MDK_CONF_DebugMessage == 1
#define DEBUG_CYASSL
#endif
// </e>
// <e>Check malloc
#define MDK_CONF_CheckMalloc 1
#if MDK_CONF_CheckMalloc == 1
#define CYASSL_MALLOC_CHECK
#endif
// </e>
// </h>
// <e>ErrNo.h
#define MDK_CONF_ErrNo 0
#if MDK_CONF_ErrNo == 1
#define HAVE_ERRNO
#endif
// </e>
// <e>Error Strings
#define MDK_CONF_ErrorStrings 1
#if MDK_CONF_ErrorStrings == 0
#define NO_ERROR_STRINGS
#endif
// </e>
// <e>zlib (need "zlib.h")
#define MDK_CONF_LIBZ 0
#if MDK_CONF_LIBZ == 1
#define HAVE_LIBZ
#endif
// </e>
// <e>CAVIUM (need CAVIUM headers)
#define MDK_CONF_CAVIUM 0
#if MDK_CONF_CAVIUM == 1
#define HAVE_CAVIUM
#endif
// </e>
// <e>Small Stack
#define MDK_CONF_SmallStack 1
#if MDK_CONF_SmallStack == 0
#define NO_CYASSL_SMALL_STACK
#endif
// </e>
// <e>Use Fast Math
#define MDK_CONF_FASTMATH 0
#if MDK_CONF_FASTMATH == 1
#define USE_FAST_MATH
#endif
// </e>
// </h>
// <<< end of configuration section >>>

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IDE/MDK5-ARM/Projects/SimpleClient/RTE/wolfSSL/settings.h
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@ -1,667 +0,0 @@
/* settings.h
*
* Copyright (C) 2006-2013 wolfSSL Inc.
*
* This file is part of CyaSSL.
*
* CyaSSL is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* CyaSSL is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/* Place OS specific preprocessor flags, defines, includes here, will be
included into every file because types.h includes it */
#ifndef CTAO_CRYPT_SETTINGS_H
#define CTAO_CRYPT_SETTINGS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Uncomment next line if using IPHONE */
/* #define IPHONE */
/* Uncomment next line if using ThreadX */
/* #define THREADX */
/* Uncomment next line if using Micrium ucOS */
/* #define MICRIUM */
/* Uncomment next line if using Mbed */
/* #define MBED */
/* Uncomment next line if using Microchip PIC32 ethernet starter kit */
/* #define MICROCHIP_PIC32 */
/* Uncomment next line if using Microchip TCP/IP stack, version 5 */
/* #define MICROCHIP_TCPIP_V5 */
/* Uncomment next line if using Microchip TCP/IP stack, version 6 or later */
/* #define MICROCHIP_TCPIP */
/* Uncomment next line if using PIC32MZ Crypto Engine */
/* #define CYASSL_MICROCHIP_PIC32MZ */
/* Uncomment next line if using FreeRTOS */
/* #define FREERTOS */
/* Uncomment next line if using FreeRTOS Windows Simulator */
/* #define FREERTOS_WINSIM */
/* Uncomment next line if using RTIP */
/* #define EBSNET */
/* Uncomment next line if using lwip */
/* #define CYASSL_LWIP */
/* Uncomment next line if building CyaSSL for a game console */
/* #define CYASSL_GAME_BUILD */
/* Uncomment next line if building CyaSSL for LSR */
/* #define CYASSL_LSR */
/* Uncomment next line if building CyaSSL for Freescale MQX/RTCS/MFS */
/* #define FREESCALE_MQX */
/* Uncomment next line if using STM32F2 */
/* #define CYASSL_STM32F2 */
/* Uncomment next line if using Comverge settings */
/* #define COMVERGE */
/* Uncomment next line if using QL SEP settings */
/* #define CYASSL_QL */
/* Uncomment next line if using LwIP native TCP socket settings */
/* #define HAVE_LWIP_NATIVE */
/* Uncomment next line if building for EROAD */
/* #define CYASSL_EROAD */
#include <cyassl/ctaocrypt/visibility.h>
#ifdef IPHONE
#define SIZEOF_LONG_LONG 8
#endif
#ifdef CYASSL_USER_SETTINGS
#include <user_settings.h>
#endif
#ifdef COMVERGE
#define THREADX
#define HAVE_NETX
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define NO_RSA
#define NO_SESSION_CACHE
#define HAVE_ECC
#endif
#ifdef THREADX
#define SIZEOF_LONG_LONG 8
#endif
#ifdef HAVE_NETX
#include "nx_api.h"
#endif
#if defined(HAVE_LWIP_NATIVE) /* using LwIP native TCP socket */
#define CYASSL_LWIP
#define NO_WRITEV
#define SINGLE_THREADED
#define CYASSL_USER_IO
#define NO_FILESYSTEM
#endif
#ifdef MICROCHIP_PIC32
/* #define CYASSL_MICROCHIP_PIC32MZ */
#define SIZEOF_LONG_LONG 8
#define SINGLE_THREADED
#define CYASSL_USER_IO
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_FILESYSTEM
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#endif
#ifdef CYASSL_MICROCHIP_PIC32MZ
#define CYASSL_PIC32MZ_CE
#define CYASSL_PIC32MZ_CRYPT
#define HAVE_AES_ENGINE
#define CYASSL_PIC32MZ_RNG
/* #define CYASSL_PIC32MZ_HASH */
#define CYASSL_AES_COUNTER
#define HAVE_AESGCM
#define NO_BIG_INT
#endif
#ifdef MICROCHIP_TCPIP_V5
/* include timer functions */
#include "TCPIP Stack/TCPIP.h"
#endif
#ifdef MICROCHIP_TCPIP
/* include timer, NTP functions */
#ifdef MICROCHIP_MPLAB_HARMONY
#include "tcpip/tcpip.h"
#else
#include "system/system_services.h"
#include "tcpip/sntp.h"
#endif
#endif
#ifdef MBED
#define CYASSL_USER_IO
#define NO_FILESYSTEM
#define NO_CERT
#define USE_CERT_BUFFERS_1024
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define HAVE_ECC
#define NO_SESSION_CACHE
#define CYASSL_CMSIS_RTOS
#endif
#ifdef CYASSL_EROAD
#define FREESCALE_MQX
#define FREESCALE_MMCAU
#define SINGLE_THREADED
#define NO_STDIO_FILESYSTEM
#define CYASSL_LEANPSK
#define HAVE_NULL_CIPHER
#define NO_OLD_TLS
#define NO_ASN
#define NO_BIG_INT
#define NO_RSA
#define NO_DSA
#define NO_DH
#define NO_CERTS
#define NO_PWDBASED
#define NO_DES3
#define NO_MD4
#define NO_RC4
#define NO_MD5
#define NO_SESSION_CACHE
#define NO_MAIN_DRIVER
#endif
#ifdef FREERTOS_WINSIM
#define FREERTOS
#define USE_WINDOWS_API
#endif
/* Micrium will use Visual Studio for compilation but not the Win32 API */
#if defined(_WIN32) && !defined(MICRIUM) && !defined(FREERTOS) \
&& !defined(EBSNET) && !defined(CYASSL_EROAD)
#define USE_WINDOWS_API
#endif
#if defined(CYASSL_LEANPSK) && !defined(XMALLOC_USER)
#include <stdlib.h>
#define XMALLOC(s, h, type) malloc((s))
#define XFREE(p, h, type) free((p))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif
#if defined(XMALLOC_USER) && defined(SSN_BUILDING_LIBYASSL)
#undef XMALLOC
#define XMALLOC yaXMALLOC
#undef XFREE
#define XFREE yaXFREE
#undef XREALLOC
#define XREALLOC yaXREALLOC
#endif
#ifdef FREERTOS
#ifndef NO_WRITEV
#define NO_WRITEV
#endif
#ifndef NO_SHA512
#define NO_SHA512
#endif
#ifndef NO_DH
#define NO_DH
#endif
#ifndef NO_DSA
#define NO_DSA
#endif
#ifndef NO_HC128
#define NO_HC128
#endif
#ifndef SINGLE_THREADED
#include "FreeRTOS.h"
#include "semphr.h"
#endif
#endif
#ifdef EBSNET
#include "rtip.h"
/* #define DEBUG_CYASSL */
#define NO_CYASSL_DIR /* tbd */
#if (POLLOS)
#define SINGLE_THREADED
#endif
#if (RTPLATFORM)
#if (!RTP_LITTLE_ENDIAN)
#define BIG_ENDIAN_ORDER
#endif
#else
#if (!KS_LITTLE_ENDIAN)
#define BIG_ENDIAN_ORDER
#endif
#endif
#if (WINMSP3)
#undef SIZEOF_LONG
#define SIZEOF_LONG_LONG 8
#else
#sslpro: settings.h - please implement SIZEOF_LONG and SIZEOF_LONG_LONG
#endif
#define XMALLOC(s, h, type) ((void *)rtp_malloc((s), SSL_PRO_MALLOC))
#define XFREE(p, h, type) (rtp_free(p))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif /* EBSNET */
#ifdef CYASSL_GAME_BUILD
#define SIZEOF_LONG_LONG 8
#if defined(__PPU) || defined(__XENON)
#define BIG_ENDIAN_ORDER
#endif
#endif
#ifdef CYASSL_LSR
#define HAVE_WEBSERVER
#define SIZEOF_LONG_LONG 8
#define CYASSL_LOW_MEMORY
#define NO_WRITEV
#define NO_SHA512
#define NO_DH
#define NO_DSA
#define NO_HC128
#define NO_DEV_RANDOM
#define NO_CYASSL_DIR
#define NO_RABBIT
#ifndef NO_FILESYSTEM
#define LSR_FS
#include "inc/hw_types.h"
#include "fs.h"
#endif
#define CYASSL_LWIP
#include <errno.h> /* for tcp errno */
#define CYASSL_SAFERTOS
#if defined(__IAR_SYSTEMS_ICC__)
/* enum uses enum */
#pragma diag_suppress=Pa089
#endif
#endif
#ifdef CYASSL_SAFERTOS
#ifndef SINGLE_THREADED
#include "SafeRTOS/semphr.h"
#endif
#include "SafeRTOS/heap.h"
#define XMALLOC(s, h, type) pvPortMalloc((s))
#define XFREE(p, h, type) vPortFree((p))
#define XREALLOC(p, n, h, t) pvPortRealloc((p), (n))
#endif
#ifdef CYASSL_LOW_MEMORY
#undef RSA_LOW_MEM
#define RSA_LOW_MEM
#undef CYASSL_SMALL_STACK
#define CYASSL_SMALL_STACK
#undef TFM_TIMING_RESISTANT
#define TFM_TIMING_RESISTANT
#endif
#ifdef FREESCALE_MQX
#define SIZEOF_LONG_LONG 8
#define NO_WRITEV
#define NO_DEV_RANDOM
#define NO_RABBIT
#define NO_CYASSL_DIR
#define USE_FAST_MATH
#define TFM_TIMING_RESISTANT
#define FREESCALE_K70_RNGA
/* #define FREESCALE_K53_RNGB */
#include "mqx.h"
#ifndef NO_FILESYSTEM
#include "mfs.h"
#include "fio.h"
#endif
#ifndef SINGLE_THREADED
#include "mutex.h"
#endif
#define XMALLOC(s, h, t) (void *)_mem_alloc_system((s))
#define XFREE(p, h, t) {void* xp = (p); if ((xp)) _mem_free((xp));}
/* Note: MQX has no realloc, using fastmath above */
#endif
#ifdef CYASSL_STM32F2
#define SIZEOF_LONG_LONG 8
#define NO_DEV_RANDOM
#define NO_CYASSL_DIR
#define NO_RABBIT
#define STM32F2_RNG
#define STM32F2_CRYPTO
#define KEIL_INTRINSICS
#endif
#ifdef MICRIUM
#include "stdlib.h"
#include "net_cfg.h"
#include "ssl_cfg.h"
#include "net_secure_os.h"
#define CYASSL_TYPES
typedef CPU_INT08U byte;
typedef CPU_INT16U word16;
typedef CPU_INT32U word32;
#if (NET_SECURE_MGR_CFG_WORD_SIZE == CPU_WORD_SIZE_32)
#define SIZEOF_LONG 4
#undef SIZEOF_LONG_LONG
#else
#undef SIZEOF_LONG
#define SIZEOF_LONG_LONG 8
#endif
#define STRING_USER
#define XSTRLEN(pstr) ((CPU_SIZE_T)Str_Len((CPU_CHAR *)(pstr)))
#define XSTRNCPY(pstr_dest, pstr_src, len_max) \
((CPU_CHAR *)Str_Copy_N((CPU_CHAR *)(pstr_dest), \
(CPU_CHAR *)(pstr_src), (CPU_SIZE_T)(len_max)))
#define XSTRNCMP(pstr_1, pstr_2, len_max) \
((CPU_INT16S)Str_Cmp_N((CPU_CHAR *)(pstr_1), \
(CPU_CHAR *)(pstr_2), (CPU_SIZE_T)(len_max)))
#define XSTRSTR(pstr, pstr_srch) \
((CPU_CHAR *)Str_Str((CPU_CHAR *)(pstr), \
(CPU_CHAR *)(pstr_srch)))
#define XMEMSET(pmem, data_val, size) \
((void)Mem_Set((void *)(pmem), (CPU_INT08U) (data_val), \
(CPU_SIZE_T)(size)))
#define XMEMCPY(pdest, psrc, size) ((void)Mem_Copy((void *)(pdest), \
(void *)(psrc), (CPU_SIZE_T)(size)))
#define XMEMCMP(pmem_1, pmem_2, size) \
(((CPU_BOOLEAN)Mem_Cmp((void *)(pmem_1), (void *)(pmem_2), \
(CPU_SIZE_T)(size))) ? DEF_NO : DEF_YES)
#define XMEMMOVE XMEMCPY
#if (NET_SECURE_MGR_CFG_EN == DEF_ENABLED)
#define MICRIUM_MALLOC
#define XMALLOC(s, h, type) ((void *)NetSecure_BlkGet((CPU_INT08U)(type), \
(CPU_SIZE_T)(s), (void *)0))
#define XFREE(p, h, type) (NetSecure_BlkFree((CPU_INT08U)(type), \
(p), (void *)0))
#define XREALLOC(p, n, h, t) realloc((p), (n))
#endif
#if (NET_SECURE_MGR_CFG_FS_EN == DEF_ENABLED)
#undef NO_FILESYSTEM
#else
#define NO_FILESYSTEM
#endif
#if (SSL_CFG_TRACE_LEVEL == CYASSL_TRACE_LEVEL_DBG)
#define DEBUG_CYASSL
#else
#undef DEBUG_CYASSL
#endif
#if (SSL_CFG_OPENSSL_EN == DEF_ENABLED)
#define OPENSSL_EXTRA
#else
#undef OPENSSL_EXTRA
#endif
#if (SSL_CFG_MULTI_THREAD_EN == DEF_ENABLED)
#undef SINGLE_THREADED
#else
#define SINGLE_THREADED
#endif
#if (SSL_CFG_DH_EN == DEF_ENABLED)
#undef NO_DH
#else
#define NO_DH
#endif
#if (SSL_CFG_DSA_EN == DEF_ENABLED)
#undef NO_DSA
#else
#define NO_DSA
#endif
#if (SSL_CFG_PSK_EN == DEF_ENABLED)
#undef NO_PSK
#else
#define NO_PSK
#endif
#if (SSL_CFG_3DES_EN == DEF_ENABLED)
#undef NO_DES
#else
#define NO_DES
#endif
#if (SSL_CFG_AES_EN == DEF_ENABLED)
#undef NO_AES
#else
#define NO_AES
#endif
#if (SSL_CFG_RC4_EN == DEF_ENABLED)
#undef NO_RC4
#else
#define NO_RC4
#endif
#if (SSL_CFG_RABBIT_EN == DEF_ENABLED)
#undef NO_RABBIT
#else
#define NO_RABBIT
#endif
#if (SSL_CFG_HC128_EN == DEF_ENABLED)
#undef NO_HC128
#else
#define NO_HC128
#endif
#if (CPU_CFG_ENDIAN_TYPE == CPU_ENDIAN_TYPE_BIG)
#define BIG_ENDIAN_ORDER
#else
#undef BIG_ENDIAN_ORDER
#define LITTLE_ENDIAN_ORDER
#endif
#if (SSL_CFG_MD4_EN == DEF_ENABLED)
#undef NO_MD4
#else
#define NO_MD4
#endif
#if (SSL_CFG_WRITEV_EN == DEF_ENABLED)
#undef NO_WRITEV
#else
#define NO_WRITEV
#endif
#if (SSL_CFG_USER_RNG_SEED_EN == DEF_ENABLED)
#define NO_DEV_RANDOM
#else
#undef NO_DEV_RANDOM
#endif
#if (SSL_CFG_USER_IO_EN == DEF_ENABLED)
#define CYASSL_USER_IO
#else
#undef CYASSL_USER_IO
#endif
#if (SSL_CFG_DYNAMIC_BUFFERS_EN == DEF_ENABLED)
#undef LARGE_STATIC_BUFFERS
#undef STATIC_CHUNKS_ONLY
#else
#define LARGE_STATIC_BUFFERS
#define STATIC_CHUNKS_ONLY
#endif
#if (SSL_CFG_DER_LOAD_EN == DEF_ENABLED)
#define CYASSL_DER_LOAD
#else
#undef CYASSL_DER_LOAD
#endif
#if (SSL_CFG_DTLS_EN == DEF_ENABLED)
#define CYASSL_DTLS
#else
#undef CYASSL_DTLS
#endif
#if (SSL_CFG_CALLBACKS_EN == DEF_ENABLED)
#define CYASSL_CALLBACKS
#else
#undef CYASSL_CALLBACKS
#endif
#if (SSL_CFG_FAST_MATH_EN == DEF_ENABLED)
#define USE_FAST_MATH
#else
#undef USE_FAST_MATH
#endif
#if (SSL_CFG_TFM_TIMING_RESISTANT_EN == DEF_ENABLED)
#define TFM_TIMING_RESISTANT
#else
#undef TFM_TIMING_RESISTANT
#endif
#endif /* MICRIUM */
#ifdef CYASSL_QL
#ifndef CYASSL_SEP
#define CYASSL_SEP
#endif
#ifndef OPENSSL_EXTRA
#define OPENSSL_EXTRA
#endif
#ifndef SESSION_CERTS
#define SESSION_CERTS
#endif
#ifndef HAVE_AESCCM
#define HAVE_AESCCM
#endif
#ifndef ATOMIC_USER
#define ATOMIC_USER
#endif
#ifndef CYASSL_DER_LOAD
#define CYASSL_DER_LOAD
#endif
#ifndef KEEP_PEER_CERT
#define KEEP_PEER_CERT
#endif
#ifndef HAVE_ECC
#define HAVE_ECC
#endif
#ifndef SESSION_INDEX
#define SESSION_INDEX
#endif
#endif /* CYASSL_QL */
#if !defined(XMALLOC_USER) && !defined(MICRIUM_MALLOC) && \
!defined(CYASSL_LEANPSK) && !defined(NO_CYASSL_MEMORY)
#define USE_CYASSL_MEMORY
#endif
#if defined(OPENSSL_EXTRA) && !defined(NO_CERTS)
#undef KEEP_PEER_CERT
#define KEEP_PEER_CERT
#endif
/* stream ciphers except arc4 need 32bit alignment, intel ok without */
#ifndef XSTREAM_ALIGNMENT
#if defined(__x86_64__) || defined(__ia64__) || defined(__i386__)
#define NO_XSTREAM_ALIGNMENT
#else
#define XSTREAM_ALIGNMENT
#endif
#endif
/* if using hardware crypto and have alignment requirements, specify the
requirement here. The record header of SSL/TLS will prvent easy alignment.
This hint tries to help as much as possible. */
#ifndef CYASSL_GENERAL_ALIGNMENT
#ifdef CYASSL_AESNI
#define CYASSL_GENERAL_ALIGNMENT 16
#elif defined(XSTREAM_ALIGNMENT)
#define CYASSL_GENERAL_ALIGNMENT 4
#else
#define CYASSL_GENERAL_ALIGNMENT 0
#endif
#endif
#ifdef HAVE_CRL
/* not widely supported yet */
#undef NO_SKID
#define NO_SKID
#endif
/* Place any other flags or defines here */
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* CTAO_CRYPT_SETTINGS_H */

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/******************************************************************************/
/* STM32_SWO.ini: STM32 Debugger Initialization File */
/******************************************************************************/
// <<< Use Configuration Wizard in Context Menu >>> //
/******************************************************************************/
/* This file is part of the uVision/ARM development tools. */
/* Copyright (c) 2004-2013 Keil Software. All rights reserved. */
/* This software may only be used under the terms of a valid, current, */
/* end user licence from KEIL for a compatible version of KEIL software */
/* development tools. Nothing else gives you the right to use this software. */
/******************************************************************************/
FUNC void DebugSetup (void) {
// <h> Debug MCU Configuration
// <o1.0> DBG_SLEEP <i> Debug Sleep Mode
// <o1.1> DBG_STOP <i> Debug Stop Mode
// <o1.2> DBG_STANDBY <i> Debug Standby Mode
// <o1.5> TRACE_IOEN <i> Trace I/O Enable
// <o1.6..7> TRACE_MODE <i> Trace Mode
// <0=> Asynchronous
// <1=> Synchronous: TRACEDATA Size 1
// <2=> Synchronous: TRACEDATA Size 2
// <3=> Synchronous: TRACEDATA Size 4
// <o1.8> DBG_IWDG_STOP <i> Independant Watchdog Stopped when Core is halted
// <o1.9> DBG_WWDG_STOP <i> Window Watchdog Stopped when Core is halted
// <o1.10> DBG_TIM1_STOP <i> Timer 1 Stopped when Core is halted
// <o1.11> DBG_TIM2_STOP <i> Timer 2 Stopped when Core is halted
// <o1.12> DBG_TIM3_STOP <i> Timer 3 Stopped when Core is halted
// <o1.13> DBG_TIM4_STOP <i> Timer 4 Stopped when Core is halted
// <o1.14> DBG_CAN_STOP <i> CAN Stopped when Core is halted
// </h>
_WDWORD(0xE0042004, 0x00000027); // DBGMCU_CR
}
DebugSetup(); // Debugger Setup

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