1378 lines
78 KiB
C
1378 lines
78 KiB
C
/* Autogen header for Unicorn Engine - DONOT MODIFY */
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#ifndef UNICORN_AUTOGEN_riscv64_H
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#define UNICORN_AUTOGEN_riscv64_H
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#ifndef UNICORN_ARCH_POSTFIX
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#define UNICORN_ARCH_POSTFIX _riscv64
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#endif
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#define uc_add_inline_hook uc_add_inline_hook_riscv64
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#define uc_del_inline_hook uc_del_inline_hook_riscv64
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#define tb_invalidate_phys_range tb_invalidate_phys_range_riscv64
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#define use_idiv_instructions use_idiv_instructions_riscv64
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#define arm_arch arm_arch_riscv64
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#define tb_target_set_jmp_target tb_target_set_jmp_target_riscv64
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#define have_bmi1 have_bmi1_riscv64
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#define have_popcnt have_popcnt_riscv64
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#define have_avx1 have_avx1_riscv64
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#define have_avx2 have_avx2_riscv64
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#define have_isa have_isa_riscv64
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#define have_altivec have_altivec_riscv64
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#define have_vsx have_vsx_riscv64
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#define flush_icache_range flush_icache_range_riscv64
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#define s390_facilities s390_facilities_riscv64
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#define tcg_dump_op tcg_dump_op_riscv64
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#define tcg_dump_ops tcg_dump_ops_riscv64
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#define tcg_gen_and_i64 tcg_gen_and_i64_riscv64
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#define tcg_gen_discard_i64 tcg_gen_discard_i64_riscv64
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#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_riscv64
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#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_riscv64
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#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_riscv64
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#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_riscv64
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#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_riscv64
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#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_riscv64
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#define tcg_gen_ld_i64 tcg_gen_ld_i64_riscv64
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#define tcg_gen_mov_i64 tcg_gen_mov_i64_riscv64
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#define tcg_gen_movi_i64 tcg_gen_movi_i64_riscv64
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#define tcg_gen_mul_i64 tcg_gen_mul_i64_riscv64
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#define tcg_gen_or_i64 tcg_gen_or_i64_riscv64
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#define tcg_gen_sar_i64 tcg_gen_sar_i64_riscv64
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#define tcg_gen_shl_i64 tcg_gen_shl_i64_riscv64
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#define tcg_gen_shr_i64 tcg_gen_shr_i64_riscv64
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#define tcg_gen_st_i64 tcg_gen_st_i64_riscv64
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#define tcg_gen_xor_i64 tcg_gen_xor_i64_riscv64
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#define cpu_icount_to_ns cpu_icount_to_ns_riscv64
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#define cpu_is_stopped cpu_is_stopped_riscv64
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#define cpu_get_ticks cpu_get_ticks_riscv64
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#define cpu_get_clock cpu_get_clock_riscv64
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#define cpu_resume cpu_resume_riscv64
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#define qemu_init_vcpu qemu_init_vcpu_riscv64
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#define cpu_stop_current cpu_stop_current_riscv64
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#define resume_all_vcpus resume_all_vcpus_riscv64
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#define vm_start vm_start_riscv64
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#define address_space_dispatch_compact address_space_dispatch_compact_riscv64
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#define flatview_translate flatview_translate_riscv64
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#define address_space_translate_for_iotlb address_space_translate_for_iotlb_riscv64
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#define qemu_get_cpu qemu_get_cpu_riscv64
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#define cpu_address_space_init cpu_address_space_init_riscv64
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#define cpu_get_address_space cpu_get_address_space_riscv64
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#define cpu_exec_unrealizefn cpu_exec_unrealizefn_riscv64
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#define cpu_exec_initfn cpu_exec_initfn_riscv64
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#define cpu_exec_realizefn cpu_exec_realizefn_riscv64
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#define tb_invalidate_phys_addr tb_invalidate_phys_addr_riscv64
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#define cpu_watchpoint_insert cpu_watchpoint_insert_riscv64
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#define cpu_watchpoint_remove_by_ref cpu_watchpoint_remove_by_ref_riscv64
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#define cpu_watchpoint_remove_all cpu_watchpoint_remove_all_riscv64
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#define cpu_watchpoint_address_matches cpu_watchpoint_address_matches_riscv64
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#define cpu_breakpoint_insert cpu_breakpoint_insert_riscv64
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#define cpu_breakpoint_remove cpu_breakpoint_remove_riscv64
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#define cpu_breakpoint_remove_by_ref cpu_breakpoint_remove_by_ref_riscv64
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#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_riscv64
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#define cpu_abort cpu_abort_riscv64
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#define cpu_physical_memory_test_and_clear_dirty cpu_physical_memory_test_and_clear_dirty_riscv64
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#define memory_region_section_get_iotlb memory_region_section_get_iotlb_riscv64
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#define flatview_add_to_dispatch flatview_add_to_dispatch_riscv64
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#define qemu_ram_get_host_addr qemu_ram_get_host_addr_riscv64
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#define qemu_ram_get_offset qemu_ram_get_offset_riscv64
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#define qemu_ram_get_used_length qemu_ram_get_used_length_riscv64
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#define qemu_ram_is_shared qemu_ram_is_shared_riscv64
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#define qemu_ram_pagesize qemu_ram_pagesize_riscv64
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#define qemu_ram_alloc_from_ptr qemu_ram_alloc_from_ptr_riscv64
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#define qemu_ram_alloc qemu_ram_alloc_riscv64
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#define qemu_ram_free qemu_ram_free_riscv64
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#define qemu_map_ram_ptr qemu_map_ram_ptr_riscv64
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#define qemu_ram_block_host_offset qemu_ram_block_host_offset_riscv64
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#define qemu_ram_block_from_host qemu_ram_block_from_host_riscv64
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#define qemu_ram_addr_from_host qemu_ram_addr_from_host_riscv64
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#define cpu_check_watchpoint cpu_check_watchpoint_riscv64
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#define iotlb_to_section iotlb_to_section_riscv64
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#define address_space_dispatch_new address_space_dispatch_new_riscv64
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#define address_space_dispatch_free address_space_dispatch_free_riscv64
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#define flatview_read_continue flatview_read_continue_riscv64
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#define address_space_read_full address_space_read_full_riscv64
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#define address_space_write address_space_write_riscv64
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#define address_space_rw address_space_rw_riscv64
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#define cpu_physical_memory_rw cpu_physical_memory_rw_riscv64
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#define address_space_write_rom address_space_write_rom_riscv64
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#define cpu_flush_icache_range cpu_flush_icache_range_riscv64
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#define cpu_exec_init_all cpu_exec_init_all_riscv64
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#define address_space_access_valid address_space_access_valid_riscv64
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#define address_space_map address_space_map_riscv64
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#define address_space_unmap address_space_unmap_riscv64
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#define cpu_physical_memory_map cpu_physical_memory_map_riscv64
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#define cpu_physical_memory_unmap cpu_physical_memory_unmap_riscv64
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#define cpu_memory_rw_debug cpu_memory_rw_debug_riscv64
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#define qemu_target_page_size qemu_target_page_size_riscv64
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#define qemu_target_page_bits qemu_target_page_bits_riscv64
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#define qemu_target_page_bits_min qemu_target_page_bits_min_riscv64
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#define target_words_bigendian target_words_bigendian_riscv64
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#define cpu_physical_memory_is_io cpu_physical_memory_is_io_riscv64
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#define ram_block_discard_range ram_block_discard_range_riscv64
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#define ramblock_is_pmem ramblock_is_pmem_riscv64
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#define page_size_init page_size_init_riscv64
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#define set_preferred_target_page_bits set_preferred_target_page_bits_riscv64
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#define finalize_target_page_bits finalize_target_page_bits_riscv64
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#define cpu_outb cpu_outb_riscv64
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#define cpu_outw cpu_outw_riscv64
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#define cpu_outl cpu_outl_riscv64
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#define cpu_inb cpu_inb_riscv64
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#define cpu_inw cpu_inw_riscv64
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#define cpu_inl cpu_inl_riscv64
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#define memory_map memory_map_riscv64
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#define memory_map_io memory_map_io_riscv64
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#define memory_map_ptr memory_map_ptr_riscv64
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#define memory_unmap memory_unmap_riscv64
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#define memory_free memory_free_riscv64
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#define flatview_unref flatview_unref_riscv64
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#define address_space_get_flatview address_space_get_flatview_riscv64
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#define memory_region_transaction_begin memory_region_transaction_begin_riscv64
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#define memory_region_transaction_commit memory_region_transaction_commit_riscv64
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#define memory_region_init memory_region_init_riscv64
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#define memory_region_access_valid memory_region_access_valid_riscv64
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#define memory_region_dispatch_read memory_region_dispatch_read_riscv64
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#define memory_region_dispatch_write memory_region_dispatch_write_riscv64
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#define memory_region_init_io memory_region_init_io_riscv64
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#define memory_region_init_ram_ptr memory_region_init_ram_ptr_riscv64
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#define memory_region_size memory_region_size_riscv64
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#define memory_region_set_readonly memory_region_set_readonly_riscv64
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#define memory_region_get_ram_ptr memory_region_get_ram_ptr_riscv64
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#define memory_region_from_host memory_region_from_host_riscv64
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#define memory_region_get_ram_addr memory_region_get_ram_addr_riscv64
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#define memory_region_add_subregion memory_region_add_subregion_riscv64
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#define memory_region_del_subregion memory_region_del_subregion_riscv64
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#define memory_region_find memory_region_find_riscv64
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#define memory_listener_register memory_listener_register_riscv64
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#define memory_listener_unregister memory_listener_unregister_riscv64
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#define address_space_remove_listeners address_space_remove_listeners_riscv64
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#define address_space_init address_space_init_riscv64
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#define address_space_destroy address_space_destroy_riscv64
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#define memory_region_init_ram memory_region_init_ram_riscv64
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#define memory_mapping_list_add_merge_sorted memory_mapping_list_add_merge_sorted_riscv64
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#define exec_inline_op exec_inline_op_riscv64
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#define floatx80_default_nan floatx80_default_nan_riscv64
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#define float_raise float_raise_riscv64
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#define float16_is_quiet_nan float16_is_quiet_nan_riscv64
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#define float16_is_signaling_nan float16_is_signaling_nan_riscv64
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#define float32_is_quiet_nan float32_is_quiet_nan_riscv64
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#define float32_is_signaling_nan float32_is_signaling_nan_riscv64
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#define float64_is_quiet_nan float64_is_quiet_nan_riscv64
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#define float64_is_signaling_nan float64_is_signaling_nan_riscv64
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#define floatx80_is_quiet_nan floatx80_is_quiet_nan_riscv64
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#define floatx80_is_signaling_nan floatx80_is_signaling_nan_riscv64
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#define floatx80_silence_nan floatx80_silence_nan_riscv64
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#define propagateFloatx80NaN propagateFloatx80NaN_riscv64
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#define float128_is_quiet_nan float128_is_quiet_nan_riscv64
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#define float128_is_signaling_nan float128_is_signaling_nan_riscv64
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#define float128_silence_nan float128_silence_nan_riscv64
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#define float16_add float16_add_riscv64
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#define float16_sub float16_sub_riscv64
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#define float32_add float32_add_riscv64
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#define float32_sub float32_sub_riscv64
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#define float64_add float64_add_riscv64
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#define float64_sub float64_sub_riscv64
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#define float16_mul float16_mul_riscv64
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#define float32_mul float32_mul_riscv64
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#define float64_mul float64_mul_riscv64
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#define float16_muladd float16_muladd_riscv64
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#define float32_muladd float32_muladd_riscv64
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#define float64_muladd float64_muladd_riscv64
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#define float16_div float16_div_riscv64
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#define float32_div float32_div_riscv64
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#define float64_div float64_div_riscv64
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#define float16_to_float32 float16_to_float32_riscv64
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#define float16_to_float64 float16_to_float64_riscv64
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#define float32_to_float16 float32_to_float16_riscv64
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#define float32_to_float64 float32_to_float64_riscv64
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#define float64_to_float16 float64_to_float16_riscv64
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#define float64_to_float32 float64_to_float32_riscv64
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#define float16_round_to_int float16_round_to_int_riscv64
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#define float32_round_to_int float32_round_to_int_riscv64
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#define float64_round_to_int float64_round_to_int_riscv64
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#define float16_to_int16_scalbn float16_to_int16_scalbn_riscv64
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#define float16_to_int32_scalbn float16_to_int32_scalbn_riscv64
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#define float16_to_int64_scalbn float16_to_int64_scalbn_riscv64
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#define float32_to_int16_scalbn float32_to_int16_scalbn_riscv64
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#define float32_to_int32_scalbn float32_to_int32_scalbn_riscv64
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#define float32_to_int64_scalbn float32_to_int64_scalbn_riscv64
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#define float64_to_int16_scalbn float64_to_int16_scalbn_riscv64
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#define float64_to_int32_scalbn float64_to_int32_scalbn_riscv64
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#define float64_to_int64_scalbn float64_to_int64_scalbn_riscv64
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#define float16_to_int16 float16_to_int16_riscv64
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#define float16_to_int32 float16_to_int32_riscv64
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#define float16_to_int64 float16_to_int64_riscv64
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#define float32_to_int16 float32_to_int16_riscv64
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#define float32_to_int32 float32_to_int32_riscv64
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#define float32_to_int64 float32_to_int64_riscv64
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#define float64_to_int16 float64_to_int16_riscv64
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#define float64_to_int32 float64_to_int32_riscv64
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#define float64_to_int64 float64_to_int64_riscv64
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#define float16_to_int16_round_to_zero float16_to_int16_round_to_zero_riscv64
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#define float16_to_int32_round_to_zero float16_to_int32_round_to_zero_riscv64
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#define float16_to_int64_round_to_zero float16_to_int64_round_to_zero_riscv64
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#define float32_to_int16_round_to_zero float32_to_int16_round_to_zero_riscv64
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#define float32_to_int32_round_to_zero float32_to_int32_round_to_zero_riscv64
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#define float32_to_int64_round_to_zero float32_to_int64_round_to_zero_riscv64
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#define float64_to_int16_round_to_zero float64_to_int16_round_to_zero_riscv64
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#define float64_to_int32_round_to_zero float64_to_int32_round_to_zero_riscv64
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#define float64_to_int64_round_to_zero float64_to_int64_round_to_zero_riscv64
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#define float16_to_uint16_scalbn float16_to_uint16_scalbn_riscv64
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#define float16_to_uint32_scalbn float16_to_uint32_scalbn_riscv64
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#define float16_to_uint64_scalbn float16_to_uint64_scalbn_riscv64
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#define float32_to_uint16_scalbn float32_to_uint16_scalbn_riscv64
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#define float32_to_uint32_scalbn float32_to_uint32_scalbn_riscv64
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#define float32_to_uint64_scalbn float32_to_uint64_scalbn_riscv64
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#define float64_to_uint16_scalbn float64_to_uint16_scalbn_riscv64
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#define float64_to_uint32_scalbn float64_to_uint32_scalbn_riscv64
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#define float64_to_uint64_scalbn float64_to_uint64_scalbn_riscv64
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#define float16_to_uint16 float16_to_uint16_riscv64
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#define float16_to_uint32 float16_to_uint32_riscv64
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#define float16_to_uint64 float16_to_uint64_riscv64
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#define float32_to_uint16 float32_to_uint16_riscv64
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#define float32_to_uint32 float32_to_uint32_riscv64
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#define float32_to_uint64 float32_to_uint64_riscv64
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#define float64_to_uint16 float64_to_uint16_riscv64
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#define float64_to_uint32 float64_to_uint32_riscv64
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#define float64_to_uint64 float64_to_uint64_riscv64
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#define float16_to_uint16_round_to_zero float16_to_uint16_round_to_zero_riscv64
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#define float16_to_uint32_round_to_zero float16_to_uint32_round_to_zero_riscv64
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#define float16_to_uint64_round_to_zero float16_to_uint64_round_to_zero_riscv64
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#define float32_to_uint16_round_to_zero float32_to_uint16_round_to_zero_riscv64
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#define float32_to_uint32_round_to_zero float32_to_uint32_round_to_zero_riscv64
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#define float32_to_uint64_round_to_zero float32_to_uint64_round_to_zero_riscv64
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#define float64_to_uint16_round_to_zero float64_to_uint16_round_to_zero_riscv64
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#define float64_to_uint32_round_to_zero float64_to_uint32_round_to_zero_riscv64
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#define float64_to_uint64_round_to_zero float64_to_uint64_round_to_zero_riscv64
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#define int64_to_float16_scalbn int64_to_float16_scalbn_riscv64
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#define int32_to_float16_scalbn int32_to_float16_scalbn_riscv64
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#define int16_to_float16_scalbn int16_to_float16_scalbn_riscv64
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#define int64_to_float16 int64_to_float16_riscv64
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#define int32_to_float16 int32_to_float16_riscv64
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#define int16_to_float16 int16_to_float16_riscv64
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#define int64_to_float32_scalbn int64_to_float32_scalbn_riscv64
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#define int32_to_float32_scalbn int32_to_float32_scalbn_riscv64
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#define int16_to_float32_scalbn int16_to_float32_scalbn_riscv64
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#define int64_to_float32 int64_to_float32_riscv64
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#define int32_to_float32 int32_to_float32_riscv64
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#define int16_to_float32 int16_to_float32_riscv64
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#define int64_to_float64_scalbn int64_to_float64_scalbn_riscv64
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#define int32_to_float64_scalbn int32_to_float64_scalbn_riscv64
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#define int16_to_float64_scalbn int16_to_float64_scalbn_riscv64
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#define int64_to_float64 int64_to_float64_riscv64
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#define int32_to_float64 int32_to_float64_riscv64
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#define int16_to_float64 int16_to_float64_riscv64
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#define uint64_to_float16_scalbn uint64_to_float16_scalbn_riscv64
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#define uint32_to_float16_scalbn uint32_to_float16_scalbn_riscv64
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#define uint16_to_float16_scalbn uint16_to_float16_scalbn_riscv64
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#define uint64_to_float16 uint64_to_float16_riscv64
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#define uint32_to_float16 uint32_to_float16_riscv64
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#define uint16_to_float16 uint16_to_float16_riscv64
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#define uint64_to_float32_scalbn uint64_to_float32_scalbn_riscv64
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#define uint32_to_float32_scalbn uint32_to_float32_scalbn_riscv64
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#define uint16_to_float32_scalbn uint16_to_float32_scalbn_riscv64
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#define uint64_to_float32 uint64_to_float32_riscv64
|
|
#define uint32_to_float32 uint32_to_float32_riscv64
|
|
#define uint16_to_float32 uint16_to_float32_riscv64
|
|
#define uint64_to_float64_scalbn uint64_to_float64_scalbn_riscv64
|
|
#define uint32_to_float64_scalbn uint32_to_float64_scalbn_riscv64
|
|
#define uint16_to_float64_scalbn uint16_to_float64_scalbn_riscv64
|
|
#define uint64_to_float64 uint64_to_float64_riscv64
|
|
#define uint32_to_float64 uint32_to_float64_riscv64
|
|
#define uint16_to_float64 uint16_to_float64_riscv64
|
|
#define float16_min float16_min_riscv64
|
|
#define float16_minnum float16_minnum_riscv64
|
|
#define float16_minnummag float16_minnummag_riscv64
|
|
#define float16_max float16_max_riscv64
|
|
#define float16_maxnum float16_maxnum_riscv64
|
|
#define float16_maxnummag float16_maxnummag_riscv64
|
|
#define float32_min float32_min_riscv64
|
|
#define float32_minnum float32_minnum_riscv64
|
|
#define float32_minnummag float32_minnummag_riscv64
|
|
#define float32_max float32_max_riscv64
|
|
#define float32_maxnum float32_maxnum_riscv64
|
|
#define float32_maxnummag float32_maxnummag_riscv64
|
|
#define float64_min float64_min_riscv64
|
|
#define float64_minnum float64_minnum_riscv64
|
|
#define float64_minnummag float64_minnummag_riscv64
|
|
#define float64_max float64_max_riscv64
|
|
#define float64_maxnum float64_maxnum_riscv64
|
|
#define float64_maxnummag float64_maxnummag_riscv64
|
|
#define float16_compare float16_compare_riscv64
|
|
#define float16_compare_quiet float16_compare_quiet_riscv64
|
|
#define float32_compare float32_compare_riscv64
|
|
#define float32_compare_quiet float32_compare_quiet_riscv64
|
|
#define float64_compare float64_compare_riscv64
|
|
#define float64_compare_quiet float64_compare_quiet_riscv64
|
|
#define float16_scalbn float16_scalbn_riscv64
|
|
#define float32_scalbn float32_scalbn_riscv64
|
|
#define float64_scalbn float64_scalbn_riscv64
|
|
#define float16_sqrt float16_sqrt_riscv64
|
|
#define float32_sqrt float32_sqrt_riscv64
|
|
#define float64_sqrt float64_sqrt_riscv64
|
|
#define float16_default_nan float16_default_nan_riscv64
|
|
#define float32_default_nan float32_default_nan_riscv64
|
|
#define float64_default_nan float64_default_nan_riscv64
|
|
#define float128_default_nan float128_default_nan_riscv64
|
|
#define float16_silence_nan float16_silence_nan_riscv64
|
|
#define float32_silence_nan float32_silence_nan_riscv64
|
|
#define float64_silence_nan float64_silence_nan_riscv64
|
|
#define float16_squash_input_denormal float16_squash_input_denormal_riscv64
|
|
#define float32_squash_input_denormal float32_squash_input_denormal_riscv64
|
|
#define float64_squash_input_denormal float64_squash_input_denormal_riscv64
|
|
#define normalizeFloatx80Subnormal normalizeFloatx80Subnormal_riscv64
|
|
#define roundAndPackFloatx80 roundAndPackFloatx80_riscv64
|
|
#define normalizeRoundAndPackFloatx80 normalizeRoundAndPackFloatx80_riscv64
|
|
#define int32_to_floatx80 int32_to_floatx80_riscv64
|
|
#define int32_to_float128 int32_to_float128_riscv64
|
|
#define int64_to_floatx80 int64_to_floatx80_riscv64
|
|
#define int64_to_float128 int64_to_float128_riscv64
|
|
#define uint64_to_float128 uint64_to_float128_riscv64
|
|
#define float32_to_floatx80 float32_to_floatx80_riscv64
|
|
#define float32_to_float128 float32_to_float128_riscv64
|
|
#define float32_rem float32_rem_riscv64
|
|
#define float32_exp2 float32_exp2_riscv64
|
|
#define float32_log2 float32_log2_riscv64
|
|
#define float32_eq float32_eq_riscv64
|
|
#define float32_le float32_le_riscv64
|
|
#define float32_lt float32_lt_riscv64
|
|
#define float32_unordered float32_unordered_riscv64
|
|
#define float32_eq_quiet float32_eq_quiet_riscv64
|
|
#define float32_le_quiet float32_le_quiet_riscv64
|
|
#define float32_lt_quiet float32_lt_quiet_riscv64
|
|
#define float32_unordered_quiet float32_unordered_quiet_riscv64
|
|
#define float64_to_floatx80 float64_to_floatx80_riscv64
|
|
#define float64_to_float128 float64_to_float128_riscv64
|
|
#define float64_rem float64_rem_riscv64
|
|
#define float64_log2 float64_log2_riscv64
|
|
#define float64_eq float64_eq_riscv64
|
|
#define float64_le float64_le_riscv64
|
|
#define float64_lt float64_lt_riscv64
|
|
#define float64_unordered float64_unordered_riscv64
|
|
#define float64_eq_quiet float64_eq_quiet_riscv64
|
|
#define float64_le_quiet float64_le_quiet_riscv64
|
|
#define float64_lt_quiet float64_lt_quiet_riscv64
|
|
#define float64_unordered_quiet float64_unordered_quiet_riscv64
|
|
#define floatx80_to_int32 floatx80_to_int32_riscv64
|
|
#define floatx80_to_int32_round_to_zero floatx80_to_int32_round_to_zero_riscv64
|
|
#define floatx80_to_int64 floatx80_to_int64_riscv64
|
|
#define floatx80_to_int64_round_to_zero floatx80_to_int64_round_to_zero_riscv64
|
|
#define floatx80_to_float32 floatx80_to_float32_riscv64
|
|
#define floatx80_to_float64 floatx80_to_float64_riscv64
|
|
#define floatx80_to_float128 floatx80_to_float128_riscv64
|
|
#define floatx80_round floatx80_round_riscv64
|
|
#define floatx80_round_to_int floatx80_round_to_int_riscv64
|
|
#define floatx80_add floatx80_add_riscv64
|
|
#define floatx80_sub floatx80_sub_riscv64
|
|
#define floatx80_mul floatx80_mul_riscv64
|
|
#define floatx80_div floatx80_div_riscv64
|
|
#define floatx80_rem floatx80_rem_riscv64
|
|
#define floatx80_sqrt floatx80_sqrt_riscv64
|
|
#define floatx80_eq floatx80_eq_riscv64
|
|
#define floatx80_le floatx80_le_riscv64
|
|
#define floatx80_lt floatx80_lt_riscv64
|
|
#define floatx80_unordered floatx80_unordered_riscv64
|
|
#define floatx80_eq_quiet floatx80_eq_quiet_riscv64
|
|
#define floatx80_le_quiet floatx80_le_quiet_riscv64
|
|
#define floatx80_lt_quiet floatx80_lt_quiet_riscv64
|
|
#define floatx80_unordered_quiet floatx80_unordered_quiet_riscv64
|
|
#define float128_to_int32 float128_to_int32_riscv64
|
|
#define float128_to_int32_round_to_zero float128_to_int32_round_to_zero_riscv64
|
|
#define float128_to_int64 float128_to_int64_riscv64
|
|
#define float128_to_int64_round_to_zero float128_to_int64_round_to_zero_riscv64
|
|
#define float128_to_uint64 float128_to_uint64_riscv64
|
|
#define float128_to_uint64_round_to_zero float128_to_uint64_round_to_zero_riscv64
|
|
#define float128_to_uint32_round_to_zero float128_to_uint32_round_to_zero_riscv64
|
|
#define float128_to_uint32 float128_to_uint32_riscv64
|
|
#define float128_to_float32 float128_to_float32_riscv64
|
|
#define float128_to_float64 float128_to_float64_riscv64
|
|
#define float128_to_floatx80 float128_to_floatx80_riscv64
|
|
#define float128_round_to_int float128_round_to_int_riscv64
|
|
#define float128_add float128_add_riscv64
|
|
#define float128_sub float128_sub_riscv64
|
|
#define float128_mul float128_mul_riscv64
|
|
#define float128_div float128_div_riscv64
|
|
#define float128_rem float128_rem_riscv64
|
|
#define float128_sqrt float128_sqrt_riscv64
|
|
#define float128_eq float128_eq_riscv64
|
|
#define float128_le float128_le_riscv64
|
|
#define float128_lt float128_lt_riscv64
|
|
#define float128_unordered float128_unordered_riscv64
|
|
#define float128_eq_quiet float128_eq_quiet_riscv64
|
|
#define float128_le_quiet float128_le_quiet_riscv64
|
|
#define float128_lt_quiet float128_lt_quiet_riscv64
|
|
#define float128_unordered_quiet float128_unordered_quiet_riscv64
|
|
#define floatx80_compare floatx80_compare_riscv64
|
|
#define floatx80_compare_quiet floatx80_compare_quiet_riscv64
|
|
#define float128_compare float128_compare_riscv64
|
|
#define float128_compare_quiet float128_compare_quiet_riscv64
|
|
#define floatx80_scalbn floatx80_scalbn_riscv64
|
|
#define float128_scalbn float128_scalbn_riscv64
|
|
#define softfloat_init softfloat_init_riscv64
|
|
#define tcg_optimize tcg_optimize_riscv64
|
|
#define gen_new_label gen_new_label_riscv64
|
|
#define tcg_can_emit_vec_op tcg_can_emit_vec_op_riscv64
|
|
#define tcg_expand_vec_op tcg_expand_vec_op_riscv64
|
|
#define tcg_register_jit tcg_register_jit_riscv64
|
|
#define tcg_tb_insert tcg_tb_insert_riscv64
|
|
#define tcg_tb_remove tcg_tb_remove_riscv64
|
|
#define tcg_tb_lookup tcg_tb_lookup_riscv64
|
|
#define tcg_tb_foreach tcg_tb_foreach_riscv64
|
|
#define tcg_nb_tbs tcg_nb_tbs_riscv64
|
|
#define tcg_region_reset_all tcg_region_reset_all_riscv64
|
|
#define tcg_region_init tcg_region_init_riscv64
|
|
#define tcg_code_size tcg_code_size_riscv64
|
|
#define tcg_code_capacity tcg_code_capacity_riscv64
|
|
#define tcg_tb_phys_invalidate_count tcg_tb_phys_invalidate_count_riscv64
|
|
#define tcg_malloc_internal tcg_malloc_internal_riscv64
|
|
#define tcg_pool_reset tcg_pool_reset_riscv64
|
|
#define tcg_context_init tcg_context_init_riscv64
|
|
#define tcg_tb_alloc tcg_tb_alloc_riscv64
|
|
#define tcg_prologue_init tcg_prologue_init_riscv64
|
|
#define tcg_func_start tcg_func_start_riscv64
|
|
#define tcg_set_frame tcg_set_frame_riscv64
|
|
#define tcg_global_mem_new_internal tcg_global_mem_new_internal_riscv64
|
|
#define tcg_temp_new_internal tcg_temp_new_internal_riscv64
|
|
#define tcg_temp_new_vec tcg_temp_new_vec_riscv64
|
|
#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_riscv64
|
|
#define tcg_temp_free_internal tcg_temp_free_internal_riscv64
|
|
#define tcg_const_i32 tcg_const_i32_riscv64
|
|
#define tcg_const_i64 tcg_const_i64_riscv64
|
|
#define tcg_const_local_i32 tcg_const_local_i32_riscv64
|
|
#define tcg_const_local_i64 tcg_const_local_i64_riscv64
|
|
#define tcg_op_supported tcg_op_supported_riscv64
|
|
#define tcg_gen_callN tcg_gen_callN_riscv64
|
|
#define tcg_op_remove tcg_op_remove_riscv64
|
|
#define tcg_emit_op tcg_emit_op_riscv64
|
|
#define tcg_op_insert_before tcg_op_insert_before_riscv64
|
|
#define tcg_op_insert_after tcg_op_insert_after_riscv64
|
|
#define tcg_cpu_exec_time tcg_cpu_exec_time_riscv64
|
|
#define tcg_gen_code tcg_gen_code_riscv64
|
|
#define tcg_gen_op1 tcg_gen_op1_riscv64
|
|
#define tcg_gen_op2 tcg_gen_op2_riscv64
|
|
#define tcg_gen_op3 tcg_gen_op3_riscv64
|
|
#define tcg_gen_op4 tcg_gen_op4_riscv64
|
|
#define tcg_gen_op5 tcg_gen_op5_riscv64
|
|
#define tcg_gen_op6 tcg_gen_op6_riscv64
|
|
#define tcg_gen_mb tcg_gen_mb_riscv64
|
|
#define tcg_gen_addi_i32 tcg_gen_addi_i32_riscv64
|
|
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_riscv64
|
|
#define tcg_gen_subi_i32 tcg_gen_subi_i32_riscv64
|
|
#define tcg_gen_andi_i32 tcg_gen_andi_i32_riscv64
|
|
#define tcg_gen_ori_i32 tcg_gen_ori_i32_riscv64
|
|
#define tcg_gen_xori_i32 tcg_gen_xori_i32_riscv64
|
|
#define tcg_gen_shli_i32 tcg_gen_shli_i32_riscv64
|
|
#define tcg_gen_shri_i32 tcg_gen_shri_i32_riscv64
|
|
#define tcg_gen_sari_i32 tcg_gen_sari_i32_riscv64
|
|
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_riscv64
|
|
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_riscv64
|
|
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_riscv64
|
|
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_riscv64
|
|
#define tcg_gen_muli_i32 tcg_gen_muli_i32_riscv64
|
|
#define tcg_gen_div_i32 tcg_gen_div_i32_riscv64
|
|
#define tcg_gen_rem_i32 tcg_gen_rem_i32_riscv64
|
|
#define tcg_gen_divu_i32 tcg_gen_divu_i32_riscv64
|
|
#define tcg_gen_remu_i32 tcg_gen_remu_i32_riscv64
|
|
#define tcg_gen_andc_i32 tcg_gen_andc_i32_riscv64
|
|
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_riscv64
|
|
#define tcg_gen_nand_i32 tcg_gen_nand_i32_riscv64
|
|
#define tcg_gen_nor_i32 tcg_gen_nor_i32_riscv64
|
|
#define tcg_gen_orc_i32 tcg_gen_orc_i32_riscv64
|
|
#define tcg_gen_clz_i32 tcg_gen_clz_i32_riscv64
|
|
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_riscv64
|
|
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_riscv64
|
|
#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_riscv64
|
|
#define tcg_gen_clrsb_i32 tcg_gen_clrsb_i32_riscv64
|
|
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_riscv64
|
|
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_riscv64
|
|
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_riscv64
|
|
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_riscv64
|
|
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_riscv64
|
|
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_riscv64
|
|
#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_riscv64
|
|
#define tcg_gen_extract_i32 tcg_gen_extract_i32_riscv64
|
|
#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_riscv64
|
|
#define tcg_gen_extract2_i32 tcg_gen_extract2_i32_riscv64
|
|
#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_riscv64
|
|
#define tcg_gen_add2_i32 tcg_gen_add2_i32_riscv64
|
|
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_riscv64
|
|
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_riscv64
|
|
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_riscv64
|
|
#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_riscv64
|
|
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_riscv64
|
|
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_riscv64
|
|
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_riscv64
|
|
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_riscv64
|
|
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_riscv64
|
|
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_riscv64
|
|
#define tcg_gen_smin_i32 tcg_gen_smin_i32_riscv64
|
|
#define tcg_gen_umin_i32 tcg_gen_umin_i32_riscv64
|
|
#define tcg_gen_smax_i32 tcg_gen_smax_i32_riscv64
|
|
#define tcg_gen_umax_i32 tcg_gen_umax_i32_riscv64
|
|
#define tcg_gen_abs_i32 tcg_gen_abs_i32_riscv64
|
|
#define tcg_gen_addi_i64 tcg_gen_addi_i64_riscv64
|
|
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_riscv64
|
|
#define tcg_gen_subi_i64 tcg_gen_subi_i64_riscv64
|
|
#define tcg_gen_andi_i64 tcg_gen_andi_i64_riscv64
|
|
#define tcg_gen_ori_i64 tcg_gen_ori_i64_riscv64
|
|
#define tcg_gen_xori_i64 tcg_gen_xori_i64_riscv64
|
|
#define tcg_gen_shli_i64 tcg_gen_shli_i64_riscv64
|
|
#define tcg_gen_shri_i64 tcg_gen_shri_i64_riscv64
|
|
#define tcg_gen_sari_i64 tcg_gen_sari_i64_riscv64
|
|
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_riscv64
|
|
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_riscv64
|
|
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_riscv64
|
|
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_riscv64
|
|
#define tcg_gen_muli_i64 tcg_gen_muli_i64_riscv64
|
|
#define tcg_gen_div_i64 tcg_gen_div_i64_riscv64
|
|
#define tcg_gen_rem_i64 tcg_gen_rem_i64_riscv64
|
|
#define tcg_gen_divu_i64 tcg_gen_divu_i64_riscv64
|
|
#define tcg_gen_remu_i64 tcg_gen_remu_i64_riscv64
|
|
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_riscv64
|
|
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_riscv64
|
|
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_riscv64
|
|
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_riscv64
|
|
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_riscv64
|
|
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_riscv64
|
|
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_riscv64
|
|
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_riscv64
|
|
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_riscv64
|
|
#define tcg_gen_not_i64 tcg_gen_not_i64_riscv64
|
|
#define tcg_gen_andc_i64 tcg_gen_andc_i64_riscv64
|
|
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_riscv64
|
|
#define tcg_gen_nand_i64 tcg_gen_nand_i64_riscv64
|
|
#define tcg_gen_nor_i64 tcg_gen_nor_i64_riscv64
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#define tcg_gen_orc_i64 tcg_gen_orc_i64_riscv64
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#define tcg_gen_clz_i64 tcg_gen_clz_i64_riscv64
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#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_riscv64
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#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_riscv64
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#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_riscv64
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#define tcg_gen_clrsb_i64 tcg_gen_clrsb_i64_riscv64
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#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_riscv64
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#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_riscv64
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#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_riscv64
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#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_riscv64
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#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_riscv64
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#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_riscv64
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#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_riscv64
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#define tcg_gen_extract_i64 tcg_gen_extract_i64_riscv64
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#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_riscv64
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#define tcg_gen_extract2_i64 tcg_gen_extract2_i64_riscv64
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#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_riscv64
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#define tcg_gen_add2_i64 tcg_gen_add2_i64_riscv64
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#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_riscv64
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#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_riscv64
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#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_riscv64
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#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_riscv64
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#define tcg_gen_smin_i64 tcg_gen_smin_i64_riscv64
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#define tcg_gen_umin_i64 tcg_gen_umin_i64_riscv64
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#define tcg_gen_smax_i64 tcg_gen_smax_i64_riscv64
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#define tcg_gen_umax_i64 tcg_gen_umax_i64_riscv64
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#define tcg_gen_abs_i64 tcg_gen_abs_i64_riscv64
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#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_riscv64
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#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_riscv64
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#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_riscv64
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#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_riscv64
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#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_riscv64
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#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_riscv64
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#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_riscv64
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#define tcg_gen_exit_tb tcg_gen_exit_tb_riscv64
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#define tcg_gen_goto_tb tcg_gen_goto_tb_riscv64
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#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_riscv64
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#define check_exit_request check_exit_request_riscv64
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#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_riscv64
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#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_riscv64
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#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_riscv64
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#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_riscv64
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#define tcg_gen_atomic_cmpxchg_i32 tcg_gen_atomic_cmpxchg_i32_riscv64
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#define tcg_gen_atomic_cmpxchg_i64 tcg_gen_atomic_cmpxchg_i64_riscv64
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#define tcg_gen_atomic_fetch_add_i32 tcg_gen_atomic_fetch_add_i32_riscv64
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#define tcg_gen_atomic_fetch_add_i64 tcg_gen_atomic_fetch_add_i64_riscv64
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#define tcg_gen_atomic_fetch_and_i32 tcg_gen_atomic_fetch_and_i32_riscv64
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#define tcg_gen_atomic_fetch_and_i64 tcg_gen_atomic_fetch_and_i64_riscv64
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#define tcg_gen_atomic_fetch_or_i32 tcg_gen_atomic_fetch_or_i32_riscv64
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#define tcg_gen_atomic_fetch_or_i64 tcg_gen_atomic_fetch_or_i64_riscv64
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#define tcg_gen_atomic_fetch_xor_i32 tcg_gen_atomic_fetch_xor_i32_riscv64
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#define tcg_gen_atomic_fetch_xor_i64 tcg_gen_atomic_fetch_xor_i64_riscv64
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#define tcg_gen_atomic_fetch_smin_i32 tcg_gen_atomic_fetch_smin_i32_riscv64
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#define tcg_gen_atomic_fetch_smin_i64 tcg_gen_atomic_fetch_smin_i64_riscv64
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#define tcg_gen_atomic_fetch_umin_i32 tcg_gen_atomic_fetch_umin_i32_riscv64
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#define tcg_gen_atomic_fetch_umin_i64 tcg_gen_atomic_fetch_umin_i64_riscv64
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#define tcg_gen_atomic_fetch_smax_i32 tcg_gen_atomic_fetch_smax_i32_riscv64
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#define tcg_gen_atomic_fetch_smax_i64 tcg_gen_atomic_fetch_smax_i64_riscv64
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#define tcg_gen_atomic_fetch_umax_i32 tcg_gen_atomic_fetch_umax_i32_riscv64
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#define tcg_gen_atomic_fetch_umax_i64 tcg_gen_atomic_fetch_umax_i64_riscv64
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#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_riscv64
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#define tcg_gen_atomic_add_fetch_i64 tcg_gen_atomic_add_fetch_i64_riscv64
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#define tcg_gen_atomic_and_fetch_i32 tcg_gen_atomic_and_fetch_i32_riscv64
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#define tcg_gen_atomic_and_fetch_i64 tcg_gen_atomic_and_fetch_i64_riscv64
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#define tcg_gen_atomic_or_fetch_i32 tcg_gen_atomic_or_fetch_i32_riscv64
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#define tcg_gen_atomic_or_fetch_i64 tcg_gen_atomic_or_fetch_i64_riscv64
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#define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_riscv64
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#define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_riscv64
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#define tcg_gen_atomic_smin_fetch_i32 tcg_gen_atomic_smin_fetch_i32_riscv64
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#define tcg_gen_atomic_smin_fetch_i64 tcg_gen_atomic_smin_fetch_i64_riscv64
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#define tcg_gen_atomic_umin_fetch_i32 tcg_gen_atomic_umin_fetch_i32_riscv64
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#define tcg_gen_atomic_umin_fetch_i64 tcg_gen_atomic_umin_fetch_i64_riscv64
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#define tcg_gen_atomic_smax_fetch_i32 tcg_gen_atomic_smax_fetch_i32_riscv64
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#define tcg_gen_atomic_smax_fetch_i64 tcg_gen_atomic_smax_fetch_i64_riscv64
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#define tcg_gen_atomic_umax_fetch_i32 tcg_gen_atomic_umax_fetch_i32_riscv64
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#define tcg_gen_atomic_umax_fetch_i64 tcg_gen_atomic_umax_fetch_i64_riscv64
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#define tcg_gen_atomic_xchg_i32 tcg_gen_atomic_xchg_i32_riscv64
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#define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_riscv64
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#define simd_desc simd_desc_riscv64
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#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_riscv64
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#define tcg_gen_gvec_2i_ool tcg_gen_gvec_2i_ool_riscv64
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#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_riscv64
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#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_riscv64
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#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_riscv64
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#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_riscv64
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#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_riscv64
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#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_riscv64
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#define tcg_gen_gvec_5_ptr tcg_gen_gvec_5_ptr_riscv64
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#define tcg_gen_gvec_2 tcg_gen_gvec_2_riscv64
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#define tcg_gen_gvec_2i tcg_gen_gvec_2i_riscv64
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#define tcg_gen_gvec_2s tcg_gen_gvec_2s_riscv64
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#define tcg_gen_gvec_3 tcg_gen_gvec_3_riscv64
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#define tcg_gen_gvec_3i tcg_gen_gvec_3i_riscv64
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#define tcg_gen_gvec_4 tcg_gen_gvec_4_riscv64
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#define tcg_gen_gvec_mov tcg_gen_gvec_mov_riscv64
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#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_riscv64
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#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_riscv64
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#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_riscv64
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#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_riscv64
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#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_riscv64
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#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_riscv64
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#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_riscv64
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#define tcg_gen_gvec_not tcg_gen_gvec_not_riscv64
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#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_riscv64
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#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_riscv64
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#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_riscv64
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#define tcg_gen_gvec_add tcg_gen_gvec_add_riscv64
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#define tcg_gen_gvec_adds tcg_gen_gvec_adds_riscv64
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#define tcg_gen_gvec_addi tcg_gen_gvec_addi_riscv64
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#define tcg_gen_gvec_subs tcg_gen_gvec_subs_riscv64
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#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_riscv64
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#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_riscv64
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#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_riscv64
|
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#define tcg_gen_gvec_sub tcg_gen_gvec_sub_riscv64
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|
#define tcg_gen_gvec_mul tcg_gen_gvec_mul_riscv64
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|
#define tcg_gen_gvec_muls tcg_gen_gvec_muls_riscv64
|
|
#define tcg_gen_gvec_muli tcg_gen_gvec_muli_riscv64
|
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#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_riscv64
|
|
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_riscv64
|
|
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_riscv64
|
|
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_riscv64
|
|
#define tcg_gen_gvec_smin tcg_gen_gvec_smin_riscv64
|
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#define tcg_gen_gvec_umin tcg_gen_gvec_umin_riscv64
|
|
#define tcg_gen_gvec_smax tcg_gen_gvec_smax_riscv64
|
|
#define tcg_gen_gvec_umax tcg_gen_gvec_umax_riscv64
|
|
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_riscv64
|
|
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_riscv64
|
|
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_riscv64
|
|
#define tcg_gen_gvec_neg tcg_gen_gvec_neg_riscv64
|
|
#define tcg_gen_gvec_abs tcg_gen_gvec_abs_riscv64
|
|
#define tcg_gen_gvec_and tcg_gen_gvec_and_riscv64
|
|
#define tcg_gen_gvec_or tcg_gen_gvec_or_riscv64
|
|
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_riscv64
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|
#define tcg_gen_gvec_andc tcg_gen_gvec_andc_riscv64
|
|
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_riscv64
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|
#define tcg_gen_gvec_nand tcg_gen_gvec_nand_riscv64
|
|
#define tcg_gen_gvec_nor tcg_gen_gvec_nor_riscv64
|
|
#define tcg_gen_gvec_eqv tcg_gen_gvec_eqv_riscv64
|
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#define tcg_gen_gvec_ands tcg_gen_gvec_ands_riscv64
|
|
#define tcg_gen_gvec_andi tcg_gen_gvec_andi_riscv64
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|
#define tcg_gen_gvec_xors tcg_gen_gvec_xors_riscv64
|
|
#define tcg_gen_gvec_xori tcg_gen_gvec_xori_riscv64
|
|
#define tcg_gen_gvec_ors tcg_gen_gvec_ors_riscv64
|
|
#define tcg_gen_gvec_ori tcg_gen_gvec_ori_riscv64
|
|
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_riscv64
|
|
#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_riscv64
|
|
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_riscv64
|
|
#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_riscv64
|
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#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_riscv64
|
|
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_riscv64
|
|
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_riscv64
|
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#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_riscv64
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|
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_riscv64
|
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#define tcg_gen_gvec_shls tcg_gen_gvec_shls_riscv64
|
|
#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_riscv64
|
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#define tcg_gen_gvec_sars tcg_gen_gvec_sars_riscv64
|
|
#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_riscv64
|
|
#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_riscv64
|
|
#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_riscv64
|
|
#define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_riscv64
|
|
#define tcg_gen_gvec_bitsel tcg_gen_gvec_bitsel_riscv64
|
|
#define tcg_can_emit_vecop_list tcg_can_emit_vecop_list_riscv64
|
|
#define vec_gen_2 vec_gen_2_riscv64
|
|
#define vec_gen_3 vec_gen_3_riscv64
|
|
#define vec_gen_4 vec_gen_4_riscv64
|
|
#define tcg_gen_mov_vec tcg_gen_mov_vec_riscv64
|
|
#define tcg_const_zeros_vec tcg_const_zeros_vec_riscv64
|
|
#define tcg_const_ones_vec tcg_const_ones_vec_riscv64
|
|
#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_riscv64
|
|
#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_riscv64
|
|
#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_riscv64
|
|
#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_riscv64
|
|
#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_riscv64
|
|
#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_riscv64
|
|
#define tcg_gen_dupi_vec tcg_gen_dupi_vec_riscv64
|
|
#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_riscv64
|
|
#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_riscv64
|
|
#define tcg_gen_dup_mem_vec tcg_gen_dup_mem_vec_riscv64
|
|
#define tcg_gen_ld_vec tcg_gen_ld_vec_riscv64
|
|
#define tcg_gen_st_vec tcg_gen_st_vec_riscv64
|
|
#define tcg_gen_stl_vec tcg_gen_stl_vec_riscv64
|
|
#define tcg_gen_and_vec tcg_gen_and_vec_riscv64
|
|
#define tcg_gen_or_vec tcg_gen_or_vec_riscv64
|
|
#define tcg_gen_xor_vec tcg_gen_xor_vec_riscv64
|
|
#define tcg_gen_andc_vec tcg_gen_andc_vec_riscv64
|
|
#define tcg_gen_orc_vec tcg_gen_orc_vec_riscv64
|
|
#define tcg_gen_nand_vec tcg_gen_nand_vec_riscv64
|
|
#define tcg_gen_nor_vec tcg_gen_nor_vec_riscv64
|
|
#define tcg_gen_eqv_vec tcg_gen_eqv_vec_riscv64
|
|
#define tcg_gen_not_vec tcg_gen_not_vec_riscv64
|
|
#define tcg_gen_neg_vec tcg_gen_neg_vec_riscv64
|
|
#define tcg_gen_abs_vec tcg_gen_abs_vec_riscv64
|
|
#define tcg_gen_shli_vec tcg_gen_shli_vec_riscv64
|
|
#define tcg_gen_shri_vec tcg_gen_shri_vec_riscv64
|
|
#define tcg_gen_sari_vec tcg_gen_sari_vec_riscv64
|
|
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_riscv64
|
|
#define tcg_gen_add_vec tcg_gen_add_vec_riscv64
|
|
#define tcg_gen_sub_vec tcg_gen_sub_vec_riscv64
|
|
#define tcg_gen_mul_vec tcg_gen_mul_vec_riscv64
|
|
#define tcg_gen_ssadd_vec tcg_gen_ssadd_vec_riscv64
|
|
#define tcg_gen_usadd_vec tcg_gen_usadd_vec_riscv64
|
|
#define tcg_gen_sssub_vec tcg_gen_sssub_vec_riscv64
|
|
#define tcg_gen_ussub_vec tcg_gen_ussub_vec_riscv64
|
|
#define tcg_gen_smin_vec tcg_gen_smin_vec_riscv64
|
|
#define tcg_gen_umin_vec tcg_gen_umin_vec_riscv64
|
|
#define tcg_gen_smax_vec tcg_gen_smax_vec_riscv64
|
|
#define tcg_gen_umax_vec tcg_gen_umax_vec_riscv64
|
|
#define tcg_gen_shlv_vec tcg_gen_shlv_vec_riscv64
|
|
#define tcg_gen_shrv_vec tcg_gen_shrv_vec_riscv64
|
|
#define tcg_gen_sarv_vec tcg_gen_sarv_vec_riscv64
|
|
#define tcg_gen_shls_vec tcg_gen_shls_vec_riscv64
|
|
#define tcg_gen_shrs_vec tcg_gen_shrs_vec_riscv64
|
|
#define tcg_gen_sars_vec tcg_gen_sars_vec_riscv64
|
|
#define tcg_gen_bitsel_vec tcg_gen_bitsel_vec_riscv64
|
|
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_riscv64
|
|
#define tb_htable_lookup tb_htable_lookup_riscv64
|
|
#define tb_set_jmp_target tb_set_jmp_target_riscv64
|
|
#define cpu_exec cpu_exec_riscv64
|
|
#define cpu_loop_exit_noexc cpu_loop_exit_noexc_riscv64
|
|
#define cpu_reloading_memory_map cpu_reloading_memory_map_riscv64
|
|
#define cpu_loop_exit cpu_loop_exit_riscv64
|
|
#define cpu_loop_exit_restore cpu_loop_exit_restore_riscv64
|
|
#define cpu_loop_exit_atomic cpu_loop_exit_atomic_riscv64
|
|
#define tlb_init tlb_init_riscv64
|
|
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_riscv64
|
|
#define tlb_flush tlb_flush_riscv64
|
|
#define tlb_flush_by_mmuidx_all_cpus tlb_flush_by_mmuidx_all_cpus_riscv64
|
|
#define tlb_flush_all_cpus tlb_flush_all_cpus_riscv64
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#define tlb_flush_by_mmuidx_all_cpus_synced tlb_flush_by_mmuidx_all_cpus_synced_riscv64
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#define tlb_flush_all_cpus_synced tlb_flush_all_cpus_synced_riscv64
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#define tlb_flush_page_by_mmuidx tlb_flush_page_by_mmuidx_riscv64
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#define tlb_flush_page tlb_flush_page_riscv64
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#define tlb_flush_page_by_mmuidx_all_cpus tlb_flush_page_by_mmuidx_all_cpus_riscv64
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#define tlb_flush_page_all_cpus tlb_flush_page_all_cpus_riscv64
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#define tlb_flush_page_by_mmuidx_all_cpus_synced tlb_flush_page_by_mmuidx_all_cpus_synced_riscv64
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#define tlb_flush_page_all_cpus_synced tlb_flush_page_all_cpus_synced_riscv64
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#define tlb_protect_code tlb_protect_code_riscv64
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#define tlb_unprotect_code tlb_unprotect_code_riscv64
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#define tlb_reset_dirty tlb_reset_dirty_riscv64
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#define tlb_set_dirty tlb_set_dirty_riscv64
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#define tlb_set_page_with_attrs tlb_set_page_with_attrs_riscv64
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#define tlb_set_page tlb_set_page_riscv64
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#define get_page_addr_code_hostp get_page_addr_code_hostp_riscv64
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#define get_page_addr_code get_page_addr_code_riscv64
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#define probe_access probe_access_riscv64
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#define tlb_vaddr_to_host tlb_vaddr_to_host_riscv64
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#define helper_ret_ldub_mmu helper_ret_ldub_mmu_riscv64
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#define helper_le_lduw_mmu helper_le_lduw_mmu_riscv64
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#define helper_be_lduw_mmu helper_be_lduw_mmu_riscv64
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#define helper_le_ldul_mmu helper_le_ldul_mmu_riscv64
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#define helper_be_ldul_mmu helper_be_ldul_mmu_riscv64
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#define helper_le_ldq_mmu helper_le_ldq_mmu_riscv64
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#define helper_be_ldq_mmu helper_be_ldq_mmu_riscv64
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#define helper_ret_ldsb_mmu helper_ret_ldsb_mmu_riscv64
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#define helper_le_ldsw_mmu helper_le_ldsw_mmu_riscv64
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#define helper_be_ldsw_mmu helper_be_ldsw_mmu_riscv64
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#define helper_le_ldsl_mmu helper_le_ldsl_mmu_riscv64
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#define helper_be_ldsl_mmu helper_be_ldsl_mmu_riscv64
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#define cpu_ldub_mmuidx_ra cpu_ldub_mmuidx_ra_riscv64
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#define cpu_ldsb_mmuidx_ra cpu_ldsb_mmuidx_ra_riscv64
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#define cpu_lduw_mmuidx_ra cpu_lduw_mmuidx_ra_riscv64
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#define cpu_ldsw_mmuidx_ra cpu_ldsw_mmuidx_ra_riscv64
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#define cpu_ldl_mmuidx_ra cpu_ldl_mmuidx_ra_riscv64
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#define cpu_ldq_mmuidx_ra cpu_ldq_mmuidx_ra_riscv64
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#define cpu_ldub_data_ra cpu_ldub_data_ra_riscv64
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#define cpu_ldsb_data_ra cpu_ldsb_data_ra_riscv64
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#define cpu_lduw_data_ra cpu_lduw_data_ra_riscv64
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#define cpu_ldsw_data_ra cpu_ldsw_data_ra_riscv64
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#define cpu_ldl_data_ra cpu_ldl_data_ra_riscv64
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#define cpu_ldq_data_ra cpu_ldq_data_ra_riscv64
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#define cpu_ldub_data cpu_ldub_data_riscv64
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#define cpu_ldsb_data cpu_ldsb_data_riscv64
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#define cpu_lduw_data cpu_lduw_data_riscv64
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#define cpu_ldsw_data cpu_ldsw_data_riscv64
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#define cpu_ldl_data cpu_ldl_data_riscv64
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#define cpu_ldq_data cpu_ldq_data_riscv64
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#define helper_ret_stb_mmu helper_ret_stb_mmu_riscv64
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#define helper_le_stw_mmu helper_le_stw_mmu_riscv64
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#define helper_be_stw_mmu helper_be_stw_mmu_riscv64
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#define helper_le_stl_mmu helper_le_stl_mmu_riscv64
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#define helper_be_stl_mmu helper_be_stl_mmu_riscv64
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#define helper_le_stq_mmu helper_le_stq_mmu_riscv64
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#define helper_be_stq_mmu helper_be_stq_mmu_riscv64
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#define cpu_stb_mmuidx_ra cpu_stb_mmuidx_ra_riscv64
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#define cpu_stw_mmuidx_ra cpu_stw_mmuidx_ra_riscv64
|
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#define cpu_stl_mmuidx_ra cpu_stl_mmuidx_ra_riscv64
|
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#define cpu_stq_mmuidx_ra cpu_stq_mmuidx_ra_riscv64
|
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#define cpu_stb_data_ra cpu_stb_data_ra_riscv64
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#define cpu_stw_data_ra cpu_stw_data_ra_riscv64
|
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#define cpu_stl_data_ra cpu_stl_data_ra_riscv64
|
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#define cpu_stq_data_ra cpu_stq_data_ra_riscv64
|
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#define cpu_stb_data cpu_stb_data_riscv64
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#define cpu_stw_data cpu_stw_data_riscv64
|
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#define cpu_stl_data cpu_stl_data_riscv64
|
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#define cpu_stq_data cpu_stq_data_riscv64
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#define helper_atomic_cmpxchgb_mmu helper_atomic_cmpxchgb_mmu_riscv64
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#define helper_atomic_xchgb_mmu helper_atomic_xchgb_mmu_riscv64
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#define helper_atomic_fetch_addb_mmu helper_atomic_fetch_addb_mmu_riscv64
|
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#define helper_atomic_fetch_andb_mmu helper_atomic_fetch_andb_mmu_riscv64
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#define helper_atomic_fetch_orb_mmu helper_atomic_fetch_orb_mmu_riscv64
|
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#define helper_atomic_fetch_xorb_mmu helper_atomic_fetch_xorb_mmu_riscv64
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#define helper_atomic_add_fetchb_mmu helper_atomic_add_fetchb_mmu_riscv64
|
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#define helper_atomic_and_fetchb_mmu helper_atomic_and_fetchb_mmu_riscv64
|
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#define helper_atomic_or_fetchb_mmu helper_atomic_or_fetchb_mmu_riscv64
|
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#define helper_atomic_xor_fetchb_mmu helper_atomic_xor_fetchb_mmu_riscv64
|
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#define helper_atomic_fetch_sminb_mmu helper_atomic_fetch_sminb_mmu_riscv64
|
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#define helper_atomic_fetch_uminb_mmu helper_atomic_fetch_uminb_mmu_riscv64
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#define helper_atomic_fetch_smaxb_mmu helper_atomic_fetch_smaxb_mmu_riscv64
|
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#define helper_atomic_fetch_umaxb_mmu helper_atomic_fetch_umaxb_mmu_riscv64
|
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#define helper_atomic_smin_fetchb_mmu helper_atomic_smin_fetchb_mmu_riscv64
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#define helper_atomic_umin_fetchb_mmu helper_atomic_umin_fetchb_mmu_riscv64
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#define helper_atomic_smax_fetchb_mmu helper_atomic_smax_fetchb_mmu_riscv64
|
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#define helper_atomic_umax_fetchb_mmu helper_atomic_umax_fetchb_mmu_riscv64
|
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#define helper_atomic_cmpxchgw_le_mmu helper_atomic_cmpxchgw_le_mmu_riscv64
|
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#define helper_atomic_xchgw_le_mmu helper_atomic_xchgw_le_mmu_riscv64
|
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#define helper_atomic_fetch_addw_le_mmu helper_atomic_fetch_addw_le_mmu_riscv64
|
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#define helper_atomic_fetch_andw_le_mmu helper_atomic_fetch_andw_le_mmu_riscv64
|
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#define helper_atomic_fetch_orw_le_mmu helper_atomic_fetch_orw_le_mmu_riscv64
|
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#define helper_atomic_fetch_xorw_le_mmu helper_atomic_fetch_xorw_le_mmu_riscv64
|
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#define helper_atomic_add_fetchw_le_mmu helper_atomic_add_fetchw_le_mmu_riscv64
|
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#define helper_atomic_and_fetchw_le_mmu helper_atomic_and_fetchw_le_mmu_riscv64
|
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#define helper_atomic_or_fetchw_le_mmu helper_atomic_or_fetchw_le_mmu_riscv64
|
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#define helper_atomic_xor_fetchw_le_mmu helper_atomic_xor_fetchw_le_mmu_riscv64
|
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#define helper_atomic_fetch_sminw_le_mmu helper_atomic_fetch_sminw_le_mmu_riscv64
|
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#define helper_atomic_fetch_uminw_le_mmu helper_atomic_fetch_uminw_le_mmu_riscv64
|
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#define helper_atomic_fetch_smaxw_le_mmu helper_atomic_fetch_smaxw_le_mmu_riscv64
|
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#define helper_atomic_fetch_umaxw_le_mmu helper_atomic_fetch_umaxw_le_mmu_riscv64
|
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#define helper_atomic_smin_fetchw_le_mmu helper_atomic_smin_fetchw_le_mmu_riscv64
|
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#define helper_atomic_umin_fetchw_le_mmu helper_atomic_umin_fetchw_le_mmu_riscv64
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#define helper_atomic_smax_fetchw_le_mmu helper_atomic_smax_fetchw_le_mmu_riscv64
|
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#define helper_atomic_umax_fetchw_le_mmu helper_atomic_umax_fetchw_le_mmu_riscv64
|
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#define helper_atomic_cmpxchgw_be_mmu helper_atomic_cmpxchgw_be_mmu_riscv64
|
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#define helper_atomic_xchgw_be_mmu helper_atomic_xchgw_be_mmu_riscv64
|
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#define helper_atomic_fetch_andw_be_mmu helper_atomic_fetch_andw_be_mmu_riscv64
|
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#define helper_atomic_fetch_orw_be_mmu helper_atomic_fetch_orw_be_mmu_riscv64
|
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#define helper_atomic_fetch_xorw_be_mmu helper_atomic_fetch_xorw_be_mmu_riscv64
|
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#define helper_atomic_and_fetchw_be_mmu helper_atomic_and_fetchw_be_mmu_riscv64
|
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#define helper_atomic_or_fetchw_be_mmu helper_atomic_or_fetchw_be_mmu_riscv64
|
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#define helper_atomic_xor_fetchw_be_mmu helper_atomic_xor_fetchw_be_mmu_riscv64
|
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#define helper_atomic_fetch_sminw_be_mmu helper_atomic_fetch_sminw_be_mmu_riscv64
|
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#define helper_atomic_fetch_uminw_be_mmu helper_atomic_fetch_uminw_be_mmu_riscv64
|
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#define helper_atomic_fetch_smaxw_be_mmu helper_atomic_fetch_smaxw_be_mmu_riscv64
|
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#define helper_atomic_fetch_umaxw_be_mmu helper_atomic_fetch_umaxw_be_mmu_riscv64
|
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#define helper_atomic_smin_fetchw_be_mmu helper_atomic_smin_fetchw_be_mmu_riscv64
|
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#define helper_atomic_umin_fetchw_be_mmu helper_atomic_umin_fetchw_be_mmu_riscv64
|
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#define helper_atomic_smax_fetchw_be_mmu helper_atomic_smax_fetchw_be_mmu_riscv64
|
|
#define helper_atomic_umax_fetchw_be_mmu helper_atomic_umax_fetchw_be_mmu_riscv64
|
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#define helper_atomic_fetch_addw_be_mmu helper_atomic_fetch_addw_be_mmu_riscv64
|
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#define helper_atomic_add_fetchw_be_mmu helper_atomic_add_fetchw_be_mmu_riscv64
|
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#define helper_atomic_cmpxchgl_le_mmu helper_atomic_cmpxchgl_le_mmu_riscv64
|
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#define helper_atomic_xchgl_le_mmu helper_atomic_xchgl_le_mmu_riscv64
|
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#define helper_atomic_fetch_addl_le_mmu helper_atomic_fetch_addl_le_mmu_riscv64
|
|
#define helper_atomic_fetch_andl_le_mmu helper_atomic_fetch_andl_le_mmu_riscv64
|
|
#define helper_atomic_fetch_orl_le_mmu helper_atomic_fetch_orl_le_mmu_riscv64
|
|
#define helper_atomic_fetch_xorl_le_mmu helper_atomic_fetch_xorl_le_mmu_riscv64
|
|
#define helper_atomic_add_fetchl_le_mmu helper_atomic_add_fetchl_le_mmu_riscv64
|
|
#define helper_atomic_and_fetchl_le_mmu helper_atomic_and_fetchl_le_mmu_riscv64
|
|
#define helper_atomic_or_fetchl_le_mmu helper_atomic_or_fetchl_le_mmu_riscv64
|
|
#define helper_atomic_xor_fetchl_le_mmu helper_atomic_xor_fetchl_le_mmu_riscv64
|
|
#define helper_atomic_fetch_sminl_le_mmu helper_atomic_fetch_sminl_le_mmu_riscv64
|
|
#define helper_atomic_fetch_uminl_le_mmu helper_atomic_fetch_uminl_le_mmu_riscv64
|
|
#define helper_atomic_fetch_smaxl_le_mmu helper_atomic_fetch_smaxl_le_mmu_riscv64
|
|
#define helper_atomic_fetch_umaxl_le_mmu helper_atomic_fetch_umaxl_le_mmu_riscv64
|
|
#define helper_atomic_smin_fetchl_le_mmu helper_atomic_smin_fetchl_le_mmu_riscv64
|
|
#define helper_atomic_umin_fetchl_le_mmu helper_atomic_umin_fetchl_le_mmu_riscv64
|
|
#define helper_atomic_smax_fetchl_le_mmu helper_atomic_smax_fetchl_le_mmu_riscv64
|
|
#define helper_atomic_umax_fetchl_le_mmu helper_atomic_umax_fetchl_le_mmu_riscv64
|
|
#define helper_atomic_cmpxchgl_be_mmu helper_atomic_cmpxchgl_be_mmu_riscv64
|
|
#define helper_atomic_xchgl_be_mmu helper_atomic_xchgl_be_mmu_riscv64
|
|
#define helper_atomic_fetch_andl_be_mmu helper_atomic_fetch_andl_be_mmu_riscv64
|
|
#define helper_atomic_fetch_orl_be_mmu helper_atomic_fetch_orl_be_mmu_riscv64
|
|
#define helper_atomic_fetch_xorl_be_mmu helper_atomic_fetch_xorl_be_mmu_riscv64
|
|
#define helper_atomic_and_fetchl_be_mmu helper_atomic_and_fetchl_be_mmu_riscv64
|
|
#define helper_atomic_or_fetchl_be_mmu helper_atomic_or_fetchl_be_mmu_riscv64
|
|
#define helper_atomic_xor_fetchl_be_mmu helper_atomic_xor_fetchl_be_mmu_riscv64
|
|
#define helper_atomic_fetch_sminl_be_mmu helper_atomic_fetch_sminl_be_mmu_riscv64
|
|
#define helper_atomic_fetch_uminl_be_mmu helper_atomic_fetch_uminl_be_mmu_riscv64
|
|
#define helper_atomic_fetch_smaxl_be_mmu helper_atomic_fetch_smaxl_be_mmu_riscv64
|
|
#define helper_atomic_fetch_umaxl_be_mmu helper_atomic_fetch_umaxl_be_mmu_riscv64
|
|
#define helper_atomic_smin_fetchl_be_mmu helper_atomic_smin_fetchl_be_mmu_riscv64
|
|
#define helper_atomic_umin_fetchl_be_mmu helper_atomic_umin_fetchl_be_mmu_riscv64
|
|
#define helper_atomic_smax_fetchl_be_mmu helper_atomic_smax_fetchl_be_mmu_riscv64
|
|
#define helper_atomic_umax_fetchl_be_mmu helper_atomic_umax_fetchl_be_mmu_riscv64
|
|
#define helper_atomic_fetch_addl_be_mmu helper_atomic_fetch_addl_be_mmu_riscv64
|
|
#define helper_atomic_add_fetchl_be_mmu helper_atomic_add_fetchl_be_mmu_riscv64
|
|
#define helper_atomic_cmpxchgq_le_mmu helper_atomic_cmpxchgq_le_mmu_riscv64
|
|
#define helper_atomic_xchgq_le_mmu helper_atomic_xchgq_le_mmu_riscv64
|
|
#define helper_atomic_fetch_addq_le_mmu helper_atomic_fetch_addq_le_mmu_riscv64
|
|
#define helper_atomic_fetch_andq_le_mmu helper_atomic_fetch_andq_le_mmu_riscv64
|
|
#define helper_atomic_fetch_orq_le_mmu helper_atomic_fetch_orq_le_mmu_riscv64
|
|
#define helper_atomic_fetch_xorq_le_mmu helper_atomic_fetch_xorq_le_mmu_riscv64
|
|
#define helper_atomic_add_fetchq_le_mmu helper_atomic_add_fetchq_le_mmu_riscv64
|
|
#define helper_atomic_and_fetchq_le_mmu helper_atomic_and_fetchq_le_mmu_riscv64
|
|
#define helper_atomic_or_fetchq_le_mmu helper_atomic_or_fetchq_le_mmu_riscv64
|
|
#define helper_atomic_xor_fetchq_le_mmu helper_atomic_xor_fetchq_le_mmu_riscv64
|
|
#define helper_atomic_fetch_sminq_le_mmu helper_atomic_fetch_sminq_le_mmu_riscv64
|
|
#define helper_atomic_fetch_uminq_le_mmu helper_atomic_fetch_uminq_le_mmu_riscv64
|
|
#define helper_atomic_fetch_smaxq_le_mmu helper_atomic_fetch_smaxq_le_mmu_riscv64
|
|
#define helper_atomic_fetch_umaxq_le_mmu helper_atomic_fetch_umaxq_le_mmu_riscv64
|
|
#define helper_atomic_smin_fetchq_le_mmu helper_atomic_smin_fetchq_le_mmu_riscv64
|
|
#define helper_atomic_umin_fetchq_le_mmu helper_atomic_umin_fetchq_le_mmu_riscv64
|
|
#define helper_atomic_smax_fetchq_le_mmu helper_atomic_smax_fetchq_le_mmu_riscv64
|
|
#define helper_atomic_umax_fetchq_le_mmu helper_atomic_umax_fetchq_le_mmu_riscv64
|
|
#define helper_atomic_cmpxchgq_be_mmu helper_atomic_cmpxchgq_be_mmu_riscv64
|
|
#define helper_atomic_xchgq_be_mmu helper_atomic_xchgq_be_mmu_riscv64
|
|
#define helper_atomic_fetch_andq_be_mmu helper_atomic_fetch_andq_be_mmu_riscv64
|
|
#define helper_atomic_fetch_orq_be_mmu helper_atomic_fetch_orq_be_mmu_riscv64
|
|
#define helper_atomic_fetch_xorq_be_mmu helper_atomic_fetch_xorq_be_mmu_riscv64
|
|
#define helper_atomic_and_fetchq_be_mmu helper_atomic_and_fetchq_be_mmu_riscv64
|
|
#define helper_atomic_or_fetchq_be_mmu helper_atomic_or_fetchq_be_mmu_riscv64
|
|
#define helper_atomic_xor_fetchq_be_mmu helper_atomic_xor_fetchq_be_mmu_riscv64
|
|
#define helper_atomic_fetch_sminq_be_mmu helper_atomic_fetch_sminq_be_mmu_riscv64
|
|
#define helper_atomic_fetch_uminq_be_mmu helper_atomic_fetch_uminq_be_mmu_riscv64
|
|
#define helper_atomic_fetch_smaxq_be_mmu helper_atomic_fetch_smaxq_be_mmu_riscv64
|
|
#define helper_atomic_fetch_umaxq_be_mmu helper_atomic_fetch_umaxq_be_mmu_riscv64
|
|
#define helper_atomic_smin_fetchq_be_mmu helper_atomic_smin_fetchq_be_mmu_riscv64
|
|
#define helper_atomic_umin_fetchq_be_mmu helper_atomic_umin_fetchq_be_mmu_riscv64
|
|
#define helper_atomic_smax_fetchq_be_mmu helper_atomic_smax_fetchq_be_mmu_riscv64
|
|
#define helper_atomic_umax_fetchq_be_mmu helper_atomic_umax_fetchq_be_mmu_riscv64
|
|
#define helper_atomic_fetch_addq_be_mmu helper_atomic_fetch_addq_be_mmu_riscv64
|
|
#define helper_atomic_add_fetchq_be_mmu helper_atomic_add_fetchq_be_mmu_riscv64
|
|
#define helper_atomic_cmpxchgb helper_atomic_cmpxchgb_riscv64
|
|
#define helper_atomic_xchgb helper_atomic_xchgb_riscv64
|
|
#define helper_atomic_fetch_addb helper_atomic_fetch_addb_riscv64
|
|
#define helper_atomic_fetch_andb helper_atomic_fetch_andb_riscv64
|
|
#define helper_atomic_fetch_orb helper_atomic_fetch_orb_riscv64
|
|
#define helper_atomic_fetch_xorb helper_atomic_fetch_xorb_riscv64
|
|
#define helper_atomic_add_fetchb helper_atomic_add_fetchb_riscv64
|
|
#define helper_atomic_and_fetchb helper_atomic_and_fetchb_riscv64
|
|
#define helper_atomic_or_fetchb helper_atomic_or_fetchb_riscv64
|
|
#define helper_atomic_xor_fetchb helper_atomic_xor_fetchb_riscv64
|
|
#define helper_atomic_fetch_sminb helper_atomic_fetch_sminb_riscv64
|
|
#define helper_atomic_fetch_uminb helper_atomic_fetch_uminb_riscv64
|
|
#define helper_atomic_fetch_smaxb helper_atomic_fetch_smaxb_riscv64
|
|
#define helper_atomic_fetch_umaxb helper_atomic_fetch_umaxb_riscv64
|
|
#define helper_atomic_smin_fetchb helper_atomic_smin_fetchb_riscv64
|
|
#define helper_atomic_umin_fetchb helper_atomic_umin_fetchb_riscv64
|
|
#define helper_atomic_smax_fetchb helper_atomic_smax_fetchb_riscv64
|
|
#define helper_atomic_umax_fetchb helper_atomic_umax_fetchb_riscv64
|
|
#define helper_atomic_cmpxchgw_le helper_atomic_cmpxchgw_le_riscv64
|
|
#define helper_atomic_xchgw_le helper_atomic_xchgw_le_riscv64
|
|
#define helper_atomic_fetch_addw_le helper_atomic_fetch_addw_le_riscv64
|
|
#define helper_atomic_fetch_andw_le helper_atomic_fetch_andw_le_riscv64
|
|
#define helper_atomic_fetch_orw_le helper_atomic_fetch_orw_le_riscv64
|
|
#define helper_atomic_fetch_xorw_le helper_atomic_fetch_xorw_le_riscv64
|
|
#define helper_atomic_add_fetchw_le helper_atomic_add_fetchw_le_riscv64
|
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#define helper_atomic_and_fetchw_le helper_atomic_and_fetchw_le_riscv64
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#define helper_atomic_or_fetchw_le helper_atomic_or_fetchw_le_riscv64
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#define helper_atomic_xor_fetchw_le helper_atomic_xor_fetchw_le_riscv64
|
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#define helper_atomic_fetch_sminw_le helper_atomic_fetch_sminw_le_riscv64
|
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#define helper_atomic_fetch_uminw_le helper_atomic_fetch_uminw_le_riscv64
|
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#define helper_atomic_fetch_smaxw_le helper_atomic_fetch_smaxw_le_riscv64
|
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#define helper_atomic_fetch_umaxw_le helper_atomic_fetch_umaxw_le_riscv64
|
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#define helper_atomic_smin_fetchw_le helper_atomic_smin_fetchw_le_riscv64
|
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#define helper_atomic_umin_fetchw_le helper_atomic_umin_fetchw_le_riscv64
|
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#define helper_atomic_smax_fetchw_le helper_atomic_smax_fetchw_le_riscv64
|
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#define helper_atomic_umax_fetchw_le helper_atomic_umax_fetchw_le_riscv64
|
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#define helper_atomic_cmpxchgw_be helper_atomic_cmpxchgw_be_riscv64
|
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#define helper_atomic_xchgw_be helper_atomic_xchgw_be_riscv64
|
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#define helper_atomic_fetch_andw_be helper_atomic_fetch_andw_be_riscv64
|
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#define helper_atomic_fetch_orw_be helper_atomic_fetch_orw_be_riscv64
|
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#define helper_atomic_fetch_xorw_be helper_atomic_fetch_xorw_be_riscv64
|
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#define helper_atomic_and_fetchw_be helper_atomic_and_fetchw_be_riscv64
|
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#define helper_atomic_or_fetchw_be helper_atomic_or_fetchw_be_riscv64
|
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#define helper_atomic_xor_fetchw_be helper_atomic_xor_fetchw_be_riscv64
|
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#define helper_atomic_fetch_sminw_be helper_atomic_fetch_sminw_be_riscv64
|
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#define helper_atomic_fetch_uminw_be helper_atomic_fetch_uminw_be_riscv64
|
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#define helper_atomic_fetch_smaxw_be helper_atomic_fetch_smaxw_be_riscv64
|
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#define helper_atomic_fetch_umaxw_be helper_atomic_fetch_umaxw_be_riscv64
|
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#define helper_atomic_smin_fetchw_be helper_atomic_smin_fetchw_be_riscv64
|
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#define helper_atomic_umin_fetchw_be helper_atomic_umin_fetchw_be_riscv64
|
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#define helper_atomic_smax_fetchw_be helper_atomic_smax_fetchw_be_riscv64
|
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#define helper_atomic_umax_fetchw_be helper_atomic_umax_fetchw_be_riscv64
|
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#define helper_atomic_fetch_addw_be helper_atomic_fetch_addw_be_riscv64
|
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#define helper_atomic_add_fetchw_be helper_atomic_add_fetchw_be_riscv64
|
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#define helper_atomic_cmpxchgl_le helper_atomic_cmpxchgl_le_riscv64
|
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#define helper_atomic_xchgl_le helper_atomic_xchgl_le_riscv64
|
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#define helper_atomic_fetch_addl_le helper_atomic_fetch_addl_le_riscv64
|
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#define helper_atomic_fetch_andl_le helper_atomic_fetch_andl_le_riscv64
|
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#define helper_atomic_fetch_orl_le helper_atomic_fetch_orl_le_riscv64
|
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#define helper_atomic_fetch_xorl_le helper_atomic_fetch_xorl_le_riscv64
|
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#define helper_atomic_add_fetchl_le helper_atomic_add_fetchl_le_riscv64
|
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#define helper_atomic_and_fetchl_le helper_atomic_and_fetchl_le_riscv64
|
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#define helper_atomic_or_fetchl_le helper_atomic_or_fetchl_le_riscv64
|
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#define helper_atomic_xor_fetchl_le helper_atomic_xor_fetchl_le_riscv64
|
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#define helper_atomic_fetch_sminl_le helper_atomic_fetch_sminl_le_riscv64
|
|
#define helper_atomic_fetch_uminl_le helper_atomic_fetch_uminl_le_riscv64
|
|
#define helper_atomic_fetch_smaxl_le helper_atomic_fetch_smaxl_le_riscv64
|
|
#define helper_atomic_fetch_umaxl_le helper_atomic_fetch_umaxl_le_riscv64
|
|
#define helper_atomic_smin_fetchl_le helper_atomic_smin_fetchl_le_riscv64
|
|
#define helper_atomic_umin_fetchl_le helper_atomic_umin_fetchl_le_riscv64
|
|
#define helper_atomic_smax_fetchl_le helper_atomic_smax_fetchl_le_riscv64
|
|
#define helper_atomic_umax_fetchl_le helper_atomic_umax_fetchl_le_riscv64
|
|
#define helper_atomic_cmpxchgl_be helper_atomic_cmpxchgl_be_riscv64
|
|
#define helper_atomic_xchgl_be helper_atomic_xchgl_be_riscv64
|
|
#define helper_atomic_fetch_andl_be helper_atomic_fetch_andl_be_riscv64
|
|
#define helper_atomic_fetch_orl_be helper_atomic_fetch_orl_be_riscv64
|
|
#define helper_atomic_fetch_xorl_be helper_atomic_fetch_xorl_be_riscv64
|
|
#define helper_atomic_and_fetchl_be helper_atomic_and_fetchl_be_riscv64
|
|
#define helper_atomic_or_fetchl_be helper_atomic_or_fetchl_be_riscv64
|
|
#define helper_atomic_xor_fetchl_be helper_atomic_xor_fetchl_be_riscv64
|
|
#define helper_atomic_fetch_sminl_be helper_atomic_fetch_sminl_be_riscv64
|
|
#define helper_atomic_fetch_uminl_be helper_atomic_fetch_uminl_be_riscv64
|
|
#define helper_atomic_fetch_smaxl_be helper_atomic_fetch_smaxl_be_riscv64
|
|
#define helper_atomic_fetch_umaxl_be helper_atomic_fetch_umaxl_be_riscv64
|
|
#define helper_atomic_smin_fetchl_be helper_atomic_smin_fetchl_be_riscv64
|
|
#define helper_atomic_umin_fetchl_be helper_atomic_umin_fetchl_be_riscv64
|
|
#define helper_atomic_smax_fetchl_be helper_atomic_smax_fetchl_be_riscv64
|
|
#define helper_atomic_umax_fetchl_be helper_atomic_umax_fetchl_be_riscv64
|
|
#define helper_atomic_fetch_addl_be helper_atomic_fetch_addl_be_riscv64
|
|
#define helper_atomic_add_fetchl_be helper_atomic_add_fetchl_be_riscv64
|
|
#define helper_atomic_cmpxchgq_le helper_atomic_cmpxchgq_le_riscv64
|
|
#define helper_atomic_xchgq_le helper_atomic_xchgq_le_riscv64
|
|
#define helper_atomic_fetch_addq_le helper_atomic_fetch_addq_le_riscv64
|
|
#define helper_atomic_fetch_andq_le helper_atomic_fetch_andq_le_riscv64
|
|
#define helper_atomic_fetch_orq_le helper_atomic_fetch_orq_le_riscv64
|
|
#define helper_atomic_fetch_xorq_le helper_atomic_fetch_xorq_le_riscv64
|
|
#define helper_atomic_add_fetchq_le helper_atomic_add_fetchq_le_riscv64
|
|
#define helper_atomic_and_fetchq_le helper_atomic_and_fetchq_le_riscv64
|
|
#define helper_atomic_or_fetchq_le helper_atomic_or_fetchq_le_riscv64
|
|
#define helper_atomic_xor_fetchq_le helper_atomic_xor_fetchq_le_riscv64
|
|
#define helper_atomic_fetch_sminq_le helper_atomic_fetch_sminq_le_riscv64
|
|
#define helper_atomic_fetch_uminq_le helper_atomic_fetch_uminq_le_riscv64
|
|
#define helper_atomic_fetch_smaxq_le helper_atomic_fetch_smaxq_le_riscv64
|
|
#define helper_atomic_fetch_umaxq_le helper_atomic_fetch_umaxq_le_riscv64
|
|
#define helper_atomic_smin_fetchq_le helper_atomic_smin_fetchq_le_riscv64
|
|
#define helper_atomic_umin_fetchq_le helper_atomic_umin_fetchq_le_riscv64
|
|
#define helper_atomic_smax_fetchq_le helper_atomic_smax_fetchq_le_riscv64
|
|
#define helper_atomic_umax_fetchq_le helper_atomic_umax_fetchq_le_riscv64
|
|
#define helper_atomic_cmpxchgq_be helper_atomic_cmpxchgq_be_riscv64
|
|
#define helper_atomic_xchgq_be helper_atomic_xchgq_be_riscv64
|
|
#define helper_atomic_fetch_andq_be helper_atomic_fetch_andq_be_riscv64
|
|
#define helper_atomic_fetch_orq_be helper_atomic_fetch_orq_be_riscv64
|
|
#define helper_atomic_fetch_xorq_be helper_atomic_fetch_xorq_be_riscv64
|
|
#define helper_atomic_and_fetchq_be helper_atomic_and_fetchq_be_riscv64
|
|
#define helper_atomic_or_fetchq_be helper_atomic_or_fetchq_be_riscv64
|
|
#define helper_atomic_xor_fetchq_be helper_atomic_xor_fetchq_be_riscv64
|
|
#define helper_atomic_fetch_sminq_be helper_atomic_fetch_sminq_be_riscv64
|
|
#define helper_atomic_fetch_uminq_be helper_atomic_fetch_uminq_be_riscv64
|
|
#define helper_atomic_fetch_smaxq_be helper_atomic_fetch_smaxq_be_riscv64
|
|
#define helper_atomic_fetch_umaxq_be helper_atomic_fetch_umaxq_be_riscv64
|
|
#define helper_atomic_smin_fetchq_be helper_atomic_smin_fetchq_be_riscv64
|
|
#define helper_atomic_umin_fetchq_be helper_atomic_umin_fetchq_be_riscv64
|
|
#define helper_atomic_smax_fetchq_be helper_atomic_smax_fetchq_be_riscv64
|
|
#define helper_atomic_umax_fetchq_be helper_atomic_umax_fetchq_be_riscv64
|
|
#define helper_atomic_fetch_addq_be helper_atomic_fetch_addq_be_riscv64
|
|
#define helper_atomic_add_fetchq_be helper_atomic_add_fetchq_be_riscv64
|
|
#define cpu_ldub_code cpu_ldub_code_riscv64
|
|
#define cpu_lduw_code cpu_lduw_code_riscv64
|
|
#define cpu_ldl_code cpu_ldl_code_riscv64
|
|
#define cpu_ldq_code cpu_ldq_code_riscv64
|
|
#define helper_div_i32 helper_div_i32_riscv64
|
|
#define helper_rem_i32 helper_rem_i32_riscv64
|
|
#define helper_divu_i32 helper_divu_i32_riscv64
|
|
#define helper_remu_i32 helper_remu_i32_riscv64
|
|
#define helper_shl_i64 helper_shl_i64_riscv64
|
|
#define helper_shr_i64 helper_shr_i64_riscv64
|
|
#define helper_sar_i64 helper_sar_i64_riscv64
|
|
#define helper_div_i64 helper_div_i64_riscv64
|
|
#define helper_rem_i64 helper_rem_i64_riscv64
|
|
#define helper_divu_i64 helper_divu_i64_riscv64
|
|
#define helper_remu_i64 helper_remu_i64_riscv64
|
|
#define helper_muluh_i64 helper_muluh_i64_riscv64
|
|
#define helper_mulsh_i64 helper_mulsh_i64_riscv64
|
|
#define helper_clz_i32 helper_clz_i32_riscv64
|
|
#define helper_ctz_i32 helper_ctz_i32_riscv64
|
|
#define helper_clz_i64 helper_clz_i64_riscv64
|
|
#define helper_ctz_i64 helper_ctz_i64_riscv64
|
|
#define helper_clrsb_i32 helper_clrsb_i32_riscv64
|
|
#define helper_clrsb_i64 helper_clrsb_i64_riscv64
|
|
#define helper_ctpop_i32 helper_ctpop_i32_riscv64
|
|
#define helper_ctpop_i64 helper_ctpop_i64_riscv64
|
|
#define helper_lookup_tb_ptr helper_lookup_tb_ptr_riscv64
|
|
#define helper_exit_atomic helper_exit_atomic_riscv64
|
|
#define helper_gvec_add8 helper_gvec_add8_riscv64
|
|
#define helper_gvec_add16 helper_gvec_add16_riscv64
|
|
#define helper_gvec_add32 helper_gvec_add32_riscv64
|
|
#define helper_gvec_add64 helper_gvec_add64_riscv64
|
|
#define helper_gvec_adds8 helper_gvec_adds8_riscv64
|
|
#define helper_gvec_adds16 helper_gvec_adds16_riscv64
|
|
#define helper_gvec_adds32 helper_gvec_adds32_riscv64
|
|
#define helper_gvec_adds64 helper_gvec_adds64_riscv64
|
|
#define helper_gvec_sub8 helper_gvec_sub8_riscv64
|
|
#define helper_gvec_sub16 helper_gvec_sub16_riscv64
|
|
#define helper_gvec_sub32 helper_gvec_sub32_riscv64
|
|
#define helper_gvec_sub64 helper_gvec_sub64_riscv64
|
|
#define helper_gvec_subs8 helper_gvec_subs8_riscv64
|
|
#define helper_gvec_subs16 helper_gvec_subs16_riscv64
|
|
#define helper_gvec_subs32 helper_gvec_subs32_riscv64
|
|
#define helper_gvec_subs64 helper_gvec_subs64_riscv64
|
|
#define helper_gvec_mul8 helper_gvec_mul8_riscv64
|
|
#define helper_gvec_mul16 helper_gvec_mul16_riscv64
|
|
#define helper_gvec_mul32 helper_gvec_mul32_riscv64
|
|
#define helper_gvec_mul64 helper_gvec_mul64_riscv64
|
|
#define helper_gvec_muls8 helper_gvec_muls8_riscv64
|
|
#define helper_gvec_muls16 helper_gvec_muls16_riscv64
|
|
#define helper_gvec_muls32 helper_gvec_muls32_riscv64
|
|
#define helper_gvec_muls64 helper_gvec_muls64_riscv64
|
|
#define helper_gvec_neg8 helper_gvec_neg8_riscv64
|
|
#define helper_gvec_neg16 helper_gvec_neg16_riscv64
|
|
#define helper_gvec_neg32 helper_gvec_neg32_riscv64
|
|
#define helper_gvec_neg64 helper_gvec_neg64_riscv64
|
|
#define helper_gvec_abs8 helper_gvec_abs8_riscv64
|
|
#define helper_gvec_abs16 helper_gvec_abs16_riscv64
|
|
#define helper_gvec_abs32 helper_gvec_abs32_riscv64
|
|
#define helper_gvec_abs64 helper_gvec_abs64_riscv64
|
|
#define helper_gvec_mov helper_gvec_mov_riscv64
|
|
#define helper_gvec_dup64 helper_gvec_dup64_riscv64
|
|
#define helper_gvec_dup32 helper_gvec_dup32_riscv64
|
|
#define helper_gvec_dup16 helper_gvec_dup16_riscv64
|
|
#define helper_gvec_dup8 helper_gvec_dup8_riscv64
|
|
#define helper_gvec_not helper_gvec_not_riscv64
|
|
#define helper_gvec_and helper_gvec_and_riscv64
|
|
#define helper_gvec_or helper_gvec_or_riscv64
|
|
#define helper_gvec_xor helper_gvec_xor_riscv64
|
|
#define helper_gvec_andc helper_gvec_andc_riscv64
|
|
#define helper_gvec_orc helper_gvec_orc_riscv64
|
|
#define helper_gvec_nand helper_gvec_nand_riscv64
|
|
#define helper_gvec_nor helper_gvec_nor_riscv64
|
|
#define helper_gvec_eqv helper_gvec_eqv_riscv64
|
|
#define helper_gvec_ands helper_gvec_ands_riscv64
|
|
#define helper_gvec_xors helper_gvec_xors_riscv64
|
|
#define helper_gvec_ors helper_gvec_ors_riscv64
|
|
#define helper_gvec_shl8i helper_gvec_shl8i_riscv64
|
|
#define helper_gvec_shl16i helper_gvec_shl16i_riscv64
|
|
#define helper_gvec_shl32i helper_gvec_shl32i_riscv64
|
|
#define helper_gvec_shl64i helper_gvec_shl64i_riscv64
|
|
#define helper_gvec_shr8i helper_gvec_shr8i_riscv64
|
|
#define helper_gvec_shr16i helper_gvec_shr16i_riscv64
|
|
#define helper_gvec_shr32i helper_gvec_shr32i_riscv64
|
|
#define helper_gvec_shr64i helper_gvec_shr64i_riscv64
|
|
#define helper_gvec_sar8i helper_gvec_sar8i_riscv64
|
|
#define helper_gvec_sar16i helper_gvec_sar16i_riscv64
|
|
#define helper_gvec_sar32i helper_gvec_sar32i_riscv64
|
|
#define helper_gvec_sar64i helper_gvec_sar64i_riscv64
|
|
#define helper_gvec_shl8v helper_gvec_shl8v_riscv64
|
|
#define helper_gvec_shl16v helper_gvec_shl16v_riscv64
|
|
#define helper_gvec_shl32v helper_gvec_shl32v_riscv64
|
|
#define helper_gvec_shl64v helper_gvec_shl64v_riscv64
|
|
#define helper_gvec_shr8v helper_gvec_shr8v_riscv64
|
|
#define helper_gvec_shr16v helper_gvec_shr16v_riscv64
|
|
#define helper_gvec_shr32v helper_gvec_shr32v_riscv64
|
|
#define helper_gvec_shr64v helper_gvec_shr64v_riscv64
|
|
#define helper_gvec_sar8v helper_gvec_sar8v_riscv64
|
|
#define helper_gvec_sar16v helper_gvec_sar16v_riscv64
|
|
#define helper_gvec_sar32v helper_gvec_sar32v_riscv64
|
|
#define helper_gvec_sar64v helper_gvec_sar64v_riscv64
|
|
#define helper_gvec_eq8 helper_gvec_eq8_riscv64
|
|
#define helper_gvec_ne8 helper_gvec_ne8_riscv64
|
|
#define helper_gvec_lt8 helper_gvec_lt8_riscv64
|
|
#define helper_gvec_le8 helper_gvec_le8_riscv64
|
|
#define helper_gvec_ltu8 helper_gvec_ltu8_riscv64
|
|
#define helper_gvec_leu8 helper_gvec_leu8_riscv64
|
|
#define helper_gvec_eq16 helper_gvec_eq16_riscv64
|
|
#define helper_gvec_ne16 helper_gvec_ne16_riscv64
|
|
#define helper_gvec_lt16 helper_gvec_lt16_riscv64
|
|
#define helper_gvec_le16 helper_gvec_le16_riscv64
|
|
#define helper_gvec_ltu16 helper_gvec_ltu16_riscv64
|
|
#define helper_gvec_leu16 helper_gvec_leu16_riscv64
|
|
#define helper_gvec_eq32 helper_gvec_eq32_riscv64
|
|
#define helper_gvec_ne32 helper_gvec_ne32_riscv64
|
|
#define helper_gvec_lt32 helper_gvec_lt32_riscv64
|
|
#define helper_gvec_le32 helper_gvec_le32_riscv64
|
|
#define helper_gvec_ltu32 helper_gvec_ltu32_riscv64
|
|
#define helper_gvec_leu32 helper_gvec_leu32_riscv64
|
|
#define helper_gvec_eq64 helper_gvec_eq64_riscv64
|
|
#define helper_gvec_ne64 helper_gvec_ne64_riscv64
|
|
#define helper_gvec_lt64 helper_gvec_lt64_riscv64
|
|
#define helper_gvec_le64 helper_gvec_le64_riscv64
|
|
#define helper_gvec_ltu64 helper_gvec_ltu64_riscv64
|
|
#define helper_gvec_leu64 helper_gvec_leu64_riscv64
|
|
#define helper_gvec_ssadd8 helper_gvec_ssadd8_riscv64
|
|
#define helper_gvec_ssadd16 helper_gvec_ssadd16_riscv64
|
|
#define helper_gvec_ssadd32 helper_gvec_ssadd32_riscv64
|
|
#define helper_gvec_ssadd64 helper_gvec_ssadd64_riscv64
|
|
#define helper_gvec_sssub8 helper_gvec_sssub8_riscv64
|
|
#define helper_gvec_sssub16 helper_gvec_sssub16_riscv64
|
|
#define helper_gvec_sssub32 helper_gvec_sssub32_riscv64
|
|
#define helper_gvec_sssub64 helper_gvec_sssub64_riscv64
|
|
#define helper_gvec_usadd8 helper_gvec_usadd8_riscv64
|
|
#define helper_gvec_usadd16 helper_gvec_usadd16_riscv64
|
|
#define helper_gvec_usadd32 helper_gvec_usadd32_riscv64
|
|
#define helper_gvec_usadd64 helper_gvec_usadd64_riscv64
|
|
#define helper_gvec_ussub8 helper_gvec_ussub8_riscv64
|
|
#define helper_gvec_ussub16 helper_gvec_ussub16_riscv64
|
|
#define helper_gvec_ussub32 helper_gvec_ussub32_riscv64
|
|
#define helper_gvec_ussub64 helper_gvec_ussub64_riscv64
|
|
#define helper_gvec_smin8 helper_gvec_smin8_riscv64
|
|
#define helper_gvec_smin16 helper_gvec_smin16_riscv64
|
|
#define helper_gvec_smin32 helper_gvec_smin32_riscv64
|
|
#define helper_gvec_smin64 helper_gvec_smin64_riscv64
|
|
#define helper_gvec_smax8 helper_gvec_smax8_riscv64
|
|
#define helper_gvec_smax16 helper_gvec_smax16_riscv64
|
|
#define helper_gvec_smax32 helper_gvec_smax32_riscv64
|
|
#define helper_gvec_smax64 helper_gvec_smax64_riscv64
|
|
#define helper_gvec_umin8 helper_gvec_umin8_riscv64
|
|
#define helper_gvec_umin16 helper_gvec_umin16_riscv64
|
|
#define helper_gvec_umin32 helper_gvec_umin32_riscv64
|
|
#define helper_gvec_umin64 helper_gvec_umin64_riscv64
|
|
#define helper_gvec_umax8 helper_gvec_umax8_riscv64
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#define helper_gvec_umax16 helper_gvec_umax16_riscv64
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#define helper_gvec_umax32 helper_gvec_umax32_riscv64
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#define helper_gvec_umax64 helper_gvec_umax64_riscv64
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#define helper_gvec_bitsel helper_gvec_bitsel_riscv64
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#define cpu_restore_state cpu_restore_state_riscv64
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#define page_collection_lock page_collection_lock_riscv64
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#define page_collection_unlock page_collection_unlock_riscv64
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#define free_code_gen_buffer free_code_gen_buffer_riscv64
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#define tcg_exec_init tcg_exec_init_riscv64
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#define tb_cleanup tb_cleanup_riscv64
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#define tb_flush tb_flush_riscv64
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#define tb_phys_invalidate tb_phys_invalidate_riscv64
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#define tb_gen_code tb_gen_code_riscv64
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#define tb_exec_lock tb_exec_lock_riscv64
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#define tb_exec_unlock tb_exec_unlock_riscv64
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#define tb_invalidate_phys_page_range tb_invalidate_phys_page_range_riscv64
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#define tb_invalidate_phys_range tb_invalidate_phys_range_riscv64
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#define tb_invalidate_phys_page_fast tb_invalidate_phys_page_fast_riscv64
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#define tb_check_watchpoint tb_check_watchpoint_riscv64
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#define cpu_io_recompile cpu_io_recompile_riscv64
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#define tb_flush_jmp_cache tb_flush_jmp_cache_riscv64
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#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_riscv64
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#define translator_loop_temp_check translator_loop_temp_check_riscv64
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#define translator_loop translator_loop_riscv64
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#define helper_atomic_cmpxchgo_le_mmu helper_atomic_cmpxchgo_le_mmu_riscv64
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#define helper_atomic_cmpxchgo_be_mmu helper_atomic_cmpxchgo_be_mmu_riscv64
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#define helper_atomic_ldo_le_mmu helper_atomic_ldo_le_mmu_riscv64
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#define helper_atomic_ldo_be_mmu helper_atomic_ldo_be_mmu_riscv64
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#define helper_atomic_sto_le_mmu helper_atomic_sto_le_mmu_riscv64
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#define helper_atomic_sto_be_mmu helper_atomic_sto_be_mmu_riscv64
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#define unassigned_mem_ops unassigned_mem_ops_riscv64
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#define floatx80_infinity floatx80_infinity_riscv64
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#define dup_const_func dup_const_func_riscv64
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#define gen_helper_raise_exception gen_helper_raise_exception_riscv64
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#define gen_helper_raise_interrupt gen_helper_raise_interrupt_riscv64
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#define gen_helper_vfp_get_fpscr gen_helper_vfp_get_fpscr_riscv64
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#define gen_helper_vfp_set_fpscr gen_helper_vfp_set_fpscr_riscv64
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#define gen_helper_cpsr_read gen_helper_cpsr_read_riscv64
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#define gen_helper_cpsr_write gen_helper_cpsr_write_riscv64
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#define riscv_cpu_mmu_index riscv_cpu_mmu_index_riscv64
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#define riscv_cpu_exec_interrupt riscv_cpu_exec_interrupt_riscv64
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#define riscv_cpu_fp_enabled riscv_cpu_fp_enabled_riscv64
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#define riscv_cpu_swap_hypervisor_regs riscv_cpu_swap_hypervisor_regs_riscv64
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#define riscv_cpu_virt_enabled riscv_cpu_virt_enabled_riscv64
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#define riscv_cpu_set_virt_enabled riscv_cpu_set_virt_enabled_riscv64
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#define riscv_cpu_force_hs_excep_enabled riscv_cpu_force_hs_excep_enabled_riscv64
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#define riscv_cpu_set_force_hs_excep riscv_cpu_set_force_hs_excep_riscv64
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#define riscv_cpu_claim_interrupts riscv_cpu_claim_interrupts_riscv64
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#define riscv_cpu_update_mip riscv_cpu_update_mip_riscv64
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#define riscv_cpu_set_rdtime_fn riscv_cpu_set_rdtime_fn_riscv64
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#define riscv_cpu_set_mode riscv_cpu_set_mode_riscv64
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#define riscv_cpu_get_phys_page_debug riscv_cpu_get_phys_page_debug_riscv64
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#define riscv_cpu_do_transaction_failed riscv_cpu_do_transaction_failed_riscv64
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#define riscv_cpu_do_unaligned_access riscv_cpu_do_unaligned_access_riscv64
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#define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv64
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#define riscv_cpu_do_interrupt riscv_cpu_do_interrupt_riscv64
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#define riscv_get_csr_ops riscv_get_csr_ops_riscv64
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#define riscv_set_csr_ops riscv_set_csr_ops_riscv64
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#define riscv_csrrw riscv_csrrw_riscv64
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#define riscv_csrrw_debug riscv_csrrw_debug_riscv64
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#define riscv_cpu_get_fflags riscv_cpu_get_fflags_riscv64
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#define riscv_cpu_set_fflags riscv_cpu_set_fflags_riscv64
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#define helper_set_rounding_mode helper_set_rounding_mode_riscv64
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#define helper_fmadd_s helper_fmadd_s_riscv64
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#define helper_fmadd_d helper_fmadd_d_riscv64
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#define helper_fmsub_s helper_fmsub_s_riscv64
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#define helper_fmsub_d helper_fmsub_d_riscv64
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#define helper_fnmsub_s helper_fnmsub_s_riscv64
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#define helper_fnmsub_d helper_fnmsub_d_riscv64
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#define helper_fnmadd_s helper_fnmadd_s_riscv64
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#define helper_fnmadd_d helper_fnmadd_d_riscv64
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#define helper_fadd_s helper_fadd_s_riscv64
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#define helper_fsub_s helper_fsub_s_riscv64
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#define helper_fmul_s helper_fmul_s_riscv64
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#define helper_fdiv_s helper_fdiv_s_riscv64
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#define helper_fmin_s helper_fmin_s_riscv64
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#define helper_fmax_s helper_fmax_s_riscv64
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#define helper_fsqrt_s helper_fsqrt_s_riscv64
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#define helper_fle_s helper_fle_s_riscv64
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#define helper_flt_s helper_flt_s_riscv64
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#define helper_feq_s helper_feq_s_riscv64
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#define helper_fcvt_w_s helper_fcvt_w_s_riscv64
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#define helper_fcvt_wu_s helper_fcvt_wu_s_riscv64
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#define helper_fcvt_s_w helper_fcvt_s_w_riscv64
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#define helper_fcvt_s_wu helper_fcvt_s_wu_riscv64
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#define helper_fclass_s helper_fclass_s_riscv64
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#define helper_fadd_d helper_fadd_d_riscv64
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#define helper_fsub_d helper_fsub_d_riscv64
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#define helper_fmul_d helper_fmul_d_riscv64
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#define helper_fdiv_d helper_fdiv_d_riscv64
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#define helper_fmin_d helper_fmin_d_riscv64
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#define helper_fmax_d helper_fmax_d_riscv64
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#define helper_fcvt_s_d helper_fcvt_s_d_riscv64
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#define helper_fcvt_d_s helper_fcvt_d_s_riscv64
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#define helper_fsqrt_d helper_fsqrt_d_riscv64
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#define helper_fle_d helper_fle_d_riscv64
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#define helper_flt_d helper_flt_d_riscv64
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#define helper_feq_d helper_feq_d_riscv64
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#define helper_fcvt_w_d helper_fcvt_w_d_riscv64
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#define helper_fcvt_wu_d helper_fcvt_wu_d_riscv64
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#define helper_fcvt_d_w helper_fcvt_d_w_riscv64
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#define helper_fcvt_d_wu helper_fcvt_d_wu_riscv64
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#define helper_fclass_d helper_fclass_d_riscv64
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#define riscv_raise_exception riscv_raise_exception_riscv64
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#define helper_raise_exception helper_raise_exception_riscv64
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#define helper_uc_riscv_exit helper_uc_riscv_exit_riscv64
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#define helper_csrrw helper_csrrw_riscv64
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#define helper_csrrs helper_csrrs_riscv64
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#define helper_csrrc helper_csrrc_riscv64
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#define helper_sret helper_sret_riscv64
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#define helper_mret helper_mret_riscv64
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#define helper_wfi helper_wfi_riscv64
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#define helper_tlb_flush helper_tlb_flush_riscv64
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#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
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#define pmpcfg_csr_write pmpcfg_csr_write_riscv64
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#define pmpcfg_csr_read pmpcfg_csr_read_riscv64
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#define pmpaddr_csr_write pmpaddr_csr_write_riscv64
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#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
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#define gen_intermediate_code gen_intermediate_code_riscv64
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#define riscv_translate_init riscv_translate_init_riscv64
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#define restore_state_to_opc restore_state_to_opc_riscv64
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#define cpu_riscv_init cpu_riscv_init_riscv64
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#define riscv_reg_reset riscv_reg_reset_riscv64
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#define riscv_reg_read riscv_reg_read_riscv64
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#define riscv_reg_write riscv_reg_write_riscv64
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#define helper_fcvt_l_s helper_fcvt_l_s_riscv64
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#define helper_fcvt_lu_s helper_fcvt_lu_s_riscv64
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#define helper_fcvt_s_l helper_fcvt_s_l_riscv64
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#define helper_fcvt_s_lu helper_fcvt_s_lu_riscv64
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#define helper_fcvt_l_d helper_fcvt_l_d_riscv64
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#define helper_fcvt_lu_d helper_fcvt_lu_d_riscv64
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#define helper_fcvt_d_l helper_fcvt_d_l_riscv64
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#define helper_fcvt_d_lu helper_fcvt_d_lu_riscv64
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#define gen_helper_tlb_flush gen_helper_tlb_flush_riscv64
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#define riscv_fpr_regnames riscv_fpr_regnames_riscv64
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#define riscv_int_regnames riscv_int_regnames_riscv64
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#endif
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