172 lines
6.3 KiB
C
172 lines
6.3 KiB
C
/*
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* Software MMU support
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/*
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* Generate inline load/store functions for all MMU modes (typically
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* at least _user and _kernel) as well as _data versions, for all data
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* sizes.
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*
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* Used by target op helpers.
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*
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* The syntax for the accessors is:
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*
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* load: cpu_ld{sign}{size}_{mmusuffix}(env, ptr)
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* cpu_ld{sign}{size}_{mmusuffix}_ra(env, ptr, retaddr)
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* cpu_ld{sign}{size}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
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*
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* store: cpu_st{size}_{mmusuffix}(env, ptr, val)
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* cpu_st{size}_{mmusuffix}_ra(env, ptr, val, retaddr)
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* cpu_st{size}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
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*
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* sign is:
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* (empty): for 32 and 64 bit sizes
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* u : unsigned
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* s : signed
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*
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* size is:
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* b: 8 bits
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* w: 16 bits
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* l: 32 bits
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* q: 64 bits
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*
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* mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
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* The "mmuidx" suffix carries an extra mmu_idx argument that specifies
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* the index to use; the "data" and "code" suffixes take the index from
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* cpu_mmu_index().
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*/
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#ifndef CPU_LDST_H
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#define CPU_LDST_H
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#include "cpu-defs.h"
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#include "cpu.h"
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typedef target_ulong abi_ptr;
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#define TARGET_ABI_FMT_ptr TARGET_ABI_FMT_lx
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uint32_t cpu_ldub_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_lduw_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_ldl_data(CPUArchState *env, abi_ptr ptr);
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uint64_t cpu_ldq_data(CPUArchState *env, abi_ptr ptr);
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int cpu_ldsb_data(CPUArchState *env, abi_ptr ptr);
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int cpu_ldsw_data(CPUArchState *env, abi_ptr ptr);
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uint32_t cpu_ldub_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
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uint32_t cpu_lduw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
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uint32_t cpu_ldl_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
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uint64_t cpu_ldq_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
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int cpu_ldsb_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
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int cpu_ldsw_data_ra(CPUArchState *env, abi_ptr ptr, uintptr_t retaddr);
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void cpu_stb_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stw_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stl_data(CPUArchState *env, abi_ptr ptr, uint32_t val);
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void cpu_stq_data(CPUArchState *env, abi_ptr ptr, uint64_t val);
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void cpu_stb_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t retaddr);
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void cpu_stw_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t retaddr);
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void cpu_stl_data_ra(CPUArchState *env, abi_ptr ptr,
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uint32_t val, uintptr_t retaddr);
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void cpu_stq_data_ra(CPUArchState *env, abi_ptr ptr,
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uint64_t val, uintptr_t retaddr);
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/* Needed for TCG_OVERSIZED_GUEST */
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#include "tcg/tcg.h"
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static inline target_ulong tlb_addr_write(const CPUTLBEntry *entry)
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{
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return entry->addr_write;
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}
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/* Find the TLB index corresponding to the mmu_idx + address pair. */
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static inline uintptr_t tlb_index(CPUArchState *env, uintptr_t mmu_idx,
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target_ulong addr)
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{
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#ifdef TARGET_ARM
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struct uc_struct *uc = env->uc;
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#endif
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uintptr_t size_mask = env_tlb(env)->f[mmu_idx].mask >> CPU_TLB_ENTRY_BITS;
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return (addr >> TARGET_PAGE_BITS) & size_mask;
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}
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/* Find the TLB entry corresponding to the mmu_idx + address pair. */
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static inline CPUTLBEntry *tlb_entry(CPUArchState *env, uintptr_t mmu_idx,
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target_ulong addr)
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{
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return &env_tlb(env)->f[mmu_idx].table[tlb_index(env, mmu_idx, addr)];
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}
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uint32_t cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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uint32_t cpu_lduw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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uint32_t cpu_ldl_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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uint64_t cpu_ldq_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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int cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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int cpu_ldsw_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra);
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void cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void cpu_stw_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void cpu_stl_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t retaddr);
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void cpu_stq_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
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int mmu_idx, uintptr_t retaddr);
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uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr);
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uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr);
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uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr);
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uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr);
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static inline int cpu_ldsb_code(CPUArchState *env, abi_ptr addr)
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{
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return (int8_t)cpu_ldub_code(env, addr);
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}
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static inline int cpu_ldsw_code(CPUArchState *env, abi_ptr addr)
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{
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return (int16_t)cpu_lduw_code(env, addr);
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}
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/**
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* tlb_vaddr_to_host:
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* @env: CPUArchState
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* @addr: guest virtual address to look up
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* @access_type: 0 for read, 1 for write, 2 for execute
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* @mmu_idx: MMU index to use for lookup
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*
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* Look up the specified guest virtual index in the TCG softmmu TLB.
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* If we can translate a host virtual address suitable for direct RAM
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* access, without causing a guest exception, then return it.
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* Otherwise (TLB entry is for an I/O access, guest software
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* TLB fill required, etc) return NULL.
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*/
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void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
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MMUAccessType access_type, int mmu_idx);
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#endif /* CPU_LDST_H */
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