352 lines
9.7 KiB
C
352 lines
9.7 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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/* Modified for Unicorn Engine by Chen Huitao<chenhuitao@hfmrit.com>, 2020 */
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#include "uc_priv.h"
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#include "sysemu/cpus.h"
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#include "cpu.h"
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#include "unicorn_common.h"
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#include "cpu_bits.h"
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#include <unicorn/riscv.h>
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#include "unicorn.h"
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RISCVCPU *cpu_riscv_init(struct uc_struct *uc, const char *cpu_model);
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static void riscv_set_pc(struct uc_struct *uc, uint64_t address)
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{
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RISCV_CPU(uc->cpu)->env.pc = address;
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}
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static void riscv_release(void *ctx)
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{
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int i;
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TCGContext *tcg_ctx = (TCGContext *)ctx;
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RISCVCPU *cpu = (RISCVCPU *)tcg_ctx->uc->cpu;
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CPUTLBDesc *d = cpu->neg.tlb.d;
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CPUTLBDescFast *f = cpu->neg.tlb.f;
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CPUTLBDesc *desc;
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CPUTLBDescFast *fast;
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release_common(ctx);
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for (i = 0; i < NB_MMU_MODES; i++) {
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desc = &(d[i]);
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fast = &(f[i]);
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g_free(desc->iotlb);
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g_free(fast->table);
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}
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}
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void riscv_reg_reset(struct uc_struct *uc)
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{
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}
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static void reg_read(CPURISCVState *env, unsigned int regid, void *value)
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{
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switch(regid) {
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case UC_RISCV_REG_X0:
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case UC_RISCV_REG_X1:
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case UC_RISCV_REG_X2:
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case UC_RISCV_REG_X3:
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case UC_RISCV_REG_X4:
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case UC_RISCV_REG_X5:
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case UC_RISCV_REG_X6:
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case UC_RISCV_REG_X7:
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case UC_RISCV_REG_X8:
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case UC_RISCV_REG_X9:
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case UC_RISCV_REG_X10:
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case UC_RISCV_REG_X11:
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case UC_RISCV_REG_X12:
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case UC_RISCV_REG_X13:
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case UC_RISCV_REG_X14:
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case UC_RISCV_REG_X15:
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case UC_RISCV_REG_X16:
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case UC_RISCV_REG_X17:
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case UC_RISCV_REG_X18:
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case UC_RISCV_REG_X19:
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case UC_RISCV_REG_X20:
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case UC_RISCV_REG_X21:
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case UC_RISCV_REG_X22:
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case UC_RISCV_REG_X23:
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case UC_RISCV_REG_X24:
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case UC_RISCV_REG_X25:
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case UC_RISCV_REG_X26:
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case UC_RISCV_REG_X27:
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case UC_RISCV_REG_X28:
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case UC_RISCV_REG_X29:
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case UC_RISCV_REG_X30:
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case UC_RISCV_REG_X31:
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#ifdef TARGET_RISCV64
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*(int64_t *)value = env->gpr[regid - UC_RISCV_REG_X0];
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#else
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*(int32_t *)value = env->gpr[regid - UC_RISCV_REG_X0];
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#endif
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break;
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case UC_RISCV_REG_PC:
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#ifdef TARGET_RISCV64
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*(int64_t *)value = env->pc;
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#else
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*(int32_t *)value = env->pc;
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#endif
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break;
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case UC_RISCV_REG_F0: // "ft0"
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case UC_RISCV_REG_F1: // "ft1"
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case UC_RISCV_REG_F2: // "ft2"
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case UC_RISCV_REG_F3: // "ft3"
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case UC_RISCV_REG_F4: // "ft4"
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case UC_RISCV_REG_F5: // "ft5"
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case UC_RISCV_REG_F6: // "ft6"
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case UC_RISCV_REG_F7: // "ft7"
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case UC_RISCV_REG_F8: // "fs0"
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case UC_RISCV_REG_F9: // "fs1"
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case UC_RISCV_REG_F10: // "fa0"
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case UC_RISCV_REG_F11: // "fa1"
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case UC_RISCV_REG_F12: // "fa2"
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case UC_RISCV_REG_F13: // "fa3"
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case UC_RISCV_REG_F14: // "fa4"
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case UC_RISCV_REG_F15: // "fa5"
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case UC_RISCV_REG_F16: // "fa6"
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case UC_RISCV_REG_F17: // "fa7"
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case UC_RISCV_REG_F18: // "fs2"
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case UC_RISCV_REG_F19: // "fs3"
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case UC_RISCV_REG_F20: // "fs4"
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case UC_RISCV_REG_F21: // "fs5"
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case UC_RISCV_REG_F22: // "fs6"
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case UC_RISCV_REG_F23: // "fs7"
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case UC_RISCV_REG_F24: // "fs8"
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case UC_RISCV_REG_F25: // "fs9"
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case UC_RISCV_REG_F26: // "fs10"
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case UC_RISCV_REG_F27: // "fs11"
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case UC_RISCV_REG_F28: // "ft8"
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case UC_RISCV_REG_F29: // "ft9"
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case UC_RISCV_REG_F30: // "ft10"
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case UC_RISCV_REG_F31: // "ft11"
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#ifdef TARGET_RISCV64
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*(int64_t *)value = env->fpr[regid - UC_RISCV_REG_F0];
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#else
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*(int32_t *)value = env->fpr[regid - UC_RISCV_REG_F0];
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#endif
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break;
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default:
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break;
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}
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return;
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}
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static void reg_write(CPURISCVState *env, unsigned int regid, const void *value)
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{
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switch(regid) {
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case UC_RISCV_REG_X0:
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case UC_RISCV_REG_X1:
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case UC_RISCV_REG_X2:
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case UC_RISCV_REG_X3:
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case UC_RISCV_REG_X4:
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case UC_RISCV_REG_X5:
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case UC_RISCV_REG_X6:
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case UC_RISCV_REG_X7:
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case UC_RISCV_REG_X8:
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case UC_RISCV_REG_X9:
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case UC_RISCV_REG_X10:
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case UC_RISCV_REG_X11:
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case UC_RISCV_REG_X12:
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case UC_RISCV_REG_X13:
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case UC_RISCV_REG_X14:
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case UC_RISCV_REG_X15:
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case UC_RISCV_REG_X16:
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case UC_RISCV_REG_X17:
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case UC_RISCV_REG_X18:
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case UC_RISCV_REG_X19:
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case UC_RISCV_REG_X20:
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case UC_RISCV_REG_X21:
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case UC_RISCV_REG_X22:
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case UC_RISCV_REG_X23:
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case UC_RISCV_REG_X24:
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case UC_RISCV_REG_X25:
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case UC_RISCV_REG_X26:
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case UC_RISCV_REG_X27:
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case UC_RISCV_REG_X28:
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case UC_RISCV_REG_X29:
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case UC_RISCV_REG_X30:
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case UC_RISCV_REG_X31:
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#ifdef TARGET_RISCV64
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env->gpr[regid - UC_RISCV_REG_X0] = *(uint64_t *)value;
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#else
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env->gpr[regid - UC_RISCV_REG_X0] = *(uint32_t *)value;
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#endif
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break;
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case UC_RISCV_REG_PC:
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#ifdef TARGET_RISCV64
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env->pc = *(uint64_t *)value;
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#else
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env->pc = *(uint32_t *)value;
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#endif
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break;
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case UC_RISCV_REG_F0: // "ft0"
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case UC_RISCV_REG_F1: // "ft1"
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case UC_RISCV_REG_F2: // "ft2"
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case UC_RISCV_REG_F3: // "ft3"
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case UC_RISCV_REG_F4: // "ft4"
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case UC_RISCV_REG_F5: // "ft5"
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case UC_RISCV_REG_F6: // "ft6"
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case UC_RISCV_REG_F7: // "ft7"
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case UC_RISCV_REG_F8: // "fs0"
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case UC_RISCV_REG_F9: // "fs1"
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case UC_RISCV_REG_F10: // "fa0"
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case UC_RISCV_REG_F11: // "fa1"
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case UC_RISCV_REG_F12: // "fa2"
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case UC_RISCV_REG_F13: // "fa3"
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case UC_RISCV_REG_F14: // "fa4"
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case UC_RISCV_REG_F15: // "fa5"
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case UC_RISCV_REG_F16: // "fa6"
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case UC_RISCV_REG_F17: // "fa7"
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case UC_RISCV_REG_F18: // "fs2"
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case UC_RISCV_REG_F19: // "fs3"
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case UC_RISCV_REG_F20: // "fs4"
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case UC_RISCV_REG_F21: // "fs5"
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case UC_RISCV_REG_F22: // "fs6"
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case UC_RISCV_REG_F23: // "fs7"
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case UC_RISCV_REG_F24: // "fs8"
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case UC_RISCV_REG_F25: // "fs9"
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case UC_RISCV_REG_F26: // "fs10"
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case UC_RISCV_REG_F27: // "fs11"
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case UC_RISCV_REG_F28: // "ft8"
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case UC_RISCV_REG_F29: // "ft9"
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case UC_RISCV_REG_F30: // "ft10"
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case UC_RISCV_REG_F31: // "ft11"
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#ifdef TARGET_RISCV64
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env->fpr[regid - UC_RISCV_REG_F0] = *(uint64_t *)value;
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#else
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env->fpr[regid - UC_RISCV_REG_F0] = *(uint32_t *)value;
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#endif
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break;
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default:
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break;
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}
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}
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int riscv_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count)
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{
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CPURISCVState *env = &(RISCV_CPU(uc->cpu)->env);
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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void *value = vals[i];
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reg_read(env, regid, value);
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}
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return 0;
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}
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int riscv_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count)
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{
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CPURISCVState *env = &(RISCV_CPU(uc->cpu)->env);
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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const void *value = vals[i];
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reg_write(env, regid, value);
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if(regid == UC_RISCV_REG_PC){
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// force to quit execution and flush TB
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uc->quit_request = true;
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uc_emu_stop(uc);
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}
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}
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return 0;
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}
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DEFAULT_VISIBILITY
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#ifdef TARGET_RISCV32
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int riscv32_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
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#else
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/* TARGET_RISCV64 */
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int riscv64_context_reg_read(struct uc_context *ctx, unsigned int *regs, void **vals, int count)
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#endif
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{
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CPURISCVState *env = (CPURISCVState *)ctx->data;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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void *value = vals[i];
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reg_read(env, regid, value);
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}
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return 0;
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}
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DEFAULT_VISIBILITY
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#ifdef TARGET_RISCV32
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int riscv32_context_reg_write(struct uc_context *ctx, unsigned int *regs, void *const *vals, int count)
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#else
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/* TARGET_RISCV64 */
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int riscv64_context_reg_write(struct uc_context *ctx, unsigned int *regs, void *const *vals, int count)
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#endif
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{
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CPURISCVState *env = (CPURISCVState *)ctx->data;
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int i;
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for (i = 0; i < count; i++) {
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unsigned int regid = regs[i];
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const void *value = vals[i];
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reg_write(env, regid, value);
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}
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return 0;
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}
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static bool riscv_stop_interrupt(struct uc_struct *uc, int intno)
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{
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// detect stop exception
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switch(intno){
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default:
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return false;
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case RISCV_EXCP_UNICORN_END:
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return true;
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case RISCV_EXCP_BREAKPOINT:
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uc->invalid_error = UC_ERR_EXCEPTION;
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return true;
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}
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}
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static bool riscv_insn_hook_validate(uint32_t insn_enum)
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{
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return false;
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}
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static int riscv_cpus_init(struct uc_struct *uc, const char *cpu_model)
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{
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RISCVCPU *cpu;
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cpu = cpu_riscv_init(uc, cpu_model);
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if (cpu == NULL) {
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return -1;
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}
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return 0;
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}
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DEFAULT_VISIBILITY
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#ifdef TARGET_RISCV32
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void riscv32_uc_init(struct uc_struct* uc)
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#else
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/* TARGET_RISCV64 */
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void riscv64_uc_init(struct uc_struct* uc)
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#endif
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{
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uc->reg_read = riscv_reg_read;
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uc->reg_write = riscv_reg_write;
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uc->reg_reset = riscv_reg_reset;
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uc->release = riscv_release;
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uc->set_pc = riscv_set_pc;
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uc->stop_interrupt = riscv_stop_interrupt;
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uc->insn_hook_validate = riscv_insn_hook_validate;
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uc->cpus_init = riscv_cpus_init;
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uc->cpu_context_size = offsetof(CPURISCVState, rdtime_fn);
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uc_common_init(uc);
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}
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