974 lines
42 KiB
C
974 lines
42 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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#include "hw/boards.h"
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#include "sysemu/cpus.h"
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#include "hw/i386/pc.h"
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#include "unicorn.h"
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#include "cpu.h"
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#include "tcg.h"
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#include "unicorn_common.h"
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#define READ_QWORD(x) ((uint64)x)
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#define READ_DWORD(x) (x & 0xffffffff)
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#define READ_WORD(x) (x & 0xffff)
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#define READ_BYTE_H(x) ((x & 0xffff) >> 8)
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#define READ_BYTE_L(x) (x & 0xff)
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static void x86_set_pc(struct uc_struct *uc, uint64_t address)
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{
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((CPUX86State *)uc->current_cpu->env_ptr)->eip = address;
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}
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void x86_release(void *ctx);
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void x86_release(void *ctx)
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{
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release_common(ctx);
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TCGContext *s = (TCGContext *) ctx;
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// arch specific
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g_free(s->cpu_A0);
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g_free(s->cpu_T[0]);
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g_free(s->cpu_T[1]);
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g_free(s->cpu_tmp0);
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g_free(s->cpu_tmp4);
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g_free(s->cpu_cc_srcT);
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g_free(s->cpu_cc_dst);
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g_free(s->cpu_cc_src);
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g_free(s->cpu_cc_src2);
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int i;
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for (i = 0; i < CPU_NB_REGS; ++i) {
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g_free(s->cpu_regs[i]);
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}
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g_free(s->tb_ctx.tbs);
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}
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void x86_reg_reset(struct uc_struct *uc)
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{
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CPUArchState *env = first_cpu->env_ptr;
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env->features[FEAT_1_EDX] = CPUID_CX8 | CPUID_CMOV | CPUID_SSE2 | CPUID_FXSR | CPUID_SSE | CPUID_CLFLUSH;
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env->features[FEAT_1_ECX] = CPUID_EXT_SSSE3 | CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_AES;
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env->features[FEAT_8000_0001_EDX] = CPUID_EXT2_3DNOW | CPUID_EXT2_RDTSCP;
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env->features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM | CPUID_EXT3_ABM | CPUID_EXT3_SKINIT | CPUID_EXT3_CR8LEG;
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env->features[FEAT_7_0_EBX] = CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP;
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env->invalid_error = UC_ERR_OK; // no error
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memset(env->regs, 0, sizeof(env->regs));
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memset(env->segs, 0, sizeof(env->segs));
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memset(env->cr, 0, sizeof(env->cr));
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memset(&env->ldt, 0, sizeof(env->ldt));
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memset(&env->gdt, 0, sizeof(env->gdt));
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memset(&env->tr, 0, sizeof(env->tr));
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memset(&env->idt, 0, sizeof(env->idt));
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env->eip = 0;
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env->eflags = 0;
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env->eflags0 = 0;
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env->fpstt = 0; /* top of stack index */
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env->fpus = 0;
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env->fpuc = 0;
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memset(env->fptags, 0, sizeof(env->fptags)); /* 0 = valid, 1 = empty */
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env->mxcsr = 0;
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memset(env->xmm_regs, 0, sizeof(env->xmm_regs));
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memset(&env->xmm_t0, 0, sizeof(env->xmm_t0));
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memset(&env->mmx_t0, 0, sizeof(env->mmx_t0));
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memset(env->ymmh_regs, 0, sizeof(env->ymmh_regs));
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memset(env->opmask_regs, 0, sizeof(env->opmask_regs));
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memset(env->zmmh_regs, 0, sizeof(env->zmmh_regs));
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/* sysenter registers */
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env->sysenter_cs = 0;
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env->sysenter_esp = 0;
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env->sysenter_eip = 0;
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env->efer = 0;
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env->star = 0;
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env->vm_hsave = 0;
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env->tsc = 0;
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env->tsc_adjust = 0;
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env->tsc_deadline = 0;
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env->mcg_status = 0;
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env->msr_ia32_misc_enable = 0;
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env->msr_ia32_feature_control = 0;
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env->msr_fixed_ctr_ctrl = 0;
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env->msr_global_ctrl = 0;
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env->msr_global_status = 0;
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env->msr_global_ovf_ctrl = 0;
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memset(env->msr_fixed_counters, 0, sizeof(env->msr_fixed_counters));
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memset(env->msr_gp_counters, 0, sizeof(env->msr_gp_counters));
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memset(env->msr_gp_evtsel, 0, sizeof(env->msr_gp_evtsel));
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#ifdef TARGET_X86_64
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memset(env->hi16_zmm_regs, 0, sizeof(env->hi16_zmm_regs));
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env->lstar = 0;
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env->cstar = 0;
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env->fmask = 0;
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env->kernelgsbase = 0;
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#endif
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// TODO: reset other registers in CPUX86State qemu/target-i386/cpu.h
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// properly initialize internal setup for each mode
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switch(uc->mode) {
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default:
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break;
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case UC_MODE_16:
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env->hflags = 0;
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env->cr[0] = 0;
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break;
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case UC_MODE_32:
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env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_OSFXSR_MASK;
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env->cr[0] = CR0_PE_MASK; // protected mode
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break;
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case UC_MODE_64:
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env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK | HF_LMA_MASK | HF_OSFXSR_MASK;
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env->hflags &= ~(HF_ADDSEG_MASK);
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env->cr[0] = CR0_PE_MASK; // protected mode
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break;
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}
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}
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int x86_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
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{
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CPUState *mycpu = first_cpu;
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switch(uc->mode) {
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default:
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break;
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case UC_MODE_16:
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switch(regid) {
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default: break;
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case UC_X86_REG_ES:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_ES].selector;
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return 0;
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case UC_X86_REG_SS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_SS].selector;
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return 0;
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case UC_X86_REG_DS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_DS].selector;
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return 0;
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case UC_X86_REG_FS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_FS].selector;
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return 0;
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case UC_X86_REG_GS:
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*(int16_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].selector;
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return 0;
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}
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// fall-thru
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case UC_MODE_32:
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switch(regid) {
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default:
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break;
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case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0];
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break;
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case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0];
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break;
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case UC_X86_REG_EFLAGS:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.eflags;
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break;
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case UC_X86_REG_EAX:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EAX];
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break;
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case UC_X86_REG_AX:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
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break;
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case UC_X86_REG_AH:
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*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
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break;
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case UC_X86_REG_AL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
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break;
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case UC_X86_REG_EBX:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EBX];
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break;
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case UC_X86_REG_BX:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
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break;
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case UC_X86_REG_BH:
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*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
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break;
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case UC_X86_REG_BL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
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break;
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case UC_X86_REG_ECX:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ECX];
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break;
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case UC_X86_REG_CX:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
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break;
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case UC_X86_REG_CH:
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*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
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break;
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case UC_X86_REG_CL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
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break;
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case UC_X86_REG_EDX:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EDX];
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break;
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case UC_X86_REG_DX:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
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break;
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case UC_X86_REG_DH:
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*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
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break;
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case UC_X86_REG_DL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
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break;
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case UC_X86_REG_ESP:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ESP];
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break;
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case UC_X86_REG_SP:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP]);
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break;
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case UC_X86_REG_EBP:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EBP];
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break;
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case UC_X86_REG_BP:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP]);
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break;
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case UC_X86_REG_ESI:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ESI];
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break;
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case UC_X86_REG_SI:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI]);
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break;
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case UC_X86_REG_EDI:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EDI];
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break;
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case UC_X86_REG_DI:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI]);
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break;
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case UC_X86_REG_EIP:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.eip;
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break;
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case UC_X86_REG_IP:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.eip);
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break;
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case UC_X86_REG_CS:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_CS].base;
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break;
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case UC_X86_REG_DS:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_DS].base;
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break;
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case UC_X86_REG_SS:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_SS].base;
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break;
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case UC_X86_REG_ES:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_ES].base;
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break;
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case UC_X86_REG_FS:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_FS].base;
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break;
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case UC_X86_REG_GS:
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].base;
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break;
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}
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break;
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#ifdef TARGET_X86_64
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case UC_MODE_64:
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switch(regid) {
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default:
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break;
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case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
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*(int64_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0];
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break;
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case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
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*(int64_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0];
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break;
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case UC_X86_REG_EFLAGS:
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*(int64_t *)value = X86_CPU(uc, mycpu)->env.eflags;
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break;
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case UC_X86_REG_RAX:
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*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EAX];
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break;
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case UC_X86_REG_EAX:
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*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
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break;
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case UC_X86_REG_AX:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
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break;
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case UC_X86_REG_AH:
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*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
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break;
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case UC_X86_REG_AL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX]);
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break;
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case UC_X86_REG_RBX:
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*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EBX];
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break;
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case UC_X86_REG_EBX:
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*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
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break;
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case UC_X86_REG_BX:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
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break;
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case UC_X86_REG_BH:
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*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
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break;
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case UC_X86_REG_BL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX]);
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break;
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case UC_X86_REG_RCX:
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*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ECX];
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break;
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case UC_X86_REG_ECX:
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*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
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break;
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case UC_X86_REG_CX:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
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break;
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case UC_X86_REG_CH:
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*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
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break;
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case UC_X86_REG_CL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX]);
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break;
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case UC_X86_REG_RDX:
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*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EDX];
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break;
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case UC_X86_REG_EDX:
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*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
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break;
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case UC_X86_REG_DX:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
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break;
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case UC_X86_REG_DH:
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*(int8_t *)value = READ_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
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break;
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case UC_X86_REG_DL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX]);
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break;
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case UC_X86_REG_RSP:
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*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ESP];
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break;
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case UC_X86_REG_ESP:
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*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESP]);
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break;
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case UC_X86_REG_SP:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP]);
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break;
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case UC_X86_REG_SPL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESP]);
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break;
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case UC_X86_REG_RBP:
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*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EBP];
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break;
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case UC_X86_REG_EBP:
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*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBP]);
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break;
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case UC_X86_REG_BP:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP]);
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break;
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case UC_X86_REG_BPL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBP]);
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break;
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case UC_X86_REG_RSI:
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*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_ESI];
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break;
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case UC_X86_REG_ESI:
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*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESI]);
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break;
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case UC_X86_REG_SI:
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*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI]);
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break;
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case UC_X86_REG_SIL:
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESI]);
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break;
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case UC_X86_REG_RDI:
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*(uint64_t *)value = X86_CPU(uc, mycpu)->env.regs[R_EDI];
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break;
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case UC_X86_REG_EDI:
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*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDI]);
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break;
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case UC_X86_REG_DI:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI]);
|
|
break;
|
|
case UC_X86_REG_DIL:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDI]);
|
|
break;
|
|
case UC_X86_REG_RIP:
|
|
*(uint64_t *)value = X86_CPU(uc, mycpu)->env.eip;
|
|
break;
|
|
case UC_X86_REG_EIP:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.eip);
|
|
break;
|
|
case UC_X86_REG_IP:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.eip);
|
|
break;
|
|
case UC_X86_REG_CS:
|
|
*(int64_t *)value = X86_CPU(uc, mycpu)->env.segs[R_CS].base;
|
|
break;
|
|
case UC_X86_REG_DS:
|
|
*(int64_t *)value = X86_CPU(uc, mycpu)->env.segs[R_DS].base;
|
|
break;
|
|
case UC_X86_REG_SS:
|
|
*(int64_t *)value = X86_CPU(uc, mycpu)->env.segs[R_SS].base;
|
|
break;
|
|
case UC_X86_REG_ES:
|
|
*(int64_t *)value = X86_CPU(uc, mycpu)->env.segs[R_ES].base;
|
|
break;
|
|
case UC_X86_REG_FS:
|
|
*(int64_t *)value = X86_CPU(uc, mycpu)->env.segs[R_FS].base;
|
|
break;
|
|
case UC_X86_REG_GS:
|
|
*(int64_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].base;
|
|
break;
|
|
case UC_X86_REG_R8:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[8]);
|
|
break;
|
|
case UC_X86_REG_R8D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[8]);
|
|
break;
|
|
case UC_X86_REG_R8W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[8]);
|
|
break;
|
|
case UC_X86_REG_R8B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[8]);
|
|
break;
|
|
case UC_X86_REG_R9:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[9]);
|
|
break;
|
|
case UC_X86_REG_R9D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[9]);
|
|
break;
|
|
case UC_X86_REG_R9W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[9]);
|
|
break;
|
|
case UC_X86_REG_R9B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[9]);
|
|
break;
|
|
case UC_X86_REG_R10:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[10]);
|
|
break;
|
|
case UC_X86_REG_R10D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[10]);
|
|
break;
|
|
case UC_X86_REG_R10W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[10]);
|
|
break;
|
|
case UC_X86_REG_R10B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[10]);
|
|
break;
|
|
case UC_X86_REG_R11:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[11]);
|
|
break;
|
|
case UC_X86_REG_R11D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[11]);
|
|
break;
|
|
case UC_X86_REG_R11W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[11]);
|
|
break;
|
|
case UC_X86_REG_R11B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[11]);
|
|
break;
|
|
case UC_X86_REG_R12:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[12]);
|
|
break;
|
|
case UC_X86_REG_R12D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[12]);
|
|
break;
|
|
case UC_X86_REG_R12W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[12]);
|
|
break;
|
|
case UC_X86_REG_R12B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[12]);
|
|
break;
|
|
case UC_X86_REG_R13:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[13]);
|
|
break;
|
|
case UC_X86_REG_R13D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[13]);
|
|
break;
|
|
case UC_X86_REG_R13W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[13]);
|
|
break;
|
|
case UC_X86_REG_R13B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[13]);
|
|
break;
|
|
case UC_X86_REG_R14:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[14]);
|
|
break;
|
|
case UC_X86_REG_R14D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[14]);
|
|
break;
|
|
case UC_X86_REG_R14W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[14]);
|
|
break;
|
|
case UC_X86_REG_R14B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[14]);
|
|
break;
|
|
case UC_X86_REG_R15:
|
|
*(int64_t *)value = READ_QWORD(X86_CPU(uc, mycpu)->env.regs[15]);
|
|
break;
|
|
case UC_X86_REG_R15D:
|
|
*(int32_t *)value = READ_DWORD(X86_CPU(uc, mycpu)->env.regs[15]);
|
|
break;
|
|
case UC_X86_REG_R15W:
|
|
*(int16_t *)value = READ_WORD(X86_CPU(uc, mycpu)->env.regs[15]);
|
|
break;
|
|
case UC_X86_REG_R15B:
|
|
*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15]);
|
|
break;
|
|
}
|
|
break;
|
|
#endif
|
|
}
|
|
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
#define WRITE_DWORD(x, w) (x = (x & ~0xffffffff) | (w & 0xffffffff))
|
|
#define WRITE_WORD(x, w) (x = (x & ~0xffff) | (w & 0xffff))
|
|
#define WRITE_BYTE_H(x, b) (x = (x & ~0xff00) | (b & 0xff))
|
|
#define WRITE_BYTE_L(x, b) (x = (x & ~0xff) | (b & 0xff))
|
|
|
|
int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
|
|
{
|
|
CPUState *mycpu = first_cpu;
|
|
|
|
switch(uc->mode) {
|
|
default:
|
|
break;
|
|
|
|
case UC_MODE_16:
|
|
switch(regid) {
|
|
default: break;
|
|
case UC_X86_REG_ES:
|
|
X86_CPU(uc, mycpu)->env.segs[R_ES].selector = *(uint16_t *)value;
|
|
return 0;
|
|
case UC_X86_REG_SS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_SS].selector = *(uint16_t *)value;
|
|
return 0;
|
|
case UC_X86_REG_DS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_DS].selector = *(uint16_t *)value;
|
|
return 0;
|
|
case UC_X86_REG_FS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_FS].selector = *(uint16_t *)value;
|
|
return 0;
|
|
case UC_X86_REG_GS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_GS].selector = *(uint16_t *)value;
|
|
return 0;
|
|
}
|
|
// fall-thru
|
|
case UC_MODE_32:
|
|
switch(regid) {
|
|
default:
|
|
break;
|
|
case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
|
|
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
|
|
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_EFLAGS:
|
|
X86_CPU(uc, mycpu)->env.eflags = *(uint32_t *)value;
|
|
X86_CPU(uc, mycpu)->env.eflags0 = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_EAX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_AX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_AH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_AL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_EBX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_BX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_BH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_BL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_ECX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_CX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_CH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_CL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_EDX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_DX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_DH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_DL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_ESP:
|
|
X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_SP:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_EBP:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_BP:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_ESI:
|
|
X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_SI:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_EDI:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_DI:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_EIP:
|
|
X86_CPU(uc, mycpu)->env.eip = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_IP:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_CS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_DS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_SS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_ES:
|
|
X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_FS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(uint32_t *)value;
|
|
break;
|
|
case UC_X86_REG_GS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint32_t *)value;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
#ifdef TARGET_X86_64
|
|
case UC_MODE_64:
|
|
switch(regid) {
|
|
default:
|
|
break;
|
|
case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
|
|
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
|
|
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EFLAGS:
|
|
X86_CPU(uc, mycpu)->env.eflags = *(uint64_t *)value;
|
|
X86_CPU(uc, mycpu)->env.eflags0 = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_RAX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EAX:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_AX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_AH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_AL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RBX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EBX:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_BX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_BH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_BL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RCX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_ECX:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_CX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_CH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_CL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RDX:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EDX:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_DX:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_DH:
|
|
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_DL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RSP:
|
|
X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_ESP:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_SP:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_SPL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RBP:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EBP:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_BP:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_BPL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RSI:
|
|
X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_ESI:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_SI:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_SIL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RDI:
|
|
X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EDI:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_DI:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_DIL:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_RIP:
|
|
X86_CPU(uc, mycpu)->env.eip = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_EIP:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.eip, *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_IP:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_CS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_DS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_SS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_ES:
|
|
X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_FS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_GS:
|
|
X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R8:
|
|
X86_CPU(uc, mycpu)->env.regs[8] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R8D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[8], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R8W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[8], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R8B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[8], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R9:
|
|
X86_CPU(uc, mycpu)->env.regs[9] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R9D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[9], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R9W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[9], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R9B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[9], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R10:
|
|
X86_CPU(uc, mycpu)->env.regs[10] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R10D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[10], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R10W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[10], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R10B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[10], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R11:
|
|
X86_CPU(uc, mycpu)->env.regs[11] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R11D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[11], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R11W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[11], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R11B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[11], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R12:
|
|
X86_CPU(uc, mycpu)->env.regs[12] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R12D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[12], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R12W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[12], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R12B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[12], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R13:
|
|
X86_CPU(uc, mycpu)->env.regs[13] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R13D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[13], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R13W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[13], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R13B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[13], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R14:
|
|
X86_CPU(uc, mycpu)->env.regs[14] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R14D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[14], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R14W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[14], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R14B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[14], *(uint8_t *)value);
|
|
break;
|
|
case UC_X86_REG_R15:
|
|
X86_CPU(uc, mycpu)->env.regs[15] = *(uint64_t *)value;
|
|
break;
|
|
case UC_X86_REG_R15D:
|
|
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[15], *(uint32_t *)value);
|
|
break;
|
|
case UC_X86_REG_R15W:
|
|
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[15], *(uint16_t *)value);
|
|
break;
|
|
case UC_X86_REG_R15B:
|
|
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15], *(uint8_t *)value);
|
|
break;
|
|
}
|
|
break;
|
|
#endif
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
__attribute__ ((visibility ("default")))
|
|
int x86_uc_machine_init(struct uc_struct *uc)
|
|
{
|
|
return machine_initialize(uc);
|
|
}
|
|
|
|
static bool x86_stop_interrupt(int intno)
|
|
{
|
|
switch(intno) {
|
|
default:
|
|
return false;
|
|
case EXCP06_ILLOP:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
void pc_machine_init(struct uc_struct *uc);
|
|
|
|
__attribute__ ((visibility ("default")))
|
|
void x86_uc_init(struct uc_struct* uc)
|
|
{
|
|
apic_register_types(uc);
|
|
apic_common_register_types(uc);
|
|
register_accel_types(uc);
|
|
pc_machine_register_types(uc);
|
|
x86_cpu_register_types(uc);
|
|
pc_machine_init(uc); // pc_piix
|
|
uc->reg_read = x86_reg_read;
|
|
uc->reg_write = x86_reg_write;
|
|
uc->reg_reset = x86_reg_reset;
|
|
uc->release = x86_release;
|
|
uc->set_pc = x86_set_pc;
|
|
uc->stop_interrupt = x86_stop_interrupt;
|
|
uc_common_init(uc);
|
|
}
|