560 lines
16 KiB
C
560 lines
16 KiB
C
#include "unicorn_test.h"
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const uint64_t code_start = 0x1000;
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const uint64_t code_len = 0x4000;
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static void uc_common_setup(uc_engine **uc, uc_arch arch, uc_mode mode,
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const char *code, uint64_t size)
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{
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OK(uc_open(arch, mode, uc));
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OK(uc_mem_map(*uc, code_start, code_len, UC_PROT_ALL));
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OK(uc_mem_write(*uc, code_start, code, size));
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}
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static void test_riscv32_nop(void)
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{
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uc_engine *uc;
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char code[] = "\x13\x00\x00\x00"; // nop
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uint32_t r_t0 = 0x1234;
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uint32_t r_t1 = 0x5678;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
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sizeof(code) - 1);
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
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TEST_CHECK(r_t0 == 0x1234);
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TEST_CHECK(r_t1 == 0x5678);
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OK(uc_close(uc));
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}
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static void test_riscv64_nop(void)
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{
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uc_engine *uc;
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char code[] = "\x13\x00\x00\x00"; // nop
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uint64_t r_t0 = 0x1234;
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uint64_t r_t1 = 0x5678;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
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TEST_CHECK(r_t0 == 0x1234);
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TEST_CHECK(r_t1 == 0x5678);
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OK(uc_close(uc));
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}
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static void test_riscv32_until_pc_update(void)
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{
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uc_engine *uc;
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char code[] = "\x93\x02\x10\x00\x13\x03\x00\x02\x13\x01\x81\x00";
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/*
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addi t0, zero, 1
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addi t1, zero, 0x20
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addi sp, sp, 8
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*/
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uint32_t r_t0 = 0x1234;
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uint32_t r_t1 = 0x7890;
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uint32_t r_pc = 0x0000;
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uint32_t r_sp = 0x1234;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_write(uc, UC_RISCV_REG_SP, &r_sp));
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// emulate the three instructions
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_read(uc, UC_RISCV_REG_SP, &r_sp));
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OK(uc_reg_read(uc, UC_RISCV_REG_PC, &r_pc));
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TEST_CHECK(r_t0 == 0x1);
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TEST_CHECK(r_t1 == 0x20);
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TEST_CHECK(r_sp == 0x123c);
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TEST_CHECK(r_pc == (code_start + sizeof(code) - 1));
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OK(uc_close(uc));
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}
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static void test_riscv64_until_pc_update(void)
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{
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uc_engine *uc;
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char code[] = "\x93\x02\x10\x00\x13\x03\x00\x02\x13\x01\x81\x00";
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/*
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addi t0, zero, 1
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addi t1, zero, 0x20
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addi sp, sp, 8
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*/
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uint64_t r_t0 = 0x1234;
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uint64_t r_t1 = 0x7890;
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uint64_t r_pc = 0x0000;
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uint64_t r_sp = 0x1234;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_write(uc, UC_RISCV_REG_SP, &r_sp));
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// emulate the three instructions
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_read(uc, UC_RISCV_REG_SP, &r_sp));
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OK(uc_reg_read(uc, UC_RISCV_REG_PC, &r_pc));
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TEST_CHECK(r_t0 == 0x1);
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TEST_CHECK(r_t1 == 0x20);
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TEST_CHECK(r_sp == 0x123c);
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TEST_CHECK(r_pc == (code_start + sizeof(code) - 1));
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OK(uc_close(uc));
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}
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static void test_riscv32_3steps_pc_update(void)
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{
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uc_engine *uc;
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char code[] = "\x93\x02\x10\x00\x13\x03\x00\x02\x13\x01\x81\x00";
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/*
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addi t0, zero, 1
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addi t1, zero, 0x20
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addi sp, sp, 8
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*/
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uint32_t r_t0 = 0x1234;
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uint32_t r_t1 = 0x7890;
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uint32_t r_pc = 0x0000;
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uint32_t r_sp = 0x1234;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_write(uc, UC_RISCV_REG_SP, &r_sp));
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// emulate the three instructions
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OK(uc_emu_start(uc, code_start, -1, 0, 3));
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_read(uc, UC_RISCV_REG_SP, &r_sp));
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OK(uc_reg_read(uc, UC_RISCV_REG_PC, &r_pc));
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TEST_CHECK(r_t0 == 0x1);
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TEST_CHECK(r_t1 == 0x20);
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TEST_CHECK(r_sp == 0x123c);
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TEST_CHECK(r_pc == (code_start + sizeof(code) - 1));
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OK(uc_close(uc));
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}
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static void test_riscv64_3steps_pc_update(void)
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{
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uc_engine *uc;
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char code[] = "\x93\x02\x10\x00\x13\x03\x00\x02\x13\x01\x81\x00";
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/*
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addi t0, zero, 1
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addi t1, zero, 0x20
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addi sp, sp, 8
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*/
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uint64_t r_t0 = 0x1234;
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uint64_t r_t1 = 0x7890;
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uint64_t r_pc = 0x0000;
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uint64_t r_sp = 0x1234;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_write(uc, UC_RISCV_REG_SP, &r_sp));
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// emulate the three instructions
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OK(uc_emu_start(uc, code_start, -1, 0, 3));
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_read(uc, UC_RISCV_REG_SP, &r_sp));
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OK(uc_reg_read(uc, UC_RISCV_REG_PC, &r_pc));
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TEST_CHECK(r_t0 == 0x1);
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TEST_CHECK(r_t1 == 0x20);
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TEST_CHECK(r_sp == 0x123c);
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TEST_CHECK(r_pc == (code_start + sizeof(code) - 1));
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OK(uc_close(uc));
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}
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static void test_riscv32_fp_move(void)
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{
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uc_engine *uc;
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char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
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uint32_t r_f1 = 0x1234;
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uint32_t r_f3 = 0x5678;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
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sizeof(code) - 1);
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// initialize machine registers
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uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1);
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uc_reg_write(uc, UC_RISCV_REG_F3, &r_f3);
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3));
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TEST_CHECK(r_f1 == 0x1234);
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TEST_CHECK(r_f3 == 0x1234);
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uc_close(uc);
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}
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static void test_riscv64_fp_move(void)
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{
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uc_engine *uc;
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char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
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uint64_t r_f1 = 0x12341234;
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uint64_t r_f3 = 0x56785678;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_write(uc, UC_RISCV_REG_F3, &r_f3));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3));
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TEST_CHECK(r_f1 == 0x12341234);
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TEST_CHECK(r_f3 == 0x12341234);
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uc_close(uc);
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}
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static void test_riscv64_fp_move_from_int(void)
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{
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uc_engine *uc;
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// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
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// https://five-embeddev.com/quickref/csrs.html
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// We have to enable mstatus.fs
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char code[] = "\xf3\x90\x01\x30\x53\x00\x0b\xf2"; // csrrw x2, mstatus, x3;
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// fmvd.d.x ft0, s6
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uint64_t r_ft0 = 0x12341234;
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uint64_t r_s6 = 0x56785678;
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uint64_t r_x3 = 0x6000;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6));
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// mstatus.fs
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OK(uc_reg_write(uc, UC_RISCV_REG_X3, &r_x3));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 2));
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OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6));
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TEST_CHECK(r_ft0 == 0x56785678);
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TEST_CHECK(r_s6 == 0x56785678);
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uc_close(uc);
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}
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static void test_riscv64_fp_move_from_int_reg_write(void)
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{
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uc_engine *uc;
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char code[] = "\x53\x00\x0b\xf2"; // fmvd.d.x ft0, s6
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uint64_t r_ft0 = 0x12341234;
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uint64_t r_s6 = 0x56785678;
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uint64_t r_mstatus = 0x6000;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6));
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// mstatus.fs
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OK(uc_reg_write(uc, UC_RISCV_REG_MSTATUS, &r_mstatus));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 1));
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OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6));
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TEST_CHECK(r_ft0 == 0x56785678);
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TEST_CHECK(r_s6 == 0x56785678);
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OK(uc_close(uc));
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}
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static void test_riscv64_fp_move_to_int(void)
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{
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uc_engine *uc;
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// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
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// https://five-embeddev.com/quickref/csrs.html
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// We have to enable mstatus.fs
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char code[] = "\xf3\x90\x01\x30\x53\x0b\x00\xe2"; // csrrw x2, mstatus, x3;
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// fmv.x.d s6, ft0
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uint64_t r_ft0 = 0x12341234;
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uint64_t r_s6 = 0x56785678;
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uint64_t r_x3 = 0x6000;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_write(uc, UC_RISCV_REG_S6, &r_s6));
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// mstatus.fs
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OK(uc_reg_write(uc, UC_RISCV_REG_X3, &r_x3));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 2));
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OK(uc_reg_read(uc, UC_RISCV_REG_FT0, &r_ft0));
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OK(uc_reg_read(uc, UC_RISCV_REG_S6, &r_s6));
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TEST_CHECK(r_ft0 == 0x12341234);
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TEST_CHECK(r_s6 == 0x12341234);
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uc_close(uc);
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}
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static void test_riscv64_code_patching(void)
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{
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uc_engine *uc;
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char code[] = "\x93\x82\x12\x00"; // addi t0, t0, 0x1
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// Zero out t0 and t1
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uint64_t r_t0 = 0x0;
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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// check value
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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TEST_CHECK(r_t0 == 0x1);
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// patch instruction
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char patch_code[] = "\x93\x82\xf2\x7f"; // addi t0, t0, 0x7FF
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OK(uc_mem_write(uc, code_start, patch_code, sizeof(patch_code) - 1));
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// zero out t0
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r_t0 = 0x0;
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(patch_code) - 1, 0, 0));
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// check value
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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TEST_CHECK(r_t0 != 0x1);
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TEST_CHECK(r_t0 == 0x7ff);
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OK(uc_close(uc));
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}
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// Need to flush the cache before running the emulation after patching
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static void test_riscv64_code_patching_count(void)
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{
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uc_engine *uc;
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char code[] = "\x93\x82\x12\x00"; // addi t0, t0, 0x1
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// Zero out t0 and t1
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uint64_t r_t0 = 0x0;
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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// emulate the instruction
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OK(uc_emu_start(uc, code_start, -1, 0, 1));
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// check value
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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TEST_CHECK(r_t0 == 0x1);
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// patch instruction
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char patch_code[] = "\x93\x82\xf2\x7f"; // addi t0, t0, 0x7FF
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OK(uc_mem_write(uc, code_start, patch_code, sizeof(patch_code) - 1));
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OK(uc_ctl_remove_cache(uc, code_start,
|
|
code_start + sizeof(patch_code) - 1));
|
|
// zero out t0
|
|
r_t0 = 0x0;
|
|
OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
|
|
OK(uc_emu_start(uc, code_start, -1, 0, 1));
|
|
// check value
|
|
OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
|
|
TEST_CHECK(r_t0 != 0x1);
|
|
TEST_CHECK(r_t0 == 0x7ff);
|
|
|
|
OK(uc_close(uc));
|
|
}
|
|
|
|
static void test_riscv64_ecall_cb(uc_engine *uc, uint32_t intno, void *data)
|
|
{
|
|
uc_emu_stop(uc);
|
|
return;
|
|
}
|
|
|
|
static void test_riscv64_ecall(void)
|
|
{
|
|
uc_engine *uc;
|
|
char code[] = "\x73\x00\x00\x00"; // ecall
|
|
uint64_t r_pc;
|
|
uc_hook h;
|
|
|
|
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
|
|
sizeof(code) - 1);
|
|
|
|
OK(uc_hook_add(uc, &h, UC_HOOK_INTR, test_riscv64_ecall_cb, NULL, 1, 0));
|
|
OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
|
|
|
|
OK(uc_reg_read(uc, UC_RISCV_REG_PC, &r_pc));
|
|
|
|
TEST_CHECK(r_pc == code_start + 4);
|
|
|
|
OK(uc_close(uc));
|
|
}
|
|
|
|
static uint64_t test_riscv32_mmio_map_read_cb(uc_engine *uc, uint64_t offset,
|
|
unsigned size, void *data)
|
|
{
|
|
int r_a4;
|
|
OK(uc_reg_read(uc, UC_RISCV_REG_A4, &r_a4));
|
|
TEST_CHECK(r_a4 == 0x40021 << 12);
|
|
TEST_CHECK(offset == 0x21018);
|
|
return 0;
|
|
}
|
|
|
|
static void test_riscv32_mmio_map(void)
|
|
{
|
|
uc_engine *uc;
|
|
// 37 17 02 40 lui a4, 0x40021
|
|
// 1c 4f c.lw a5, 0x18(a4)
|
|
//
|
|
char code[] = "\x37\x17\x02\x40\x1c\x4f";
|
|
|
|
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
|
|
sizeof(code) - 1);
|
|
|
|
OK(uc_mmio_map(uc, 0x40000000, 0x40000, test_riscv32_mmio_map_read_cb, NULL,
|
|
NULL, NULL));
|
|
OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
|
|
|
|
OK(uc_close(uc));
|
|
}
|
|
|
|
static void test_riscv32_map(void)
|
|
{
|
|
uc_engine *uc;
|
|
// 37 17 02 40 lui a4, 0x40021
|
|
// 1c 4f c.lw a5, 0x18(a4)
|
|
//
|
|
char code[] = "\x37\x17\x02\x40\x1c\x4f";
|
|
uint64_t val = 0xdeadbeef;
|
|
|
|
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
|
|
sizeof(code) - 1);
|
|
|
|
OK(uc_mem_map(uc, 0x40000000, 0x40000, UC_PROT_ALL));
|
|
OK(uc_mem_write(uc, 0x40000000 + 0x21018, &val, 8));
|
|
OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
|
|
|
|
OK(uc_reg_read(uc, UC_RISCV_REG_A5, &val));
|
|
|
|
TEST_CHECK(val == 0xdeadbeef);
|
|
OK(uc_close(uc));
|
|
}
|
|
|
|
static uint64_t test_riscv64_mmio_map_read_cb(uc_engine *uc, uint64_t offset,
|
|
unsigned size, void *data)
|
|
{
|
|
uint64_t r_a4;
|
|
OK(uc_reg_read(uc, UC_RISCV_REG_A4, &r_a4));
|
|
TEST_CHECK(r_a4 == 0x40021 << 12);
|
|
TEST_CHECK(offset == 0x21018);
|
|
return 0;
|
|
}
|
|
|
|
static void test_riscv64_mmio_map(void)
|
|
{
|
|
uc_engine *uc;
|
|
// 37 17 02 40 lui a4, 0x40021
|
|
// 1c 4f c.lw a5, 0x18(a4)
|
|
//
|
|
char code[] = "\x37\x17\x02\x40\x1c\x4f";
|
|
|
|
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
|
|
sizeof(code) - 1);
|
|
|
|
OK(uc_mmio_map(uc, 0x40000000, 0x40000, test_riscv64_mmio_map_read_cb, NULL,
|
|
NULL, NULL));
|
|
OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
|
|
|
|
OK(uc_close(uc));
|
|
}
|
|
|
|
TEST_LIST = {
|
|
{"test_riscv32_nop", test_riscv32_nop},
|
|
{"test_riscv64_nop", test_riscv64_nop},
|
|
{"test_riscv32_3steps_pc_update", test_riscv32_3steps_pc_update},
|
|
{"test_riscv64_3steps_pc_update", test_riscv64_3steps_pc_update},
|
|
{"test_riscv32_until_pc_update", test_riscv32_until_pc_update},
|
|
{"test_riscv64_until_pc_update", test_riscv64_until_pc_update},
|
|
{"test_riscv32_fp_move", test_riscv32_fp_move},
|
|
{"test_riscv64_fp_move", test_riscv64_fp_move},
|
|
{"test_riscv64_fp_move_from_int", test_riscv64_fp_move_from_int},
|
|
{"test_riscv64_fp_move_from_int_reg_write",
|
|
test_riscv64_fp_move_from_int_reg_write},
|
|
{"test_riscv64_fp_move_to_int", test_riscv64_fp_move_to_int},
|
|
{"test_riscv64_ecall", test_riscv64_ecall},
|
|
{"test_riscv32_mmio_map", test_riscv32_mmio_map},
|
|
{"test_riscv64_mmio_map", test_riscv64_mmio_map},
|
|
{"test_riscv32_map", test_riscv32_map},
|
|
{"test_riscv64_code_patching", test_riscv64_code_patching},
|
|
{"test_riscv64_code_patching_count", test_riscv64_code_patching_count},
|
|
{NULL, NULL}};
|