117 lines
3.0 KiB
C
117 lines
3.0 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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#include "hw/boards.h"
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#include "hw/mips/mips.h"
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#include "sysemu/cpus.h"
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#include "unicorn.h"
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#include "cpu.h"
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#include "unicorn_common.h"
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#define READ_QWORD(x) ((uint64)x)
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#define READ_DWORD(x) (x & 0xffffffff)
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#define READ_WORD(x) (x & 0xffff)
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#define READ_BYTE_H(x) ((x & 0xffff) >> 8)
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#define READ_BYTE_L(x) (x & 0xff)
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static uint64_t mips_mem_redirect(uint64_t address)
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{
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// kseg0 range masks off high address bit
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if (address >= 0x80000000 && address <= 0x9fffffff)
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return address & 0x7fffffff;
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// kseg1 range masks off top 3 address bits
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if (address >= 0xa0000000 && address <= 0xbfffffff) {
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return address & 0x1fffffff;
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}
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// no redirect
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return address;
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}
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static void mips_set_pc(struct uc_struct *uc, uint64_t address)
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{
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((CPUMIPSState *)uc->current_cpu->env_ptr)->active_tc.PC = address;
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}
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void mips_reg_reset(struct uc_struct *uc)
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{
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(void)uc;
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CPUArchState *env = first_cpu->env_ptr;
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memset(env->active_tc.gpr, 0, sizeof(env->active_tc.gpr));
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env->active_tc.PC = 0;
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}
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int mips_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
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{
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CPUState *mycpu = first_cpu;
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
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*(int32_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0];
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else {
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switch(regid) {
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default: break;
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case UC_MIPS_REG_PC:
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*(int32_t *)value = MIPS_CPU(uc, mycpu)->env.active_tc.PC;
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break;
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}
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}
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return 0;
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}
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#define WRITE_DWORD(x, w) (x = (x & ~0xffffffff) | (w & 0xffffffff))
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#define WRITE_WORD(x, w) (x = (x & ~0xffff) | (w & 0xffff))
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#define WRITE_BYTE_H(x, b) (x = (x & ~0xff00) | (b & 0xff))
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#define WRITE_BYTE_L(x, b) (x = (x & ~0xff) | (b & 0xff))
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int mips_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
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{
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CPUState *mycpu = first_cpu;
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if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
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MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(uint32_t *)value;
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else {
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switch(regid) {
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default: break;
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case UC_MIPS_REG_PC:
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MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(uint32_t *)value;
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break;
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}
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}
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return 0;
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}
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__attribute__ ((visibility ("default")))
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#ifdef TARGET_MIPS64
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#ifdef TARGET_WORDS_BIGENDIAN
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void mips64_uc_init(struct uc_struct* uc)
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#else
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void mips64el_uc_init(struct uc_struct* uc)
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#endif
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#else // if TARGET_MIPS
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#ifdef TARGET_WORDS_BIGENDIAN
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void mips_uc_init(struct uc_struct* uc)
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#else
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void mipsel_uc_init(struct uc_struct* uc)
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#endif
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#endif
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{
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register_accel_types(uc);
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mips_cpu_register_types(uc);
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mips_machine_init(uc);
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uc->reg_read = mips_reg_read;
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uc->reg_write = mips_reg_write;
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uc->reg_reset = mips_reg_reset;
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uc->set_pc = mips_set_pc;
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uc->mem_redirect = mips_mem_redirect;
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uc_common_init(uc);
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}
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