522 lines
15 KiB
C
522 lines
15 KiB
C
/*
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* i386 helpers (without register variable usage)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "sysemu/tcg.h"
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void cpu_sync_bndcs_hflags(CPUX86State *env)
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{
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uint32_t hflags = env->hflags;
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uint32_t hflags2 = env->hflags2;
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uint32_t bndcsr;
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if ((hflags & HF_CPL_MASK) == 3) {
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bndcsr = env->bndcs_regs.cfgu;
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} else {
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bndcsr = env->msr_bndcfgs;
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}
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if ((env->cr[4] & CR4_OSXSAVE_MASK)
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&& (env->xcr0 & XSTATE_BNDCSR_MASK)
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&& (bndcsr & BNDCFG_ENABLE)) {
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hflags |= HF_MPX_EN_MASK;
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} else {
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hflags &= ~HF_MPX_EN_MASK;
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}
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if (bndcsr & BNDCFG_BNDPRESERVE) {
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hflags2 |= HF2_MPX_PR_MASK;
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} else {
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hflags2 &= ~HF2_MPX_PR_MASK;
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}
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env->hflags = hflags;
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env->hflags2 = hflags2;
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}
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static void cpu_x86_version(CPUX86State *env, int *family, int *model)
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{
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int cpuver = env->cpuid_version;
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if (family == NULL || model == NULL) {
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return;
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}
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*family = (cpuver >> 8) & 0x0f;
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*model = ((cpuver >> 12) & 0xf0) + ((cpuver >> 4) & 0x0f);
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}
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/* Broadcast MCA signal for processor version 06H_EH and above */
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int cpu_x86_support_mca_broadcast(CPUX86State *env)
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{
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int family = 0;
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int model = 0;
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cpu_x86_version(env, &family, &model);
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if ((family == 6 && model >= 14) || family > 6) {
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return 1;
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}
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return 0;
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}
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/***********************************************************/
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/* x86 mmu */
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/* XXX: add PGE support */
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void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
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{
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CPUX86State *env = &cpu->env;
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a20_state = (a20_state != 0);
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if (a20_state != ((env->a20_mask >> 20) & 1)) {
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CPUState *cs = CPU(cpu);
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qemu_log_mask(CPU_LOG_MMU, "A20 update: a20=%d\n", a20_state);
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/* if the cpu is currently executing code, we must unlink it and
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all the potentially executing TB */
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cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
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/* when a20 is changed, all the MMU mappings are invalid, so
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we must flush everything */
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tlb_flush(cs);
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env->a20_mask = ~(1 << 20) | (a20_state << 20);
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}
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}
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void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
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{
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X86CPU *cpu = env_archcpu(env);
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int pe_state;
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qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
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if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
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(env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
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tlb_flush(CPU(cpu));
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}
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#ifdef TARGET_X86_64
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if (!(env->cr[0] & CR0_PG_MASK) && (new_cr0 & CR0_PG_MASK) &&
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(env->efer & MSR_EFER_LME)) {
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/* enter in long mode */
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/* XXX: generate an exception */
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if (!(env->cr[4] & CR4_PAE_MASK))
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return;
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env->efer |= MSR_EFER_LMA;
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env->hflags |= HF_LMA_MASK;
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} else if ((env->cr[0] & CR0_PG_MASK) && !(new_cr0 & CR0_PG_MASK) &&
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(env->efer & MSR_EFER_LMA)) {
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/* exit long mode */
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env->efer &= ~MSR_EFER_LMA;
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env->hflags &= ~(HF_LMA_MASK | HF_CS64_MASK);
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env->eip &= 0xffffffff;
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}
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#endif
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env->cr[0] = new_cr0 | CR0_ET_MASK;
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/* update PE flag in hidden flags */
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pe_state = (env->cr[0] & CR0_PE_MASK);
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env->hflags = (env->hflags & ~HF_PE_MASK) | (pe_state << HF_PE_SHIFT);
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/* ensure that ADDSEG is always set in real mode */
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env->hflags |= ((pe_state ^ 1) << HF_ADDSEG_SHIFT);
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/* update FPU flags */
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env->hflags = (env->hflags & ~(HF_MP_MASK | HF_EM_MASK | HF_TS_MASK)) |
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((new_cr0 << (HF_MP_SHIFT - 1)) & (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK));
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}
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/* XXX: in legacy PAE mode, generate a GPF if reserved bits are set in
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the PDPT */
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void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
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{
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env->cr[3] = new_cr3;
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if (env->cr[0] & CR0_PG_MASK) {
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qemu_log_mask(CPU_LOG_MMU,
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"CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
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tlb_flush(env_cpu(env));
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}
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}
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void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
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{
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uint32_t hflags;
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#if defined(DEBUG_MMU)
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printf("CR4 update: %08x -> %08x\n", (uint32_t)env->cr[4], new_cr4);
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#endif
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if ((new_cr4 ^ env->cr[4]) &
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(CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
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CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) {
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tlb_flush(env_cpu(env));
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}
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/* Clear bits we're going to recompute. */
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hflags = env->hflags & ~(HF_OSFXSR_MASK | HF_SMAP_MASK);
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/* SSE handling */
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if (!(env->features[FEAT_1_EDX] & CPUID_SSE)) {
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new_cr4 &= ~CR4_OSFXSR_MASK;
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}
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if (new_cr4 & CR4_OSFXSR_MASK) {
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hflags |= HF_OSFXSR_MASK;
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}
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if (!(env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_SMAP)) {
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new_cr4 &= ~CR4_SMAP_MASK;
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}
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if (new_cr4 & CR4_SMAP_MASK) {
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hflags |= HF_SMAP_MASK;
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}
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if (!(env->features[FEAT_7_0_ECX] & CPUID_7_0_ECX_PKU)) {
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new_cr4 &= ~CR4_PKE_MASK;
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}
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env->cr[4] = new_cr4;
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env->hflags = hflags;
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cpu_sync_bndcs_hflags(env);
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}
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hwaddr x86_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
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MemTxAttrs *attrs)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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target_ulong pde_addr, pte_addr;
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uint64_t pte;
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int32_t a20_mask;
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uint32_t page_offset;
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int page_size;
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*attrs = cpu_get_mem_attrs(env);
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a20_mask = x86_get_a20_mask(env);
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if (!(env->cr[0] & CR0_PG_MASK)) {
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pte = addr & a20_mask;
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page_size = 4096;
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} else if (env->cr[4] & CR4_PAE_MASK) {
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target_ulong pdpe_addr;
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uint64_t pde, pdpe;
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#ifdef TARGET_X86_64
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if (env->hflags & HF_LMA_MASK) {
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bool la57 = env->cr[4] & CR4_LA57_MASK;
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uint64_t pml5e_addr, pml5e;
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uint64_t pml4e_addr, pml4e;
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int32_t sext;
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/* test virtual address sign extension */
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sext = la57 ? (int64_t)addr >> 56 : (int64_t)addr >> 47;
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if (sext != 0 && sext != -1) {
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return -1;
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}
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if (la57) {
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pml5e_addr = ((env->cr[3] & ~0xfff) +
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(((addr >> 48) & 0x1ff) << 3)) & a20_mask;
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pml5e = x86_ldq_phys(cs, pml5e_addr);
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if (!(pml5e & PG_PRESENT_MASK)) {
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return -1;
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}
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} else {
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pml5e = env->cr[3];
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}
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pml4e_addr = ((pml5e & PG_ADDRESS_MASK) +
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(((addr >> 39) & 0x1ff) << 3)) & a20_mask;
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pml4e = x86_ldq_phys(cs, pml4e_addr);
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if (!(pml4e & PG_PRESENT_MASK)) {
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return -1;
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}
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pdpe_addr = ((pml4e & PG_ADDRESS_MASK) +
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(((addr >> 30) & 0x1ff) << 3)) & a20_mask;
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK)) {
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return -1;
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}
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if (pdpe & PG_PSE_MASK) {
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page_size = 1024 * 1024 * 1024;
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pte = pdpe;
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goto out;
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}
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} else
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#endif
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{
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pdpe_addr = ((env->cr[3] & ~0x1f) + ((addr >> 27) & 0x18)) &
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a20_mask;
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pdpe = x86_ldq_phys(cs, pdpe_addr);
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if (!(pdpe & PG_PRESENT_MASK))
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return -1;
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}
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pde_addr = ((pdpe & PG_ADDRESS_MASK) +
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(((addr >> 21) & 0x1ff) << 3)) & a20_mask;
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pde = x86_ldq_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK)) {
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return -1;
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}
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if (pde & PG_PSE_MASK) {
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/* 2 MB page */
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page_size = 2048 * 1024;
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pte = pde;
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} else {
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/* 4 KB page */
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pte_addr = ((pde & PG_ADDRESS_MASK) +
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(((addr >> 12) & 0x1ff) << 3)) & a20_mask;
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page_size = 4096;
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pte = x86_ldq_phys(cs, pte_addr);
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}
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if (!(pte & PG_PRESENT_MASK)) {
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return -1;
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}
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} else {
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uint32_t pde;
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/* page directory entry */
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pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & a20_mask;
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pde = x86_ldl_phys(cs, pde_addr);
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if (!(pde & PG_PRESENT_MASK))
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return -1;
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if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
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pte = pde | ((pde & 0x1fe000LL) << (32 - 13));
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page_size = 4096 * 1024;
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} else {
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/* page directory entry */
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pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & a20_mask;
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pte = x86_ldl_phys(cs, pte_addr);
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if (!(pte & PG_PRESENT_MASK)) {
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return -1;
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}
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page_size = 4096;
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}
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pte = pte & a20_mask;
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}
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#ifdef TARGET_X86_64
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out:
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#endif
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pte &= PG_ADDRESS_MASK & ~(page_size - 1);
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page_offset = (addr & TARGET_PAGE_MASK) & (page_size - 1);
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return pte | page_offset;
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}
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int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
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target_ulong *base, unsigned int *limit,
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unsigned int *flags)
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{
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CPUState *cs = env_cpu(env);
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SegmentCache *dt;
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target_ulong ptr;
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uint32_t e1, e2;
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int index;
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if (selector & 0x4)
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dt = &env->ldt;
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else
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dt = &env->gdt;
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index = selector & ~7;
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ptr = dt->base + index;
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if ((index + 7) > dt->limit
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|| cpu_memory_rw_debug(cs, ptr, (uint8_t *)&e1, sizeof(e1), 0) != 0
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|| cpu_memory_rw_debug(cs, ptr+4, (uint8_t *)&e2, sizeof(e2), 0) != 0)
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return 0;
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*base = ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000));
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*limit = (e1 & 0xffff) | (e2 & 0x000f0000);
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if (e2 & DESC_G_MASK)
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*limit = (*limit << 12) | 0xfff;
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*flags = e2;
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return 1;
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}
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void do_cpu_init(X86CPU *cpu)
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{
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CPUState *cs = CPU(cpu);
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CPUX86State *env = &cpu->env;
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CPUX86State *save = g_new(CPUX86State, 1);
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int sipi = cs->interrupt_request & CPU_INTERRUPT_SIPI;
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*save = *env;
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cpu_reset(cs);
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cs->interrupt_request = sipi;
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memcpy(&env->start_init_save, &save->start_init_save,
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offsetof(CPUX86State, end_init_save) -
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offsetof(CPUX86State, start_init_save));
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g_free(save);
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// apic_init_reset(cpu->apic_state);
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}
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void do_cpu_sipi(X86CPU *cpu)
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{
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// apic_sipi(cpu->apic_state);
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}
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/* Frob eflags into and out of the CPU temporary format. */
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void x86_cpu_exec_enter(CPUState *cs)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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env->df = 1 - (2 * ((env->eflags >> 10) & 1));
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CC_OP = CC_OP_EFLAGS;
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env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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}
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void x86_cpu_exec_exit(CPUState *cs)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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env->eflags = cpu_compute_eflags(env);
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}
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uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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MemTxAttrs attrs = cpu_get_mem_attrs(env);
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AddressSpace *as = cpu_addressspace(cs, attrs);
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#ifdef UNICORN_ARCH_POSTFIX
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return glue(address_space_ldub, UNICORN_ARCH_POSTFIX)(as->uc, as, addr, attrs, NULL);
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#else
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return address_space_ldub(as->uc, as, addr, attrs, NULL);
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#endif
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}
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uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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MemTxAttrs attrs = cpu_get_mem_attrs(env);
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AddressSpace *as = cpu_addressspace(cs, attrs);
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#ifdef UNICORN_ARCH_POSTFIX
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return glue(address_space_lduw, UNICORN_ARCH_POSTFIX)(as->uc, as, addr, attrs, NULL);
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#else
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return address_space_lduw(as->uc, as, addr, attrs, NULL);
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#endif
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}
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uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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MemTxAttrs attrs = cpu_get_mem_attrs(env);
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AddressSpace *as = cpu_addressspace(cs, attrs);
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#ifdef UNICORN_ARCH_POSTFIX
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return glue(address_space_ldl, UNICORN_ARCH_POSTFIX)(as->uc, as, addr, attrs, NULL);
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#else
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return address_space_ldl(as->uc, as, addr, attrs, NULL);
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#endif
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}
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uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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MemTxAttrs attrs = cpu_get_mem_attrs(env);
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AddressSpace *as = cpu_addressspace(cs, attrs);
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#ifdef UNICORN_ARCH_POSTFIX
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return glue(address_space_ldq, UNICORN_ARCH_POSTFIX)(as->uc, as, addr, attrs, NULL);
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#else
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return address_space_ldq(as->uc, as, addr, attrs, NULL);
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#endif
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}
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void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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MemTxAttrs attrs = cpu_get_mem_attrs(env);
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AddressSpace *as = cpu_addressspace(cs, attrs);
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#ifdef UNICORN_ARCH_POSTFIX
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glue(address_space_stb, UNICORN_ARCH_POSTFIX)(as->uc, as, addr, val, attrs, NULL);
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#else
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address_space_stb(as->uc, as, addr, val, attrs, NULL);
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#endif
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}
|
|
|
|
void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val)
|
|
{
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
#ifdef UNICORN_ARCH_POSTFIX
|
|
glue(address_space_stl_notdirty, UNICORN_ARCH_POSTFIX)(as->uc, as, addr, val, attrs, NULL);
|
|
#else
|
|
address_space_stl_notdirty(as->uc, as, addr, val, attrs, NULL);
|
|
#endif
|
|
}
|
|
|
|
void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val)
|
|
{
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
#ifdef UNICORN_ARCH_POSTFIX
|
|
glue(address_space_stw,UNICORN_ARCH_POSTFIX)(as->uc, as, addr, val, attrs, NULL);
|
|
#else
|
|
address_space_stw(as->uc, as, addr, val, attrs, NULL);
|
|
#endif
|
|
}
|
|
|
|
void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val)
|
|
{
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
#ifdef UNICORN_ARCH_POSTFIX
|
|
glue(address_space_stl, UNICORN_ARCH_POSTFIX)(as->uc, as, addr, val, attrs, NULL);
|
|
#else
|
|
address_space_stl(as->uc, as, addr, val, attrs, NULL);
|
|
#endif
|
|
}
|
|
|
|
void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val)
|
|
{
|
|
X86CPU *cpu = X86_CPU(cs);
|
|
CPUX86State *env = &cpu->env;
|
|
MemTxAttrs attrs = cpu_get_mem_attrs(env);
|
|
AddressSpace *as = cpu_addressspace(cs, attrs);
|
|
|
|
#ifdef UNICORN_ARCH_POSTFIX
|
|
glue(address_space_stq, UNICORN_ARCH_POSTFIX)(as->uc, as, addr, val, attrs, NULL);
|
|
#else
|
|
address_space_stq(as->uc, as, addr, val, attrs, NULL);
|
|
#endif
|
|
}
|