139 lines
3.5 KiB
C
139 lines
3.5 KiB
C
/* Unicorn Emulator Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2015 */
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/* Modified for Unicorn Engine by Chen Huitao<chenhuitao@hfmrit.com>, 2020 */
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#include "sysemu/cpus.h"
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#include "cpu.h"
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#include "unicorn_common.h"
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#include "uc_priv.h"
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#include "unicorn.h"
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M68kCPU *cpu_m68k_init(struct uc_struct *uc);
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static void m68k_set_pc(struct uc_struct *uc, uint64_t address)
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{
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((CPUM68KState *)uc->cpu->env_ptr)->pc = address;
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}
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static uint64_t m68k_get_pc(struct uc_struct *uc)
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{
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return ((CPUM68KState *)uc->cpu->env_ptr)->pc;
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}
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static void m68k_release(void *ctx)
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{
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int i;
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TCGContext *tcg_ctx = (TCGContext *)ctx;
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M68kCPU *cpu = (M68kCPU *)tcg_ctx->uc->cpu;
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CPUTLBDesc *d = cpu->neg.tlb.d;
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CPUTLBDescFast *f = cpu->neg.tlb.f;
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CPUTLBDesc *desc;
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CPUTLBDescFast *fast;
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release_common(ctx);
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for (i = 0; i < NB_MMU_MODES; i++) {
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desc = &(d[i]);
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fast = &(f[i]);
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g_free(desc->iotlb);
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g_free(fast->table);
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}
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}
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static void reg_reset(struct uc_struct *uc)
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{
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CPUArchState *env = uc->cpu->env_ptr;
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memset(env->aregs, 0, sizeof(env->aregs));
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memset(env->dregs, 0, sizeof(env->dregs));
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env->pc = 0;
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}
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DEFAULT_VISIBILITY
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uc_err reg_read(void *_env, int mode, unsigned int regid, void *value,
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size_t *size)
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{
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CPUM68KState *env = _env;
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uc_err ret = UC_ERR_ARG;
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if (regid >= UC_M68K_REG_A0 && regid <= UC_M68K_REG_A7) {
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->aregs[regid - UC_M68K_REG_A0];
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} else if (regid >= UC_M68K_REG_D0 && regid <= UC_M68K_REG_D7) {
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->dregs[regid - UC_M68K_REG_D0];
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} else {
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switch (regid) {
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default:
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break;
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case UC_M68K_REG_PC:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->pc;
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break;
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case UC_M68K_REG_SR:
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CHECK_REG_TYPE(uint32_t);
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*(uint32_t *)value = env->sr;
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break;
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}
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}
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return ret;
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}
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DEFAULT_VISIBILITY
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uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
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size_t *size, int *setpc)
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{
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CPUM68KState *env = _env;
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uc_err ret = UC_ERR_ARG;
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if (regid >= UC_M68K_REG_A0 && regid <= UC_M68K_REG_A7) {
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CHECK_REG_TYPE(uint32_t);
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env->aregs[regid - UC_M68K_REG_A0] = *(uint32_t *)value;
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} else if (regid >= UC_M68K_REG_D0 && regid <= UC_M68K_REG_D7) {
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CHECK_REG_TYPE(uint32_t);
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env->dregs[regid - UC_M68K_REG_D0] = *(uint32_t *)value;
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} else {
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switch (regid) {
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default:
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break;
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case UC_M68K_REG_PC:
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CHECK_REG_TYPE(uint32_t);
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env->pc = *(uint32_t *)value;
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*setpc = 1;
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break;
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case UC_M68K_REG_SR:
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CHECK_REG_TYPE(uint32_t);
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cpu_m68k_set_sr(env, *(uint32_t *)value);
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break;
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}
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}
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return ret;
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}
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static int m68k_cpus_init(struct uc_struct *uc, const char *cpu_model)
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{
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M68kCPU *cpu;
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cpu = cpu_m68k_init(uc);
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if (cpu == NULL) {
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return -1;
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}
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return 0;
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}
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DEFAULT_VISIBILITY
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void uc_init(struct uc_struct *uc)
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{
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uc->release = m68k_release;
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uc->reg_read = reg_read;
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uc->reg_write = reg_write;
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uc->reg_reset = reg_reset;
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uc->set_pc = m68k_set_pc;
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uc->get_pc = m68k_get_pc;
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uc->cpus_init = m68k_cpus_init;
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uc->cpu_context_size = offsetof(CPUM68KState, end_reset_fields);
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uc_common_init(uc);
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}
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