History

Sven Bartscher 59fb8a2733 rust: Add RISCV CSR registers The addition of these registers in the C base caused the rust values for all floating point registers and the PC to point to some of the CSR registers instead.		2021-11-30 16:09:24 +01:00
..
src	rust: Add RISCV CSR registers	2021-11-30 16:09:24 +01:00
tests	Add map_mmio to rust bindings	2021-11-24 12:15:20 +01:00
build.rs	Merge pull request #1480 from domenukk/rust_bindings	2021-11-10 07:52:31 +01:00
Cargo.toml	Fix uc_version and bump again	2021-11-25 18:19:46 +01:00
COPYING	bindings: add Rust	2021-10-04 01:01:43 +08:00
README.md	reapply missing changes	2021-11-09 16:04:59 +01:00

README.md

Unicorn-engine

Rust bindings for the Unicorn emulator with utility functions.

Checkout Unicorn2 source code at dev branch.

use unicorn_engine::{Unicorn, RegisterARM};
use unicorn_engine::unicorn_const::{Arch, Mode, Permission, SECOND_SCALE};

fn main() {
    let arm_code32: Vec<u8> = vec![0x17, 0x00, 0x40, 0xe2]; // sub r0, #23

    let mut unicorn = Unicorn::new(Arch::ARM, Mode::LITTLE_ENDIAN).expect("failed to initialize Unicorn instance");
    let mut emu = unicorn.borrow();
    emu.mem_map(0x1000, 0x4000, Permission::ALL).expect("failed to map code page");
    emu.mem_write(0x1000, &arm_code32).expect("failed to write instructions");

    emu.reg_write(RegisterARM::R0, 123).expect("failed write R0");
    emu.reg_write(RegisterARM::R5, 1337).expect("failed write R5");

    let _ = emu.emu_start(0x1000, (0x1000 + arm_code32.len()) as u64, 10 * SECOND_SCALE, 1000);
    assert_eq!(emu.reg_read(RegisterARM::R0, Ok(100));
    assert_eq!(emu.reg_read(RegisterARM::R5, Ok(1337));
}

Further sample code can be found in tests/unicorn.rs.

Usage

Add this to your Cargo.toml:

[dependencies]
unicorn-engine = "2.0.0-rc3"

Acknowledgements

These bindings are based on Sébastien Duquette's (@ekse) unicorn-rs. We picked up the project, as it is no longer maintained. Thanks to all contributors.