227 lines
6.3 KiB
C
227 lines
6.3 KiB
C
#include "unicorn_test.h"
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const uint64_t code_start = 0x1000;
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const uint64_t code_len = 0x4000;
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static void uc_common_setup(uc_engine **uc, uc_arch arch, uc_mode mode,
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const char *code, uint64_t size)
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{
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OK(uc_open(arch, mode, uc));
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OK(uc_mem_map(*uc, code_start, code_len, UC_PROT_ALL));
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OK(uc_mem_write(*uc, code_start, code, size));
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}
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static void test_riscv32_nop()
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{
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uc_engine *uc;
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char code[] = "\x13\x00\x00\x00"; // nop
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uint32_t r_t0 = 0x1234;
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uint32_t r_t1 = 0x5678;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
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sizeof(code) - 1);
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
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TEST_CHECK(r_t0 == 0x1234);
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TEST_CHECK(r_t1 == 0x5678);
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OK(uc_close(uc));
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}
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static void test_riscv64_nop()
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{
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uc_engine *uc;
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char code[] = "\x13\x00\x00\x00"; // nop
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uint64_t r_t0 = 0x1234;
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uint64_t r_t1 = 0x5678;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
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TEST_CHECK(r_t0 == 0x1234);
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TEST_CHECK(r_t1 == 0x5678);
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OK(uc_close(uc));
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}
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static void test_riscv32_until_pc_update()
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{
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uc_engine *uc;
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char code[] = "\x93\x02\x10\x00\x13\x03\x00\x02\x13\x01\x81\x00";
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/*
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addi t0, zero, 1
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addi t1, zero, 0x20
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addi sp, sp, 8
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*/
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uint32_t r_t0 = 0x1234;
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uint32_t r_t1 = 0x7890;
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uint32_t r_pc = 0x0000;
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uint32_t r_sp = 0x1234;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_write(uc, UC_RISCV_REG_SP, &r_sp));
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// emulate the three instructions
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_read(uc, UC_RISCV_REG_SP, &r_sp));
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OK(uc_reg_read(uc, UC_RISCV_REG_PC, &r_pc));
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TEST_CHECK(r_t0 == 0x1);
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TEST_CHECK(r_t1 == 0x20);
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TEST_CHECK(r_sp == 0x123c);
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TEST_CHECK(r_pc == (code_start + sizeof(code) - 1));
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OK(uc_close(uc));
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}
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static void test_riscv64_until_pc_update()
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{
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uc_engine *uc;
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char code[] = "\x93\x02\x10\x00\x13\x03\x00\x02\x13\x01\x81\x00";
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/*
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addi t0, zero, 1
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addi t1, zero, 0x20
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addi sp, sp, 8
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*/
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uint64_t r_t0 = 0x1234;
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uint64_t r_t1 = 0x7890;
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uint64_t r_pc = 0x0000;
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uint64_t r_sp = 0x1234;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_write(uc, UC_RISCV_REG_SP, &r_sp));
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// emulate the three instructions
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_read(uc, UC_RISCV_REG_SP, &r_sp));
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OK(uc_reg_read(uc, UC_RISCV_REG_PC, &r_pc));
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TEST_CHECK(r_t0 == 0x1);
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TEST_CHECK(r_t1 == 0x20);
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TEST_CHECK(r_sp == 0x123c);
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TEST_CHECK(r_pc == (code_start + sizeof(code) - 1));
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OK(uc_close(uc));
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}
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static void test_riscv32_3steps_pc_update()
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{
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uc_engine *uc;
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char code[] = "\x93\x02\x10\x00\x13\x03\x00\x02\x13\x01\x81\x00";
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/*
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addi t0, zero, 1
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addi t1, zero, 0x20
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addi sp, sp, 8
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*/
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uint32_t r_t0 = 0x1234;
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uint32_t r_t1 = 0x7890;
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uint32_t r_pc = 0x0000;
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uint32_t r_sp = 0x1234;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_write(uc, UC_RISCV_REG_SP, &r_sp));
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// emulate the three instructions
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OK(uc_emu_start(uc, code_start, -1, 0, 3));
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_read(uc, UC_RISCV_REG_SP, &r_sp));
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OK(uc_reg_read(uc, UC_RISCV_REG_PC, &r_pc));
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TEST_CHECK(r_t0 == 0x1);
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TEST_CHECK(r_t1 == 0x20);
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TEST_CHECK(r_sp == 0x123c);
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TEST_CHECK(r_pc == (code_start + sizeof(code) - 1));
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OK(uc_close(uc));
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}
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static void test_riscv64_3steps_pc_update()
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{
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uc_engine *uc;
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char code[] = "\x93\x02\x10\x00\x13\x03\x00\x02\x13\x01\x81\x00";
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/*
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addi t0, zero, 1
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addi t1, zero, 0x20
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addi sp, sp, 8
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*/
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uint64_t r_t0 = 0x1234;
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uint64_t r_t1 = 0x7890;
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uint64_t r_pc = 0x0000;
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uint64_t r_sp = 0x1234;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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// initialize machine registers
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OK(uc_reg_write(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_write(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_write(uc, UC_RISCV_REG_SP, &r_sp));
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// emulate the three instructions
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OK(uc_emu_start(uc, code_start, -1, 0, 3));
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OK(uc_reg_read(uc, UC_RISCV_REG_T0, &r_t0));
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OK(uc_reg_read(uc, UC_RISCV_REG_T1, &r_t1));
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OK(uc_reg_read(uc, UC_RISCV_REG_SP, &r_sp));
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OK(uc_reg_read(uc, UC_RISCV_REG_PC, &r_pc));
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TEST_CHECK(r_t0 == 0x1);
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TEST_CHECK(r_t1 == 0x20);
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TEST_CHECK(r_sp == 0x123c);
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TEST_CHECK(r_pc == (code_start + sizeof(code) - 1));
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OK(uc_close(uc));
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}
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TEST_LIST = {{"test_riscv32_nop", test_riscv32_nop},
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{"test_riscv64_nop", test_riscv64_nop},
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{"test_riscv32_3steps_pc_update", test_riscv32_3steps_pc_update},
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{"test_riscv64_3steps_pc_update", test_riscv64_3steps_pc_update},
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{"test_riscv32_until_pc_update", test_riscv32_until_pc_update},
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{"test_riscv64_until_pc_update", test_riscv64_until_pc_update},
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{NULL, NULL}};
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