1048 lines
30 KiB
C
1048 lines
30 KiB
C
/*
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* m68k op helpers
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*
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* Copyright (c) 2006-2007 CodeSourcery
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* Written by Paul Brook
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "exec/helper-proto.h"
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#include "fpu/softfloat.h"
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#define SIGNBIT (1u << 31)
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void HELPER(cf_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
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{
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switch (reg) {
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case M68K_CR_CACR:
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env->cacr = val;
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m68k_switch_sp(env);
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break;
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case M68K_CR_ACR0:
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case M68K_CR_ACR1:
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case M68K_CR_ACR2:
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case M68K_CR_ACR3:
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/* TODO: Implement Access Control Registers. */
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break;
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case M68K_CR_VBR:
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env->vbr = val;
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break;
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/* TODO: Implement control registers. */
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default:
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cpu_abort(env_cpu(env),
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"Unimplemented control register write 0x%x = 0x%x\n",
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reg, val);
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}
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}
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void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
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{
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switch (reg) {
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/* MC680[1234]0 */
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case M68K_CR_SFC:
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env->sfc = val & 7;
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return;
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case M68K_CR_DFC:
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env->dfc = val & 7;
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return;
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case M68K_CR_VBR:
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env->vbr = val;
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return;
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/* MC680[2346]0 */
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case M68K_CR_CACR:
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if (m68k_feature(env, M68K_FEATURE_M68020)) {
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env->cacr = val & 0x0000000f;
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} else if (m68k_feature(env, M68K_FEATURE_M68030)) {
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env->cacr = val & 0x00003f1f;
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} else if (m68k_feature(env, M68K_FEATURE_M68040)) {
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env->cacr = val & 0x80008000;
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} else if (m68k_feature(env, M68K_FEATURE_M68060)) {
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env->cacr = val & 0xf8e0e000;
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}
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m68k_switch_sp(env);
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return;
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/* MC680[34]0 */
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case M68K_CR_TC:
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env->mmu.tcr = val;
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return;
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case M68K_CR_MMUSR:
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env->mmu.mmusr = val;
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return;
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case M68K_CR_SRP:
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env->mmu.srp = val;
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return;
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case M68K_CR_URP:
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env->mmu.urp = val;
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return;
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case M68K_CR_USP:
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env->sp[M68K_USP] = val;
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return;
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case M68K_CR_MSP:
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env->sp[M68K_SSP] = val;
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return;
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case M68K_CR_ISP:
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env->sp[M68K_ISP] = val;
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return;
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/* MC68040/MC68LC040 */
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case M68K_CR_ITT0:
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env->mmu.ttr[M68K_ITTR0] = val;
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return;
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case M68K_CR_ITT1:
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env->mmu.ttr[M68K_ITTR1] = val;
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return;
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case M68K_CR_DTT0:
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env->mmu.ttr[M68K_DTTR0] = val;
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return;
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case M68K_CR_DTT1:
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env->mmu.ttr[M68K_DTTR1] = val;
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return;
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}
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cpu_abort(env_cpu(env),
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"Unimplemented control register write 0x%x = 0x%x\n",
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reg, val);
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}
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uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
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{
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switch (reg) {
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/* MC680[1234]0 */
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case M68K_CR_SFC:
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return env->sfc;
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case M68K_CR_DFC:
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return env->dfc;
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case M68K_CR_VBR:
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return env->vbr;
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/* MC680[234]0 */
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case M68K_CR_CACR:
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return env->cacr;
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/* MC680[34]0 */
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case M68K_CR_TC:
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return env->mmu.tcr;
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case M68K_CR_MMUSR:
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return env->mmu.mmusr;
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case M68K_CR_SRP:
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return env->mmu.srp;
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case M68K_CR_USP:
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return env->sp[M68K_USP];
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case M68K_CR_MSP:
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return env->sp[M68K_SSP];
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case M68K_CR_ISP:
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return env->sp[M68K_ISP];
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/* MC68040/MC68LC040 */
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case M68K_CR_URP:
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return env->mmu.urp;
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case M68K_CR_ITT0:
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return env->mmu.ttr[M68K_ITTR0];
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case M68K_CR_ITT1:
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return env->mmu.ttr[M68K_ITTR1];
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case M68K_CR_DTT0:
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return env->mmu.ttr[M68K_DTTR0];
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case M68K_CR_DTT1:
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return env->mmu.ttr[M68K_DTTR1];
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}
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cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n",
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reg);
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}
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void HELPER(set_macsr)(CPUM68KState *env, uint32_t val)
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{
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uint32_t acc;
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int8_t exthigh;
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uint8_t extlow;
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uint64_t regval;
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int i;
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if ((env->macsr ^ val) & (MACSR_FI | MACSR_SU)) {
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for (i = 0; i < 4; i++) {
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regval = env->macc[i];
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exthigh = regval >> 40;
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if (env->macsr & MACSR_FI) {
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acc = regval >> 8;
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extlow = regval;
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} else {
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acc = regval;
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extlow = regval >> 32;
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}
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if (env->macsr & MACSR_FI) {
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regval = (((uint64_t)acc) << 8) | extlow;
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regval |= ((int64_t)exthigh) << 40;
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} else if (env->macsr & MACSR_SU) {
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regval = acc | (((int64_t)extlow) << 32);
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regval |= ((int64_t)exthigh) << 40;
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} else {
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regval = acc | (((uint64_t)extlow) << 32);
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regval |= ((uint64_t)(uint8_t)exthigh) << 40;
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}
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env->macc[i] = regval;
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}
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}
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env->macsr = val;
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}
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void m68k_switch_sp(CPUM68KState *env)
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{
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int new_sp;
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env->sp[env->current_sp] = env->aregs[7];
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if (m68k_feature(env, M68K_FEATURE_M68000)) {
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if (env->sr & SR_S) {
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if (env->sr & SR_M) {
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new_sp = M68K_SSP;
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} else {
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new_sp = M68K_ISP;
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}
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} else {
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new_sp = M68K_USP;
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}
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} else {
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new_sp = (env->sr & SR_S && env->cacr & M68K_CACR_EUSP)
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? M68K_SSP : M68K_USP;
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}
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env->aregs[7] = env->sp[new_sp];
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env->current_sp = new_sp;
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}
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static int check_TTR(uint32_t ttr, int *prot, target_ulong addr,
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int access_type)
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{
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uint32_t base, mask;
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/* check if transparent translation is enabled */
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if ((ttr & M68K_TTR_ENABLED) == 0) {
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return 0;
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}
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/* check mode access */
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switch (ttr & M68K_TTR_SFIELD) {
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case M68K_TTR_SFIELD_USER:
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/* match only if user */
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if ((access_type & ACCESS_SUPER) != 0) {
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return 0;
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}
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break;
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case M68K_TTR_SFIELD_SUPER:
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/* match only if supervisor */
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if ((access_type & ACCESS_SUPER) == 0) {
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return 0;
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}
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break;
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default:
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/* all other values disable mode matching (FC2) */
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break;
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}
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/* check address matching */
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base = ttr & M68K_TTR_ADDR_BASE;
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mask = (ttr & M68K_TTR_ADDR_MASK) ^ M68K_TTR_ADDR_MASK;
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mask <<= M68K_TTR_ADDR_MASK_SHIFT;
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if ((addr & mask) != (base & mask)) {
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return 0;
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}
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*prot = PAGE_READ | PAGE_EXEC;
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if ((ttr & M68K_DESC_WRITEPROT) == 0) {
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*prot |= PAGE_WRITE;
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}
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return 1;
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}
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static int get_physical_address(CPUM68KState *env, hwaddr *physical,
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int *prot, target_ulong address,
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int access_type, target_ulong *page_size)
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{
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CPUState *cs = env_cpu(env);
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uint32_t entry;
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uint32_t next;
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target_ulong page_mask;
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bool debug = access_type & ACCESS_DEBUG;
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int page_bits;
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int i;
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MemTxResult txres;
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/* Transparent Translation (physical = logical) */
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for (i = 0; i < M68K_MAX_TTR; i++) {
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if (check_TTR(env->mmu.TTR(access_type, i),
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prot, address, access_type)) {
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if (access_type & ACCESS_PTEST) {
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/* Transparent Translation Register bit */
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env->mmu.mmusr = M68K_MMU_T_040 | M68K_MMU_R_040;
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}
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*physical = address & TARGET_PAGE_MASK;
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*page_size = TARGET_PAGE_SIZE;
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return 0;
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}
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}
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/* Page Table Root Pointer */
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*prot = PAGE_READ | PAGE_WRITE;
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if (access_type & ACCESS_CODE) {
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*prot |= PAGE_EXEC;
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}
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if (access_type & ACCESS_SUPER) {
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next = env->mmu.srp;
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} else {
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next = env->mmu.urp;
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}
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/* Root Index */
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entry = M68K_POINTER_BASE(next) | M68K_ROOT_INDEX(address);
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next = glue(address_space_ldl, UNICORN_ARCH_POSTFIX)(cs->as->uc, cs->as, entry, MEMTXATTRS_UNSPECIFIED, &txres);
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if (txres != MEMTX_OK) {
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goto txfail;
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}
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if (!M68K_UDT_VALID(next)) {
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return -1;
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}
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if (!(next & M68K_DESC_USED) && !debug) {
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glue(address_space_stl, UNICORN_ARCH_POSTFIX)(cs->as->uc, cs->as, entry, next | M68K_DESC_USED,
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MEMTXATTRS_UNSPECIFIED, &txres);
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if (txres != MEMTX_OK) {
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goto txfail;
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}
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}
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if (next & M68K_DESC_WRITEPROT) {
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if (access_type & ACCESS_PTEST) {
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env->mmu.mmusr |= M68K_MMU_WP_040;
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}
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*prot &= ~PAGE_WRITE;
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if (access_type & ACCESS_STORE) {
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return -1;
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}
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}
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/* Pointer Index */
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entry = M68K_POINTER_BASE(next) | M68K_POINTER_INDEX(address);
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next = glue(address_space_ldl, UNICORN_ARCH_POSTFIX)(cs->as->uc, cs->as, entry, MEMTXATTRS_UNSPECIFIED, &txres);
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if (txres != MEMTX_OK) {
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goto txfail;
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}
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if (!M68K_UDT_VALID(next)) {
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return -1;
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}
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if (!(next & M68K_DESC_USED) && !debug) {
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glue(address_space_stl, UNICORN_ARCH_POSTFIX)(cs->as->uc, cs->as, entry, next | M68K_DESC_USED,
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MEMTXATTRS_UNSPECIFIED, &txres);
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if (txres != MEMTX_OK) {
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goto txfail;
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}
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}
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if (next & M68K_DESC_WRITEPROT) {
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if (access_type & ACCESS_PTEST) {
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env->mmu.mmusr |= M68K_MMU_WP_040;
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}
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*prot &= ~PAGE_WRITE;
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if (access_type & ACCESS_STORE) {
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return -1;
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}
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}
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/* Page Index */
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if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
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entry = M68K_8K_PAGE_BASE(next) | M68K_8K_PAGE_INDEX(address);
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} else {
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entry = M68K_4K_PAGE_BASE(next) | M68K_4K_PAGE_INDEX(address);
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}
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next = glue(address_space_ldl, UNICORN_ARCH_POSTFIX)(cs->as->uc, cs->as, entry, MEMTXATTRS_UNSPECIFIED, &txres);
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if (txres != MEMTX_OK) {
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goto txfail;
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}
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if (!M68K_PDT_VALID(next)) {
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return -1;
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}
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if (M68K_PDT_INDIRECT(next)) {
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next = glue(address_space_ldl, UNICORN_ARCH_POSTFIX)(cs->as->uc, cs->as, M68K_INDIRECT_POINTER(next),
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MEMTXATTRS_UNSPECIFIED, &txres);
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if (txres != MEMTX_OK) {
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goto txfail;
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}
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}
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if (access_type & ACCESS_STORE) {
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if (next & M68K_DESC_WRITEPROT) {
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if (!(next & M68K_DESC_USED) && !debug) {
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glue(address_space_stl, UNICORN_ARCH_POSTFIX)(cs->as->uc, cs->as, entry, next | M68K_DESC_USED,
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MEMTXATTRS_UNSPECIFIED, &txres);
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if (txres != MEMTX_OK) {
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goto txfail;
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}
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}
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} else if ((next & (M68K_DESC_MODIFIED | M68K_DESC_USED)) !=
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(M68K_DESC_MODIFIED | M68K_DESC_USED) && !debug) {
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glue(address_space_stl, UNICORN_ARCH_POSTFIX)(cs->as->uc, cs->as, entry,
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next | (M68K_DESC_MODIFIED | M68K_DESC_USED),
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MEMTXATTRS_UNSPECIFIED, &txres);
|
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if (txres != MEMTX_OK) {
|
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goto txfail;
|
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}
|
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}
|
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} else {
|
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if (!(next & M68K_DESC_USED) && !debug) {
|
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glue(address_space_stl, UNICORN_ARCH_POSTFIX)(cs->as->uc, cs->as, entry, next | M68K_DESC_USED,
|
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MEMTXATTRS_UNSPECIFIED, &txres);
|
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if (txres != MEMTX_OK) {
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goto txfail;
|
|
}
|
|
}
|
|
}
|
|
|
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if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
|
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page_bits = 13;
|
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} else {
|
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page_bits = 12;
|
|
}
|
|
*page_size = 1 << page_bits;
|
|
page_mask = ~(*page_size - 1);
|
|
*physical = next & page_mask;
|
|
|
|
if (access_type & ACCESS_PTEST) {
|
|
env->mmu.mmusr |= next & M68K_MMU_SR_MASK_040;
|
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env->mmu.mmusr |= *physical & 0xfffff000;
|
|
env->mmu.mmusr |= M68K_MMU_R_040;
|
|
}
|
|
|
|
if (next & M68K_DESC_WRITEPROT) {
|
|
*prot &= ~PAGE_WRITE;
|
|
if (access_type & ACCESS_STORE) {
|
|
return -1;
|
|
}
|
|
}
|
|
if (next & M68K_DESC_SUPERONLY) {
|
|
if ((access_type & ACCESS_SUPER) == 0) {
|
|
return -1;
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
|
|
txfail:
|
|
/*
|
|
* A page table load/store failed. TODO: we should really raise a
|
|
* suitable guest fault here if this is not a debug access.
|
|
* For now just return that the translation failed.
|
|
*/
|
|
return -1;
|
|
}
|
|
|
|
hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
|
{
|
|
M68kCPU *cpu = M68K_CPU(cs);
|
|
CPUM68KState *env = &cpu->env;
|
|
hwaddr phys_addr;
|
|
int prot;
|
|
int access_type;
|
|
target_ulong page_size;
|
|
|
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if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
|
|
/* MMU disabled */
|
|
return addr;
|
|
}
|
|
|
|
access_type = ACCESS_DATA | ACCESS_DEBUG;
|
|
if (env->sr & SR_S) {
|
|
access_type |= ACCESS_SUPER;
|
|
}
|
|
if (get_physical_address(env, &phys_addr, &prot,
|
|
addr, access_type, &page_size) != 0) {
|
|
return -1;
|
|
}
|
|
return phys_addr;
|
|
}
|
|
|
|
/*
|
|
* Notify CPU of a pending interrupt. Prioritization and vectoring should
|
|
* be handled by the interrupt controller. Real hardware only requests
|
|
* the vector when the interrupt is acknowledged by the CPU. For
|
|
* simplicity we calculate it when the interrupt is signalled.
|
|
*/
|
|
void m68k_set_irq_level(M68kCPU *cpu, int level, uint8_t vector)
|
|
{
|
|
CPUState *cs = CPU(cpu);
|
|
CPUM68KState *env = &cpu->env;
|
|
|
|
env->pending_level = level;
|
|
env->pending_vector = vector;
|
|
if (level) {
|
|
cpu_interrupt(cs, CPU_INTERRUPT_HARD);
|
|
} else {
|
|
cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
|
|
}
|
|
}
|
|
|
|
bool m68k_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
|
|
MMUAccessType qemu_access_type, int mmu_idx,
|
|
bool probe, uintptr_t retaddr)
|
|
{
|
|
M68kCPU *cpu = M68K_CPU(cs);
|
|
CPUM68KState *env = &cpu->env;
|
|
|
|
hwaddr physical;
|
|
int prot;
|
|
int access_type;
|
|
int ret;
|
|
target_ulong page_size;
|
|
|
|
if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
|
|
/* MMU disabled */
|
|
tlb_set_page(cs, address & TARGET_PAGE_MASK,
|
|
address & TARGET_PAGE_MASK,
|
|
PAGE_READ | PAGE_WRITE | PAGE_EXEC,
|
|
mmu_idx, TARGET_PAGE_SIZE);
|
|
return true;
|
|
}
|
|
|
|
if (qemu_access_type == MMU_INST_FETCH) {
|
|
access_type = ACCESS_CODE;
|
|
} else {
|
|
access_type = ACCESS_DATA;
|
|
if (qemu_access_type == MMU_DATA_STORE) {
|
|
access_type |= ACCESS_STORE;
|
|
}
|
|
}
|
|
if (mmu_idx != MMU_USER_IDX) {
|
|
access_type |= ACCESS_SUPER;
|
|
}
|
|
|
|
ret = get_physical_address(&cpu->env, &physical, &prot,
|
|
address, access_type, &page_size);
|
|
if (likely(ret == 0)) {
|
|
address &= TARGET_PAGE_MASK;
|
|
physical += address & (page_size - 1);
|
|
tlb_set_page(cs, address, physical,
|
|
prot, mmu_idx, TARGET_PAGE_SIZE);
|
|
return true;
|
|
}
|
|
|
|
if (probe) {
|
|
return false;
|
|
}
|
|
|
|
/* page fault */
|
|
env->mmu.ssw = M68K_ATC_040;
|
|
switch (size) {
|
|
case 1:
|
|
env->mmu.ssw |= M68K_BA_SIZE_BYTE;
|
|
break;
|
|
case 2:
|
|
env->mmu.ssw |= M68K_BA_SIZE_WORD;
|
|
break;
|
|
case 4:
|
|
env->mmu.ssw |= M68K_BA_SIZE_LONG;
|
|
break;
|
|
}
|
|
if (access_type & ACCESS_SUPER) {
|
|
env->mmu.ssw |= M68K_TM_040_SUPER;
|
|
}
|
|
if (access_type & ACCESS_CODE) {
|
|
env->mmu.ssw |= M68K_TM_040_CODE;
|
|
} else {
|
|
env->mmu.ssw |= M68K_TM_040_DATA;
|
|
}
|
|
if (!(access_type & ACCESS_STORE)) {
|
|
env->mmu.ssw |= M68K_RW_040;
|
|
}
|
|
|
|
cs->exception_index = EXCP_ACCESS;
|
|
env->mmu.ar = address;
|
|
cpu_loop_exit_restore(cs, retaddr);
|
|
}
|
|
|
|
uint32_t HELPER(bitrev)(uint32_t x)
|
|
{
|
|
x = ((x >> 1) & 0x55555555u) | ((x << 1) & 0xaaaaaaaau);
|
|
x = ((x >> 2) & 0x33333333u) | ((x << 2) & 0xccccccccu);
|
|
x = ((x >> 4) & 0x0f0f0f0fu) | ((x << 4) & 0xf0f0f0f0u);
|
|
return bswap32(x);
|
|
}
|
|
|
|
uint32_t HELPER(ff1)(uint32_t x)
|
|
{
|
|
int n;
|
|
for (n = 32; x; n--)
|
|
x >>= 1;
|
|
return n;
|
|
}
|
|
|
|
uint32_t HELPER(sats)(uint32_t val, uint32_t v)
|
|
{
|
|
/* The result has the opposite sign to the original value. */
|
|
if ((int32_t)v < 0) {
|
|
val = (((int32_t)val) >> 31) ^ SIGNBIT;
|
|
}
|
|
return val;
|
|
}
|
|
|
|
void cpu_m68k_set_sr(CPUM68KState *env, uint32_t sr)
|
|
{
|
|
env->sr = sr & 0xffe0;
|
|
cpu_m68k_set_ccr(env, sr);
|
|
m68k_switch_sp(env);
|
|
}
|
|
|
|
void HELPER(set_sr)(CPUM68KState *env, uint32_t val)
|
|
{
|
|
cpu_m68k_set_sr(env, val);
|
|
}
|
|
|
|
/* MAC unit. */
|
|
/*
|
|
* FIXME: The MAC unit implementation is a bit of a mess. Some helpers
|
|
* take values, others take register numbers and manipulate the contents
|
|
* in-place.
|
|
*/
|
|
void HELPER(mac_move)(CPUM68KState *env, uint32_t dest, uint32_t src)
|
|
{
|
|
uint32_t mask;
|
|
env->macc[dest] = env->macc[src];
|
|
mask = MACSR_PAV0 << dest;
|
|
if (env->macsr & (MACSR_PAV0 << src))
|
|
env->macsr |= mask;
|
|
else
|
|
env->macsr &= ~mask;
|
|
}
|
|
|
|
uint64_t HELPER(macmuls)(CPUM68KState *env, uint32_t op1, uint32_t op2)
|
|
{
|
|
int64_t product;
|
|
int64_t res;
|
|
|
|
product = (uint64_t)op1 * op2;
|
|
res = (product << 24) >> 24;
|
|
if (res != product) {
|
|
env->macsr |= MACSR_V;
|
|
if (env->macsr & MACSR_OMC) {
|
|
/* Make sure the accumulate operation overflows. */
|
|
if (product < 0)
|
|
res = ~(1ll << 50);
|
|
else
|
|
res = 1ll << 50;
|
|
}
|
|
}
|
|
return res;
|
|
}
|
|
|
|
uint64_t HELPER(macmulu)(CPUM68KState *env, uint32_t op1, uint32_t op2)
|
|
{
|
|
uint64_t product;
|
|
|
|
product = (uint64_t)op1 * op2;
|
|
if (product & (0xffffffull << 40)) {
|
|
env->macsr |= MACSR_V;
|
|
if (env->macsr & MACSR_OMC) {
|
|
/* Make sure the accumulate operation overflows. */
|
|
product = 1ll << 50;
|
|
} else {
|
|
product &= ((1ull << 40) - 1);
|
|
}
|
|
}
|
|
return product;
|
|
}
|
|
|
|
uint64_t HELPER(macmulf)(CPUM68KState *env, uint32_t op1, uint32_t op2)
|
|
{
|
|
uint64_t product;
|
|
uint32_t remainder;
|
|
|
|
product = (uint64_t)op1 * op2;
|
|
if (env->macsr & MACSR_RT) {
|
|
remainder = product & 0xffffff;
|
|
product >>= 24;
|
|
if (remainder > 0x800000)
|
|
product++;
|
|
else if (remainder == 0x800000)
|
|
product += (product & 1);
|
|
} else {
|
|
product >>= 24;
|
|
}
|
|
return product;
|
|
}
|
|
|
|
void HELPER(macsats)(CPUM68KState *env, uint32_t acc)
|
|
{
|
|
int64_t tmp;
|
|
int64_t result;
|
|
tmp = env->macc[acc];
|
|
result = ((tmp << 16) >> 16);
|
|
if (result != tmp) {
|
|
env->macsr |= MACSR_V;
|
|
}
|
|
if (env->macsr & MACSR_V) {
|
|
env->macsr |= MACSR_PAV0 << acc;
|
|
if (env->macsr & MACSR_OMC) {
|
|
/*
|
|
* The result is saturated to 32 bits, despite overflow occurring
|
|
* at 48 bits. Seems weird, but that's what the hardware docs
|
|
* say.
|
|
*/
|
|
result = (result >> 63) ^ 0x7fffffff;
|
|
}
|
|
}
|
|
env->macc[acc] = result;
|
|
}
|
|
|
|
void HELPER(macsatu)(CPUM68KState *env, uint32_t acc)
|
|
{
|
|
uint64_t val;
|
|
|
|
val = env->macc[acc];
|
|
if (val & (0xffffull << 48)) {
|
|
env->macsr |= MACSR_V;
|
|
}
|
|
if (env->macsr & MACSR_V) {
|
|
env->macsr |= MACSR_PAV0 << acc;
|
|
if (env->macsr & MACSR_OMC) {
|
|
if (val > (1ull << 53))
|
|
val = 0;
|
|
else
|
|
val = (1ull << 48) - 1;
|
|
} else {
|
|
val &= ((1ull << 48) - 1);
|
|
}
|
|
}
|
|
env->macc[acc] = val;
|
|
}
|
|
|
|
void HELPER(macsatf)(CPUM68KState *env, uint32_t acc)
|
|
{
|
|
int64_t sum;
|
|
int64_t result;
|
|
|
|
sum = env->macc[acc];
|
|
result = (sum << 16) >> 16;
|
|
if (result != sum) {
|
|
env->macsr |= MACSR_V;
|
|
}
|
|
if (env->macsr & MACSR_V) {
|
|
env->macsr |= MACSR_PAV0 << acc;
|
|
if (env->macsr & MACSR_OMC) {
|
|
result = (result >> 63) ^ 0x7fffffffffffll;
|
|
}
|
|
}
|
|
env->macc[acc] = result;
|
|
}
|
|
|
|
void HELPER(mac_set_flags)(CPUM68KState *env, uint32_t acc)
|
|
{
|
|
uint64_t val;
|
|
val = env->macc[acc];
|
|
if (val == 0) {
|
|
env->macsr |= MACSR_Z;
|
|
} else if (val & (1ull << 47)) {
|
|
env->macsr |= MACSR_N;
|
|
}
|
|
if (env->macsr & (MACSR_PAV0 << acc)) {
|
|
env->macsr |= MACSR_V;
|
|
}
|
|
if (env->macsr & MACSR_FI) {
|
|
val = ((int64_t)val) >> 40;
|
|
if (val != 0 && val != -1)
|
|
env->macsr |= MACSR_EV;
|
|
} else if (env->macsr & MACSR_SU) {
|
|
val = ((int64_t)val) >> 32;
|
|
if (val != 0 && val != -1)
|
|
env->macsr |= MACSR_EV;
|
|
} else {
|
|
if ((val >> 32) != 0)
|
|
env->macsr |= MACSR_EV;
|
|
}
|
|
}
|
|
|
|
#define EXTSIGN(val, index) ( \
|
|
(index == 0) ? (int8_t)(val) : ((index == 1) ? (int16_t)(val) : (val)) \
|
|
)
|
|
|
|
#define COMPUTE_CCR(op, x, n, z, v, c) { \
|
|
switch (op) { \
|
|
case CC_OP_FLAGS: \
|
|
/* Everything in place. */ \
|
|
break; \
|
|
case CC_OP_ADDB: \
|
|
case CC_OP_ADDW: \
|
|
case CC_OP_ADDL: \
|
|
res = n; \
|
|
src2 = v; \
|
|
src1 = EXTSIGN(res - src2, op - CC_OP_ADDB); \
|
|
c = x; \
|
|
z = n; \
|
|
v = (res ^ src1) & ~(src1 ^ src2); \
|
|
break; \
|
|
case CC_OP_SUBB: \
|
|
case CC_OP_SUBW: \
|
|
case CC_OP_SUBL: \
|
|
res = n; \
|
|
src2 = v; \
|
|
src1 = EXTSIGN(res + src2, op - CC_OP_SUBB); \
|
|
c = x; \
|
|
z = n; \
|
|
v = (res ^ src1) & (src1 ^ src2); \
|
|
break; \
|
|
case CC_OP_CMPB: \
|
|
case CC_OP_CMPW: \
|
|
case CC_OP_CMPL: \
|
|
src1 = n; \
|
|
src2 = v; \
|
|
res = EXTSIGN(src1 - src2, op - CC_OP_CMPB); \
|
|
n = res; \
|
|
z = res; \
|
|
c = src1 < src2; \
|
|
v = (res ^ src1) & (src1 ^ src2); \
|
|
break; \
|
|
case CC_OP_LOGIC: \
|
|
c = v = 0; \
|
|
z = n; \
|
|
break; \
|
|
default: \
|
|
cpu_abort(env_cpu(env), "Bad CC_OP %d", op); \
|
|
} \
|
|
} while (0)
|
|
|
|
uint32_t cpu_m68k_get_ccr(CPUM68KState *env)
|
|
{
|
|
uint32_t x, c, n, z, v;
|
|
uint32_t res, src1, src2;
|
|
|
|
x = env->cc_x;
|
|
n = env->cc_n;
|
|
z = env->cc_z;
|
|
v = env->cc_v;
|
|
c = env->cc_c;
|
|
|
|
COMPUTE_CCR(env->cc_op, x, n, z, v, c);
|
|
|
|
n = n >> 31;
|
|
z = (z == 0);
|
|
v = v >> 31;
|
|
|
|
return x * CCF_X + n * CCF_N + z * CCF_Z + v * CCF_V + c * CCF_C;
|
|
}
|
|
|
|
uint32_t HELPER(get_ccr)(CPUM68KState *env)
|
|
{
|
|
return cpu_m68k_get_ccr(env);
|
|
}
|
|
|
|
void cpu_m68k_set_ccr(CPUM68KState *env, uint32_t ccr)
|
|
{
|
|
env->cc_x = (ccr & CCF_X ? 1 : 0);
|
|
env->cc_n = (ccr & CCF_N ? -1 : 0);
|
|
env->cc_z = (ccr & CCF_Z ? 0 : 1);
|
|
env->cc_v = (ccr & CCF_V ? -1 : 0);
|
|
env->cc_c = (ccr & CCF_C ? 1 : 0);
|
|
env->cc_op = CC_OP_FLAGS;
|
|
}
|
|
|
|
void HELPER(set_ccr)(CPUM68KState *env, uint32_t ccr)
|
|
{
|
|
cpu_m68k_set_ccr(env, ccr);
|
|
}
|
|
|
|
void HELPER(flush_flags)(CPUM68KState *env, uint32_t cc_op)
|
|
{
|
|
uint32_t res, src1, src2;
|
|
|
|
COMPUTE_CCR(cc_op, env->cc_x, env->cc_n, env->cc_z, env->cc_v, env->cc_c);
|
|
env->cc_op = CC_OP_FLAGS;
|
|
}
|
|
|
|
uint32_t HELPER(get_macf)(CPUM68KState *env, uint64_t val)
|
|
{
|
|
int rem;
|
|
uint32_t result;
|
|
|
|
if (env->macsr & MACSR_SU) {
|
|
/* 16-bit rounding. */
|
|
rem = val & 0xffffff;
|
|
val = (val >> 24) & 0xffffu;
|
|
if (rem > 0x800000)
|
|
val++;
|
|
else if (rem == 0x800000)
|
|
val += (val & 1);
|
|
} else if (env->macsr & MACSR_RT) {
|
|
/* 32-bit rounding. */
|
|
rem = val & 0xff;
|
|
val >>= 8;
|
|
if (rem > 0x80)
|
|
val++;
|
|
else if (rem == 0x80)
|
|
val += (val & 1);
|
|
} else {
|
|
/* No rounding. */
|
|
val >>= 8;
|
|
}
|
|
if (env->macsr & MACSR_OMC) {
|
|
/* Saturate. */
|
|
if (env->macsr & MACSR_SU) {
|
|
if (val != (uint16_t) val) {
|
|
result = ((val >> 63) ^ 0x7fff) & 0xffff;
|
|
} else {
|
|
result = val & 0xffff;
|
|
}
|
|
} else {
|
|
if (val != (uint32_t)val) {
|
|
result = ((uint32_t)(val >> 63) & 0x7fffffff);
|
|
} else {
|
|
result = (uint32_t)val;
|
|
}
|
|
}
|
|
} else {
|
|
/* No saturation. */
|
|
if (env->macsr & MACSR_SU) {
|
|
result = val & 0xffff;
|
|
} else {
|
|
result = (uint32_t)val;
|
|
}
|
|
}
|
|
return result;
|
|
}
|
|
|
|
uint32_t HELPER(get_macs)(uint64_t val)
|
|
{
|
|
if (val == (int32_t)val) {
|
|
return (int32_t)val;
|
|
} else {
|
|
return (val >> 61) ^ ~SIGNBIT;
|
|
}
|
|
}
|
|
|
|
uint32_t HELPER(get_macu)(uint64_t val)
|
|
{
|
|
if ((val >> 32) == 0) {
|
|
return (uint32_t)val;
|
|
} else {
|
|
return 0xffffffffu;
|
|
}
|
|
}
|
|
|
|
uint32_t HELPER(get_mac_extf)(CPUM68KState *env, uint32_t acc)
|
|
{
|
|
uint32_t val;
|
|
val = env->macc[acc] & 0x00ff;
|
|
val |= (env->macc[acc] >> 32) & 0xff00;
|
|
val |= (env->macc[acc + 1] << 16) & 0x00ff0000;
|
|
val |= (env->macc[acc + 1] >> 16) & 0xff000000;
|
|
return val;
|
|
}
|
|
|
|
uint32_t HELPER(get_mac_exti)(CPUM68KState *env, uint32_t acc)
|
|
{
|
|
uint32_t val;
|
|
val = (env->macc[acc] >> 32) & 0xffff;
|
|
val |= (env->macc[acc + 1] >> 16) & 0xffff0000;
|
|
return val;
|
|
}
|
|
|
|
void HELPER(set_mac_extf)(CPUM68KState *env, uint32_t val, uint32_t acc)
|
|
{
|
|
int64_t res;
|
|
int32_t tmp;
|
|
res = env->macc[acc] & 0xffffffff00ull;
|
|
tmp = (int16_t)(val & 0xff00);
|
|
res |= ((int64_t)tmp) << 32;
|
|
res |= val & 0xff;
|
|
env->macc[acc] = res;
|
|
res = env->macc[acc + 1] & 0xffffffff00ull;
|
|
tmp = (val & 0xff000000);
|
|
res |= ((int64_t)tmp) << 16;
|
|
res |= (val >> 16) & 0xff;
|
|
env->macc[acc + 1] = res;
|
|
}
|
|
|
|
void HELPER(set_mac_exts)(CPUM68KState *env, uint32_t val, uint32_t acc)
|
|
{
|
|
int64_t res;
|
|
int32_t tmp;
|
|
res = (uint32_t)env->macc[acc];
|
|
tmp = (int16_t)val;
|
|
res |= ((int64_t)tmp) << 32;
|
|
env->macc[acc] = res;
|
|
res = (uint32_t)env->macc[acc + 1];
|
|
tmp = val & 0xffff0000;
|
|
res |= (int64_t)tmp << 16;
|
|
env->macc[acc + 1] = res;
|
|
}
|
|
|
|
void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t val, uint32_t acc)
|
|
{
|
|
uint64_t res;
|
|
res = (uint32_t)env->macc[acc];
|
|
res |= ((uint64_t)(val & 0xffff)) << 32;
|
|
env->macc[acc] = res;
|
|
res = (uint32_t)env->macc[acc + 1];
|
|
res |= (uint64_t)(val & 0xffff0000) << 16;
|
|
env->macc[acc + 1] = res;
|
|
}
|
|
|
|
void HELPER(ptest)(CPUM68KState *env, uint32_t addr, uint32_t is_read)
|
|
{
|
|
hwaddr physical;
|
|
int access_type;
|
|
int prot;
|
|
int ret;
|
|
target_ulong page_size;
|
|
|
|
access_type = ACCESS_PTEST;
|
|
if (env->dfc & 4) {
|
|
access_type |= ACCESS_SUPER;
|
|
}
|
|
if ((env->dfc & 3) == 2) {
|
|
access_type |= ACCESS_CODE;
|
|
}
|
|
if (!is_read) {
|
|
access_type |= ACCESS_STORE;
|
|
}
|
|
|
|
env->mmu.mmusr = 0;
|
|
env->mmu.ssw = 0;
|
|
ret = get_physical_address(env, &physical, &prot, addr,
|
|
access_type, &page_size);
|
|
if (ret == 0) {
|
|
addr &= TARGET_PAGE_MASK;
|
|
physical += addr & (page_size - 1);
|
|
tlb_set_page(env_cpu(env), addr, physical,
|
|
prot, access_type & ACCESS_SUPER ?
|
|
MMU_KERNEL_IDX : MMU_USER_IDX, page_size);
|
|
}
|
|
}
|
|
|
|
void HELPER(pflush)(CPUM68KState *env, uint32_t addr, uint32_t opmode)
|
|
{
|
|
CPUState *cs = env_cpu(env);
|
|
|
|
switch (opmode) {
|
|
case 0: /* Flush page entry if not global */
|
|
case 1: /* Flush page entry */
|
|
tlb_flush_page(cs, addr);
|
|
break;
|
|
case 2: /* Flush all except global entries */
|
|
tlb_flush(cs);
|
|
break;
|
|
case 3: /* Flush all entries */
|
|
tlb_flush(cs);
|
|
break;
|
|
}
|
|
}
|
|
|
|
void HELPER(reset)(CPUM68KState *env)
|
|
{
|
|
/* FIXME: reset all except CPU */
|
|
}
|