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Commit Graph

105 Commits

Author SHA1 Message Date
mio
fdbd743c21
Remove hard-coded cpu model 2021-12-30 00:54:55 +01:00
mio
a72cbda6de
Initialize empty structs explictly to build on MSVC 2021-12-30 00:51:07 +01:00
mio
03f9dd8b61
Expand case ranges to build on MSVC 2021-12-30 00:42:13 +01:00
mio
ab4ef2e1de
Fix MSVC build and remove warning about unused functions 2021-12-30 00:26:25 +01:00
mio
034a1aa5f2
Make s390x stopping mechanism work 2021-12-27 23:48:20 +01:00
mio
a38151bf77
Make s390x skey work 2021-12-27 23:19:17 +01:00
mio
e977f81813
Make s390x build 2021-12-26 23:09:25 +01:00
mio
faa689c0f0
Merge systemz to the latest uc2 codebase 2021-12-26 22:58:32 +01:00
lazymio
cddc9cf2ed
Fix arm post init 2021-12-25 00:16:51 +01:00
lazymio
4f73d75ea8
Fix #1500 2021-12-23 21:46:27 +01:00
lazymio
ef6f8a2427
Fix x86 CPUID 2021-12-22 23:39:41 +01:00
lazymio
7bb756249a
Better design of cpuid instruction hook 2021-12-22 20:36:56 +01:00
Nguyen Anh Quynh
09b0c66f11 move all static vars in translate.c to tcg.h 2021-12-07 04:53:32 +08:00
Nguyen Anh Quynh
b042a6a01d add missing files 2021-12-06 04:28:13 +08:00
lazymio
8a0ca8715e
Fix SR read/write and a test 2021-12-04 23:22:28 +01:00
Brandon Miller
d204dc6374
Added SR to M68K reg_read and reg_write (#1507) 2021-12-02 14:12:49 +08:00
lazymio
221cde18df
Write CPSR as it is initiated from instructions to allow regs switch 2021-11-24 17:10:51 +01:00
lazymio
87a391d549
Inline uc_tracecode when there is only exactly one hook 2021-11-21 16:44:39 +01:00
lazymio
23ef5da491
Merge pull request #1481 from bet4it/cp15 
Restore cp15 registers
 2021-11-09 16:50:31 +01:00
Bet4
acaed986b5 Restore cp15 registers 2021-11-09 13:13:08 +08:00
lazymio
640251e1aa
Leave out size parameter in callback 2021-11-09 00:21:34 +01:00
lazymio
c6fdbb3735
Add RISCV CSR registers 2021-11-07 20:36:04 +01:00
George Hotz
7268c2a19b
mips: support reading and writing of hi/lo regs 2021-11-07 20:27:02 +01:00
lazymio
613ddf0985
Format 2021-11-04 19:58:44 +01:00
lazymio
871de4ad65
Split mips cpu to 32 and 64 2021-11-04 19:58:32 +01:00
lazymio
0555095388
Support changing cpu model for ppc 2021-11-04 19:53:02 +01:00
lazymio
e5a2eae173
Add comment for default cpu model 2021-11-04 19:22:50 +01:00
lazymio
64452e249d
Support changing cpu model for sparc 2021-11-04 19:22:08 +01:00
lazymio
b0280f5e55
Support changing cpu model for m68k 2021-11-04 19:16:35 +01:00
lazymio
172a2fbe6d
Support changing cpu model for riscv 2021-11-04 19:13:53 +01:00
lazymio
435ac71f47
Support changing cpu model for x86 2021-11-04 19:10:29 +01:00
lazymio
837c3be347
Support changing cpu model for MIPS 2021-11-04 19:05:56 +01:00
lazymio
dfbffa44ec
Support changing cpu model for ARM 2021-11-04 18:37:10 +01:00
lazymio
6b5529fcb7
Merge pull request #1458 from bet4it/patch 
Port some patches from Unicorn1 to Unicorn2
 2021-11-03 20:59:42 +01:00
lazymio
9818840f4e
Add tests for UC_HOOK_TCG_OPCODE 2021-11-03 20:56:45 +01:00
lazymio
09aa0f944f
Merge QDucasse:riscv_extension_d 
Fix and close #1469

Fix test for riscv float points

Fix the riscv cpu config we left out
 2021-11-03 13:20:46 +01:00
lazymio
bcf85be86d
Add a new hook type UC_HOOK_TCG_OPCODE 2021-11-03 01:46:24 +01:00
Bet4
aaf340d9e4 Merge branch 'dev' into patch 2021-11-02 18:36:22 +08:00
lazymio
6c3960242b
Format unicorn_arm and unicorn_aarch64 2021-11-01 10:17:58 +01:00
lazymio
3dd2e0f95d
Basic implementation of uc_ctl 2021-11-01 00:39:36 +01:00
lazymio
e62b0ef255
Add clang-format and format code to qemu code style 2021-10-29 12:44:49 +02:00
lazymio
e695686c15
Remove AFL Integration by reverting 2021-10-26 11:22:21 +02:00
lazymio
7ac7c23c12
Fix Windows build for AFL integration 2021-10-25 16:11:58 +02:00
lazymio
1fa2eb688b
Fix UC_MODE_AFL and update config 2021-10-25 14:39:40 +02:00
lazymio
dd7476a9bd
Initial import unicornafl 2021-10-25 00:51:16 +02:00
mio
567bd08b86
Update riscv pc and fix #1465 2021-10-19 23:22:13 +02:00
Bet4
c400924fe1
Merge branch 'dev' into patch 2021-10-17 18:18:09 +08:00
mio
6d0d0897f8
Fix Rust build and CI. 
Add a test for ppc and fix ppc on windows.
 2021-10-17 02:11:38 +02:00
Sven Almgren
f27c6fa655 X86 instruction FTST was incorrectly overwriting ST0 instead of FT0 (#1372) 
* X86 instruction FTST was incorrectly overwriting ST0 instead of FT0

* credits update
 2021-10-12 08:41:57 +08:00
Bet4
5f40667d91 Support querying architecture mode besides arm (#1389) 2021-10-11 11:39:23 +08:00
mio
ae1b6ad89b
Support building on Android arm aarch64 x86 x86_64 
1. Add cmake support in CMakeLists.txt according to https://developer.android.com/ndk/guides/other_build_systems

2. Resolve symbols errors

3. Backport fixes from 438ed42311

   > QEMU relies on two optimization for ppc64 and arm:
   >
   > 1. if(0) /* optimized code */
   > 2. assert(0); /* optimized code */
   >
   > But the assert on mingw32 doesn't have noreturn attribute which prevents
   > the second optimization and some code is reverted to the original code
   > to fit in the first optimization.
   >
   > The assert implementation is copied from glib as qemu did.

   Unfortunately, NDK also doesn't have an assert implementation qemu prefers.
 2021-10-06 04:42:44 +08:00
mio
9d8a309fbf
Allow user to instrument cpuid instruction 2021-10-05 17:15:49 +02:00
mio
bccc7f2fb7
Remove NULL tcg arg and add a test for sysenter 2021-10-04 18:50:42 +02:00
mio
2d043d387d
Change mips model to add DSP 2021-10-03 23:10:39 +02:00
Nguyen Anh Quynh
aaaea14214 import Unicorn2 2021-10-03 22:14:44 +08:00