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Author SHA1 Message Date
Nguyen Anh Quynh
5005b4a6e2 arm: early check to see if the address of this block is the until address 2015-09-17 09:16:57 +07:00
Nguyen Anh Quynh
d6b9c31dc9 sparc: more cleanup 2015-09-16 16:04:12 +07:00
Nguyen Anh Quynh
f36bd83f85 cleanup regress/sparc*.py 2015-09-16 15:46:10 +07:00
mothran
893e6abcbd first atttempt at SPARC64 fixes, no longer SEGV's, set CPU model to: Sun UltraSparc IV 2015-09-15 23:12:03 -07:00
Nguyen Anh Quynh
fe807952d0 bindings: update Sparc registers after the last core change 2015-09-15 14:17:57 +07:00
Nguyen Anh Quynh
e581b8ea0e Merge branch 'master' of https://github.com/unicorn-engine/unicorn 2015-09-15 14:17:10 +07:00
Nguyen Anh Quynh
7eaedc5c15 add a comment for Arm instruction in regress/arm_movr12_hang.py 2015-09-15 14:16:57 +07:00
Nguyen Anh Quynh
163e49bf59 Merge pull request #141 from mothran/sparc_regs 
Updated sparc register system
 2015-09-15 14:14:46 +07:00
mothran
6962126707 update sparc_reg.py with %i registers 2015-09-14 23:28:09 -07:00
mothran
d1e19df64e update the sparc_reg to test all g/o/l registers 2015-09-14 23:05:33 -07:00
mothran
69d73aa845 added emulated SPARC code for regress/sparc_reg.py, appears to be a bug in G and I registers 2015-09-14 21:23:42 -07:00
mothran
1638372793 fix small whitespace issue 2015-09-14 20:48:31 -07:00
mothran
f4894a1c77 removed unneed cases in the switch statement 2015-09-14 20:44:50 -07:00
mothran
d4d5631181 updated the sparc.h header so the alignment of certain registers was correct 2015-09-14 20:42:41 -07:00
mothran
6b521e9e9b update the sparc reg read/write to include o/l/i registers 2015-09-14 20:03:32 -07:00
mothran
85b3594c7c Merge branch 'master' of github.com:unicorn-engine/unicorn into sparc_regs 2015-09-14 19:57:23 -07:00
cherepanov74
2fc483ec47 Fixes crash on Windows 64bit 2015-09-14 20:42:29 +02:00
Nguyen Anh Quynh
3f726d1c57 chmod +x regress/sparc64.py 2015-09-14 09:46:05 +07:00
mothran
7dc41a8e4e update the regwptr upon reset 2015-09-13 18:10:28 -07:00
Nguyen Anh Quynh
507fc4dab7 Merge pull request #137 from mothran/sparc64_crash 
added the sparc64 crash regression
 2015-09-13 09:34:20 +08:00
mothran
2789e7951b added the sparc64 crash regression 2015-09-12 10:35:50 -07:00
mothran
657a6c3e25 modified the sparc reg get/set functions to use the current reg window ptr 2015-09-12 10:29:35 -07:00
Nguyen Anh Quynh
ab337ef65a Merge branch 'master' of https://github.com/unicorn-engine/unicorn 2015-09-11 15:58:58 +08:00
mothran
afecfee565 added SPARC sp / fp registers, also updated uint32_t's to uint64_t's in SPARC64 2015-09-10 23:20:52 -07:00
Nguyen Anh Quynh
548355acca sparc: do not accept BIGENDIAN mode in samples. more sanity check should be done in the core 2015-09-11 14:02:27 +08:00
Nguyen Anh Quynh
b306fa65bd Merge pull request #135 from lunixbochs/test-133 
add test for #133
 2015-09-10 01:17:15 +08:00
Ryan Hileman
586d5ca9f8 add test for #133 2015-09-09 08:27:13 -07:00
Nguyen Anh Quynh
113245e12a fix some comments in unicorn.h 2015-09-09 17:00:00 +08:00
Nguyen Anh Quynh
39ac1bcb4e rename UC_ERR_INVAL to UC_ERR_ARG 2015-09-09 16:54:47 +08:00
Nguyen Anh Quynh
d7ef204398 rename error codes ERR_MEM_READ, ERR_MEM_WRITE, ERR_MEM_FETCH 2015-09-09 16:25:48 +08:00
Nguyen Anh Quynh
d3d38d3f21 handle read/write/fetch from unaligned addresses. this adds new error codes UC_ERR_READ_UNALIGNED, UC_ERR_WRITE_UNALIGNED & UC_ERR_FETCH_UNALIGNED 2015-09-09 15:52:15 +08:00
Nguyen Anh Quynh
6b52be24a3 fix regress/mips_except.py 2015-09-09 15:32:31 +08:00
Nguyen Anh Quynh
18b6680e96 mips: disable debug output 2015-09-08 23:56:25 +08:00
Nguyen Anh Quynh
ae703e0efd Merge branch 'master' of https://github.com/unicorn-engine/unicorn 2015-09-08 22:52:23 +08:00
Nguyen Anh Quynh
99379e92e9 Merge pull request #131 from lunixbochs/mips-exception 
add regress for #130
 2015-09-08 15:47:53 +08:00
Ryan Hileman
d134c62366 add regress for #130 2015-09-08 00:44:14 -07:00
Nguyen Anh Quynh
09c66f2183 Merge pull request #129 from lunixbochs/master 
refactor Go bindings to be more idiomatic
 2015-09-08 15:32:13 +08:00
Ryan Hileman
9a0d80b84c refactor Go bindings to be more idiomatic 2015-09-08 00:04:27 -07:00
Nguyen Anh Quynh
2929138c99 sparc: do not call INSN handler on until-address, and verify until-address early when translating block in JIT frontend. 2015-09-08 13:26:53 +08:00
Nguyen Anh Quynh
fda17cd377 java: rename UC_MEM_EXE to UC_MEM_FETCH 2015-09-08 12:57:40 +08:00
Nguyen Anh Quynh
7a5d790ade rename UC_MEM_EXE to UC_MEM_FETCH 2015-09-08 12:55:56 +08:00
Nguyen Anh Quynh
d9f4e3f56b Merge pull request #128 from lunixbochs/no-go-uc 
go binding updates
 2015-09-08 11:14:29 +08:00
Ryan Hileman
7beb90ca95 remove UC_ prefix for go binding consts 2015-09-07 19:25:13 -07:00
Ryan Hileman
185b7a7cef fix Go types on uc_mem_read() and uc_mem_write() 2015-09-07 19:25:04 -07:00
Nguyen Anh Quynh
1724fabb05 add shebang for regress/sparc_reg.py 2015-09-08 09:14:22 +08:00
Nguyen Anh Quynh
74c2b05144 Merge pull request #127 from lunixbochs/test-126 
add regress for #126
 2015-09-08 09:10:43 +08:00
Ryan Hileman
5f6c475479 add regress for #126 2015-09-07 18:08:05 -07:00
Nguyen Anh Quynh
c1dd9fbfdf arm64: handle SP register. this fixes issue #122 2015-09-08 08:40:42 +08:00
Nguyen Anh Quynh
4e9af41345 Merge pull request #121 from cseagle/java_dev 
update java binding to follow api change of uc_mem_read and uc_mem_write
 2015-09-08 08:08:02 +08:00
Nguyen Anh Quynh
6085cd8046 Merge pull request #124 from lunixbochs/test-122 
add test for #122
 2015-09-08 08:07:18 +08:00