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Merge pull request #1554 from bet4it/const

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Update constants of bindings
This commit is contained in:
lazymio 2022-02-19 21:27:40 +01:00 committed by GitHub
commit fc4ca3b04f
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18 changed files with 309 additions and 150 deletions
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1
bindings/dotnet/UnicornManaged/Const/Ppc.fs
View File

@ -406,4 +406,5 @@ module Ppc =
let UC_PPC_REG_MSR = 77
let UC_PPC_REG_FPSCR = 78
let UC_PPC_REG_CR = 79
let UC_PPC_REG_ENDING = 80

1
bindings/go/unicorn/ppc_const.go
View File

@ -401,4 +401,5 @@ const (
PPC_REG_MSR = 77
PPC_REG_FPSCR = 78
PPC_REG_CR = 79
PPC_REG_ENDING = 80
)

1
bindings/java/unicorn/PpcConst.java
View File

@ -403,5 +403,6 @@ public interface PpcConst {
public static final int UC_PPC_REG_MSR = 77;
public static final int UC_PPC_REG_FPSCR = 78;
public static final int UC_PPC_REG_CR = 79;
public static final int UC_PPC_REG_ENDING = 80;
}

1
bindings/pascal/unicorn/PpcConst.pas
View File

@ -404,6 +404,7 @@ const
UC_PPC_REG_MSR = 77;
UC_PPC_REG_FPSCR = 78;
UC_PPC_REG_CR = 79;
UC_PPC_REG_ENDING = 80;
implementation
end.

1
bindings/python/unicorn/ppc_const.py
View File

@ -399,3 +399,4 @@ UC_PPC_REG_CTR = 76
UC_PPC_REG_MSR = 77
UC_PPC_REG_FPSCR = 78
UC_PPC_REG_CR = 79
UC_PPC_REG_ENDING = 80

1
bindings/ruby/unicorn_gem/lib/unicorn_engine/ppc_const.rb
View File

@ -401,4 +401,5 @@ module UnicornEngine
UC_PPC_REG_MSR = 77
UC_PPC_REG_FPSCR = 78
UC_PPC_REG_CR = 79
UC_PPC_REG_ENDING = 80
end

3
bindings/rust/src/arm.rs
View File

@ -144,7 +144,8 @@ pub enum RegisterARM {
XPSR_NZCVQ = 136,
XPSR_G = 137,
XPSR_NZCVQG = 138,
ENDING = 139,
CP_REG = 139,
ENDING = 140,
}
impl RegisterARM {

11
bindings/rust/src/arm64.rs
View File

@ -268,25 +268,25 @@ pub enum RegisterARM64 {
PC = 260,
CPACR_EL1 = 261,
// thread registers
// thread registers, depreciated, use CP_REG instead
TPIDR_EL0 = 262,
TPIDRRO_EL0 = 263,
TPIDR_EL1 = 264,
PSTATE = 265,
// exception link registers
// exception link registers, depreciated, use CP_REG instead
ELR_EL0 = 266,
ELR_EL1 = 267,
ELR_EL2 = 268,
ELR_EL3 = 269,
// stack pointers registers
// stack pointers registers, depreciated, use CP_REG instead
SP_EL0 = 270,
SP_EL1 = 271,
SP_EL2 = 272,
SP_EL3 = 273,
// other CP15 registers
// other CP15 registers, depreciated, use CP_REG instead
TTBR0_EL1 = 274,
TTBR1_EL1 = 275,
ESR_EL0 = 276,
@ -303,7 +303,8 @@ pub enum RegisterARM64 {
VBAR_EL1 = 287,
VBAR_EL2 = 288,
VBAR_EL3 = 289,
ENDING = 290,
CP_REG = 290,
ENDING = 291,
// alias registers
// (assoc) IP0 = 215,
// (assoc) IP1 = 216,

21
bindings/rust/src/lib.rs
View File

@ -40,11 +40,13 @@ mod m68k;
mod mips;
mod ppc;
mod riscv;
mod s390x;
mod sparc;
mod x86;
pub use crate::{
arm::*, arm64::*, m68k::*, mips::*, ppc::*, riscv::*, sparc::*, unicorn_const::*, x86::*,
arm::*, arm64::*, m68k::*, mips::*, ppc::*, riscv::*, s390x::*, sparc::*, unicorn_const::*,
x86::*,
};
use alloc::{boxed::Box, rc::Rc, vec::Vec};
@ -164,7 +166,7 @@ impl<'a> TryFrom<uc_handle> for Unicorn<'a, ()> {
type Error = uc_error;
fn try_from(handle: uc_handle) -> Result<Unicorn<'a, ()>, uc_error> {
if handle == ptr::null_mut() {
if handle.is_null() {
return Err(uc_error::HANDLE);
}
let mut arch: libc::size_t = Default::default();
@ -514,7 +516,8 @@ impl<'a, D> Unicorn<'a, D> {
/// The user has to make sure that the buffer length matches the register size.
/// This adds support for registers >64 bit (GDTR/IDTR, XMM, YMM, ZMM (x86); Q, V (arm64)).
pub fn reg_write_long<T: Into<i32>>(&self, regid: T, value: &[u8]) -> Result<(), uc_error> {
let err = unsafe { ffi::uc_reg_write(self.get_handle(), regid.into(), value.as_ptr() as _) };
let err =
unsafe { ffi::uc_reg_write(self.get_handle(), regid.into(), value.as_ptr() as _) };
if err == uc_error::OK {
Ok(())
} else {
@ -527,8 +530,9 @@ impl<'a, D> Unicorn<'a, D> {
/// Not to be used with registers larger than 64 bit.
pub fn reg_read<T: Into<i32>>(&self, regid: T) -> Result<u64, uc_error> {
let mut value: u64 = 0;
let err =
unsafe { ffi::uc_reg_read(self.get_handle(), regid.into(), &mut value as *mut u64 as _) };
let err = unsafe {
ffi::uc_reg_read(self.get_handle(), regid.into(), &mut value as *mut u64 as _)
};
if err == uc_error::OK {
Ok(value)
} else {
@ -595,8 +599,9 @@ impl<'a, D> Unicorn<'a, D> {
/// Read a signed 32-bit value from a register.
pub fn reg_read_i32<T: Into<i32>>(&self, regid: T) -> Result<i32, uc_error> {
let mut value: i32 = 0;
let err =
unsafe { ffi::uc_reg_read(self.get_handle(), regid.into(), &mut value as *mut i32 as _) };
let err = unsafe {
ffi::uc_reg_read(self.get_handle(), regid.into(), &mut value as *mut i32 as _)
};
if err == uc_error::OK {
Ok(value)
} else {
@ -1002,6 +1007,7 @@ impl<'a, D> Unicorn<'a, D> {
Arch::M68K => RegisterM68K::PC as i32,
Arch::PPC => RegisterPPC::PC as i32,
Arch::RISCV => RegisterRISCV::PC as i32,
Arch::S390X => RegisterS390X::PC as i32,
Arch::MAX => panic!("Illegal Arch specified"),
};
self.reg_read(reg)
@ -1020,6 +1026,7 @@ impl<'a, D> Unicorn<'a, D> {
Arch::M68K => RegisterM68K::PC as i32,
Arch::PPC => RegisterPPC::PC as i32,
Arch::RISCV => RegisterRISCV::PC as i32,
Arch::S390X => RegisterS390X::PC as i32,
Arch::MAX => panic!("Illegal Arch specified"),
};
self.reg_write(reg, value)

1
bindings/rust/src/m68k.rs
View File

@ -21,6 +21,7 @@ pub enum RegisterM68K {
D7,
SR,
PC,
ENDING,
}
impl From<RegisterM68K> for i32 {

130
bindings/rust/src/mips.rs
View File

@ -9,38 +9,38 @@ pub enum RegisterMIPS {
// General purpose registers
PC = 1,
GPR0 = 2,
GPR1 = 3,
GPR2 = 4,
GPR3 = 5,
GPR4 = 6,
GPR5 = 7,
GPR6 = 8,
GPR7 = 9,
GPR8 = 10,
GPR9 = 11,
GPR10 = 12,
GPR11 = 13,
GPR12 = 14,
GPR13 = 15,
GPR14 = 16,
GPR15 = 17,
GPR16 = 18,
GPR17 = 19,
GPR18 = 20,
GPR19 = 21,
GPR20 = 22,
GPR21 = 23,
GPR22 = 24,
GPR23 = 25,
GPR24 = 26,
GPR25 = 27,
GPR26 = 28,
GPR27 = 29,
GPR28 = 30,
GPR29 = 31,
GPR30 = 32,
GPR31 = 33,
R0 = 2,
R1 = 3,
R2 = 4,
R3 = 5,
R4 = 6,
R5 = 7,
R6 = 8,
R7 = 9,
R8 = 10,
R9 = 11,
R10 = 12,
R11 = 13,
R12 = 14,
R13 = 15,
R14 = 16,
R15 = 17,
R16 = 18,
R17 = 19,
R18 = 20,
R19 = 21,
R20 = 22,
R21 = 23,
R22 = 24,
R23 = 25,
R24 = 26,
R25 = 27,
R26 = 28,
R27 = 29,
R28 = 30,
R29 = 31,
R30 = 32,
R31 = 33,
// DSP registers
DSPCCOND = 34,
@ -203,39 +203,39 @@ impl RegisterMIPS {
// (assoc) LO1 = 46,
// (assoc) LO2 = 47,
// (assoc) LO3 = 48,
pub const ZERO: RegisterMIPS = RegisterMIPS::GPR0;
pub const AT: RegisterMIPS = RegisterMIPS::GPR1;
pub const V0: RegisterMIPS = RegisterMIPS::GPR2;
pub const V1: RegisterMIPS = RegisterMIPS::GPR3;
pub const A0: RegisterMIPS = RegisterMIPS::GPR4;
pub const A1: RegisterMIPS = RegisterMIPS::GPR5;
pub const A2: RegisterMIPS = RegisterMIPS::GPR6;
pub const A3: RegisterMIPS = RegisterMIPS::GPR7;
pub const T0: RegisterMIPS = RegisterMIPS::GPR8;
pub const T1: RegisterMIPS = RegisterMIPS::GPR9;
pub const T2: RegisterMIPS = RegisterMIPS::GPR10;
pub const T3: RegisterMIPS = RegisterMIPS::GPR11;
pub const T4: RegisterMIPS = RegisterMIPS::GPR12;
pub const T5: RegisterMIPS = RegisterMIPS::GPR13;
pub const T6: RegisterMIPS = RegisterMIPS::GPR14;
pub const T7: RegisterMIPS = RegisterMIPS::GPR15;
pub const S0: RegisterMIPS = RegisterMIPS::GPR16;
pub const S1: RegisterMIPS = RegisterMIPS::GPR17;
pub const S2: RegisterMIPS = RegisterMIPS::GPR18;
pub const S3: RegisterMIPS = RegisterMIPS::GPR19;
pub const S4: RegisterMIPS = RegisterMIPS::GPR20;
pub const S5: RegisterMIPS = RegisterMIPS::GPR21;
pub const S6: RegisterMIPS = RegisterMIPS::GPR22;
pub const S7: RegisterMIPS = RegisterMIPS::GPR23;
pub const T8: RegisterMIPS = RegisterMIPS::GPR24;
pub const T9: RegisterMIPS = RegisterMIPS::GPR25;
pub const K0: RegisterMIPS = RegisterMIPS::GPR26;
pub const K1: RegisterMIPS = RegisterMIPS::GPR27;
pub const GP: RegisterMIPS = RegisterMIPS::GPR28;
pub const SP: RegisterMIPS = RegisterMIPS::GPR29;
pub const FP: RegisterMIPS = RegisterMIPS::GPR30;
pub const S8: RegisterMIPS = RegisterMIPS::GPR30;
pub const RA: RegisterMIPS = RegisterMIPS::GPR31;
pub const ZERO: RegisterMIPS = RegisterMIPS::R0;
pub const AT: RegisterMIPS = RegisterMIPS::R1;
pub const V0: RegisterMIPS = RegisterMIPS::R2;
pub const V1: RegisterMIPS = RegisterMIPS::R3;
pub const A0: RegisterMIPS = RegisterMIPS::R4;
pub const A1: RegisterMIPS = RegisterMIPS::R5;
pub const A2: RegisterMIPS = RegisterMIPS::R6;
pub const A3: RegisterMIPS = RegisterMIPS::R7;
pub const T0: RegisterMIPS = RegisterMIPS::R8;
pub const T1: RegisterMIPS = RegisterMIPS::R9;
pub const T2: RegisterMIPS = RegisterMIPS::R10;
pub const T3: RegisterMIPS = RegisterMIPS::R11;
pub const T4: RegisterMIPS = RegisterMIPS::R12;
pub const T5: RegisterMIPS = RegisterMIPS::R13;
pub const T6: RegisterMIPS = RegisterMIPS::R14;
pub const T7: RegisterMIPS = RegisterMIPS::R15;
pub const S0: RegisterMIPS = RegisterMIPS::R16;
pub const S1: RegisterMIPS = RegisterMIPS::R17;
pub const S2: RegisterMIPS = RegisterMIPS::R18;
pub const S3: RegisterMIPS = RegisterMIPS::R19;
pub const S4: RegisterMIPS = RegisterMIPS::R20;
pub const S5: RegisterMIPS = RegisterMIPS::R21;
pub const S6: RegisterMIPS = RegisterMIPS::R22;
pub const S7: RegisterMIPS = RegisterMIPS::R23;
pub const T8: RegisterMIPS = RegisterMIPS::R24;
pub const T9: RegisterMIPS = RegisterMIPS::R25;
pub const K0: RegisterMIPS = RegisterMIPS::R26;
pub const K1: RegisterMIPS = RegisterMIPS::R27;
pub const GP: RegisterMIPS = RegisterMIPS::R28;
pub const SP: RegisterMIPS = RegisterMIPS::R29;
pub const FP: RegisterMIPS = RegisterMIPS::R30;
pub const S8: RegisterMIPS = RegisterMIPS::R30;
pub const RA: RegisterMIPS = RegisterMIPS::R31;
pub const HI0: RegisterMIPS = RegisterMIPS::AC0;
pub const HI1: RegisterMIPS = RegisterMIPS::AC1;
pub const HI2: RegisterMIPS = RegisterMIPS::AC2;

111
bindings/rust/src/ppc.rs
View File

@ -7,38 +7,85 @@
pub enum RegisterPPC {
INVALID = 0,
PC = 1,
GPR0 = 2,
GPR1 = 3,
GPR2 = 4,
GPR3 = 5,
GPR4 = 6,
GPR5 = 7,
GPR6 = 8,
GPR7 = 9,
GPR8 = 10,
GPR9 = 11,
GPR10 = 12,
GPR11 = 13,
GPR12 = 14,
GPR13 = 15,
GPR14 = 16,
GPR15 = 17,
GPR16 = 18,
GPR17 = 19,
GPR18 = 20,
GPR19 = 21,
GPR20 = 22,
GPR21 = 23,
GPR22 = 24,
GPR23 = 25,
GPR24 = 26,
GPR25 = 27,
GPR26 = 28,
GPR27 = 29,
GPR28 = 30,
GPR29 = 31,
GPR30 = 32,
GPR31 = 33,
R0 = 2,
R1 = 3,
R2 = 4,
R3 = 5,
R4 = 6,
R5 = 7,
R6 = 8,
R7 = 9,
R8 = 10,
R9 = 11,
R10 = 12,
R11 = 13,
R12 = 14,
R13 = 15,
R14 = 16,
R15 = 17,
R16 = 18,
R17 = 19,
R18 = 20,
R19 = 21,
R20 = 22,
R21 = 23,
R22 = 24,
R23 = 25,
R24 = 26,
R25 = 27,
R26 = 28,
R27 = 29,
R28 = 30,
R29 = 31,
R30 = 32,
R31 = 33,
CR0 = 34,
CR1 = 35,
CR2 = 36,
CR3 = 37,
CR4 = 38,
CR5 = 39,
CR6 = 40,
CR7 = 41,
FPR0 = 42,
FPR1 = 43,
FPR2 = 44,
FPR3 = 45,
FPR4 = 46,
FPR5 = 47,
FPR6 = 48,
FPR7 = 49,
FPR8 = 50,
FPR9 = 51,
FPR10 = 52,
FPR11 = 53,
FPR12 = 54,
FPR13 = 55,
FPR14 = 56,
FPR15 = 57,
FPR16 = 58,
FPR17 = 59,
FPR18 = 60,
FPR19 = 61,
FPR20 = 62,
FPR21 = 63,
FPR22 = 64,
FPR23 = 65,
FPR24 = 66,
FPR25 = 67,
FPR26 = 68,
FPR27 = 69,
FPR28 = 70,
FPR29 = 71,
FPR30 = 72,
FPR31 = 73,
LR = 74,
XER = 75,
CTR = 76,
MSR = 77,
FPSCR = 78,
CR = 79,
ENDING = 80,
}
impl From<RegisterPPC> for i32 {

64
bindings/rust/src/riscv.rs
View File

@ -240,38 +240,38 @@ impl RegisterRISCV {
// (assoc) T4 = 30,
// (assoc) T5 = 31,
// (assoc) T6 = 32,
// (assoc) FT0 = 33,
// (assoc) FT1 = 34,
// (assoc) FT2 = 35,
// (assoc) FT3 = 36,
// (assoc) FT4 = 37,
// (assoc) FT5 = 38,
// (assoc) FT6 = 39,
// (assoc) FT7 = 40,
// (assoc) FS0 = 41,
// (assoc) FS1 = 42,
// (assoc) FA0 = 43,
// (assoc) FA1 = 44,
// (assoc) FA2 = 45,
// (assoc) FA3 = 46,
// (assoc) FA4 = 47,
// (assoc) FA5 = 48,
// (assoc) FA6 = 49,
// (assoc) FA7 = 50,
// (assoc) FS2 = 51,
// (assoc) FS3 = 52,
// (assoc) FS4 = 53,
// (assoc) FS5 = 54,
// (assoc) FS6 = 55,
// (assoc) FS7 = 56,
// (assoc) FS8 = 57,
// (assoc) FS9 = 58,
// (assoc) FS10 = 59,
// (assoc) FS11 = 60,
// (assoc) FT8 = 61,
// (assoc) FT9 = 62,
// (assoc) FT10 = 63,
// (assoc) FT11 = 64,
// (assoc) FT0 = 158,
// (assoc) FT1 = 159,
// (assoc) FT2 = 160,
// (assoc) FT3 = 161,
// (assoc) FT4 = 162,
// (assoc) FT5 = 163,
// (assoc) FT6 = 164,
// (assoc) FT7 = 165,
// (assoc) FS0 = 166,
// (assoc) FS1 = 167,
// (assoc) FA0 = 168,
// (assoc) FA1 = 169,
// (assoc) FA2 = 170,
// (assoc) FA3 = 171,
// (assoc) FA4 = 172,
// (assoc) FA5 = 173,
// (assoc) FA6 = 174,
// (assoc) FA7 = 175,
// (assoc) FS2 = 176,
// (assoc) FS3 = 177,
// (assoc) FS4 = 178,
// (assoc) FS5 = 179,
// (assoc) FS6 = 180,
// (assoc) FS7 = 181,
// (assoc) FS8 = 182,
// (assoc) FS9 = 183,
// (assoc) FS10 = 184,
// (assoc) FS11 = 185,
// (assoc) FT8 = 186,
// (assoc) FT9 = 187,
// (assoc) FT10 = 188,
// (assoc) FT11 = 189,
pub const ZERO: RegisterRISCV = RegisterRISCV::X0;
pub const RA: RegisterRISCV = RegisterRISCV::X1;
pub const SP: RegisterRISCV = RegisterRISCV::X2;

86
bindings/rust/src/s390x.rs Normal file
View File

@ -0,0 +1,86 @@
// S390X registers
#[repr(C)]
#[derive(PartialEq, Debug, Clone, Copy)]
#[allow(non_camel_case_types)]
pub enum RegisterS390X {
INVALID = 0,
// General purpose registers
R0 = 1,
R1 = 2,
R2 = 3,
R3 = 4,
R4 = 5,
R5 = 6,
R6 = 7,
R7 = 8,
R8 = 9,
R9 = 10,
R10 = 11,
R11 = 12,
R12 = 13,
R13 = 14,
R14 = 15,
R15 = 16,
// Floating point registers
F0 = 17,
F1 = 18,
F2 = 19,
F3 = 20,
F4 = 21,
F5 = 22,
F6 = 23,
F7 = 24,
F8 = 25,
F9 = 26,
F10 = 27,
F11 = 28,
F12 = 29,
F13 = 30,
F14 = 31,
F15 = 32,
F16 = 33,
F17 = 34,
F18 = 35,
F19 = 36,
F20 = 37,
F21 = 38,
F22 = 39,
F23 = 40,
F24 = 41,
F25 = 42,
F26 = 43,
F27 = 44,
F28 = 45,
F29 = 46,
F30 = 47,
F31 = 48,
// Access registers
A0 = 49,
A1 = 50,
A2 = 51,
A3 = 52,
A4 = 53,
A5 = 54,
A6 = 55,
A7 = 56,
A8 = 57,
A9 = 58,
A10 = 59,
A11 = 60,
A12 = 61,
A13 = 62,
A14 = 63,
A15 = 64,
PC = 65,
PSWM = 66,
ENDING = 67,
}
impl From<RegisterS390X> for i32 {
fn from(r: RegisterS390X) -> Self {
r as i32
}
}

9
bindings/rust/src/unicorn_const.rs
View File

@ -5,7 +5,7 @@ pub const API_MAJOR: u64 = 2;
pub const API_MINOR: u64 = 0;
pub const VERSION_MAJOR: u64 = 2;
pub const VERSION_MINOR: u64 = 0;
pub const VERSION_EXTRA: u64 = 0;
pub const VERSION_EXTRA: u64 = 6;
pub const SECOND_SCALE: u64 = 1_000_000;
pub const MILISECOND_SCALE: u64 = 1_000;
@ -128,7 +128,8 @@ pub enum Arch {
SPARC = 6,
M68K = 7,
RISCV = 8,
MAX = 9,
S390X = 9,
MAX = 10,
}
impl TryFrom<usize> for Arch {
@ -144,6 +145,7 @@ impl TryFrom<usize> for Arch {
x if x == Self::SPARC as usize => Ok(Self::SPARC),
x if x == Self::M68K as usize => Ok(Self::M68K),
x if x == Self::RISCV as usize => Ok(Self::RISCV),
x if x == Self::S390X as usize => Ok(Self::S390X),
x if x == Self::MAX as usize => Ok(Self::MAX),
_ => Err(uc_error::ARCH),
}
@ -160,7 +162,8 @@ bitflags! {
const THUMB = 0x10;
const MCLASS = 0x20;
const V8 = 0x40;
const ARM926 = 0x80;
const ARMBE8 = 0x80;
const ARM926 = Self::ARMBE8.bits;
const ARM946 = 0x100;
const ARM1176 = 0x200;
const MICRO = Self::THUMB.bits;

7
bindings/rust/src/x86.rs
View File

@ -237,7 +237,12 @@ pub enum RegisterX86 {
GS_BASE = 231,
FLAGS = 232,
RFLAGS = 233,
ENDING = 234,
FIP = 234,
FCS = 235,
FDP = 236,
FDS = 237,
FOP = 238,
ENDING = 239,
}
impl From<RegisterX86> for i32 {

6
bindings/rust/tests/unicorn.rs
View File

@ -607,8 +607,8 @@ fn emulate_ppc() {
emu.mem_read_as_vec(0x1000, ppc_code32.len()),
Ok(ppc_code32.clone())
);
assert_eq!(emu.reg_write(RegisterPPC::GPR3, 42), Ok(()));
assert_eq!(emu.reg_write(RegisterPPC::GPR6, 1337), Ok(()));
assert_eq!(emu.reg_write(RegisterPPC::R3, 42), Ok(()));
assert_eq!(emu.reg_write(RegisterPPC::R6, 1337), Ok(()));
assert_eq!(
emu.emu_start(
0x1000,
@ -618,7 +618,7 @@ fn emulate_ppc() {
),
Ok(())
);
assert_eq!(emu.reg_read(RegisterPPC::GPR26), Ok(1379));
assert_eq!(emu.reg_read(RegisterPPC::R26), Ok(1379));
}
#[test]

4
include/unicorn/ppc.h
View File

@ -418,7 +418,9 @@ typedef enum uc_ppc_reg {
UC_PPC_REG_CTR,
UC_PPC_REG_MSR,
UC_PPC_REG_FPSCR,
UC_PPC_REG_CR
UC_PPC_REG_CR,
UC_PPC_REG_ENDING, // <-- mark the end of the list or registers
} uc_ppc_reg;
#ifdef __cplusplus