From afecfee565db653588a5627e83710f8a20531b72 Mon Sep 17 00:00:00 2001 From: mothran Date: Thu, 10 Sep 2015 23:20:52 -0700 Subject: [PATCH 01/10] added SPARC sp / fp registers, also updated uint32_t's to uint64_t's in SPARC64 --- qemu/target-sparc/unicorn.c | 23 +++++++++++++++++------ qemu/target-sparc/unicorn64.c | 26 +++++++++++++++++++------- 2 files changed, 36 insertions(+), 13 deletions(-) diff --git a/qemu/target-sparc/unicorn.c b/qemu/target-sparc/unicorn.c index 9f00f340..19e3ab0e 100644 --- a/qemu/target-sparc/unicorn.c +++ b/qemu/target-sparc/unicorn.c @@ -54,8 +54,14 @@ int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) switch(regid) { default: break; case UC_SPARC_REG_PC: - *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc; - break; + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc; + break; + case UC_SPARC_REG_SP: + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regbase[6]; + break; + case UC_SPARC_REG_FP: + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regbase[22]; + break; } } @@ -78,13 +84,18 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) switch(regid) { default: break; case UC_SPARC_REG_PC: - SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value; - SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4; - break; + SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value; + SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4; + break; + case UC_SPARC_REG_SP: + SPARC_CPU(uc, mycpu)->env.regbase[6] = *(uint32_t *)value; + break; + case UC_SPARC_REG_FP: + SPARC_CPU(uc, mycpu)->env.regbase[22] = *(uint32_t *)value; + break; } } - return 0; } diff --git a/qemu/target-sparc/unicorn64.c b/qemu/target-sparc/unicorn64.c index aefef116..eb88c095 100644 --- a/qemu/target-sparc/unicorn64.c +++ b/qemu/target-sparc/unicorn64.c @@ -32,13 +32,19 @@ int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) CPUState *mycpu = first_cpu; if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) - *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0]; + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0]; else { switch(regid) { default: break; case UC_SPARC_REG_PC: - *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc; - break; + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.pc; + break; + case UC_SPARC_REG_SP: + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regbase[6]; + break; + case UC_SPARC_REG_FP: + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regbase[22]; + break; } } @@ -56,14 +62,20 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) CPUState *mycpu = first_cpu; if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) - SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(uint32_t *)value; + SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(uint64_t *)value; else { switch(regid) { default: break; case UC_SPARC_REG_PC: - SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value; - SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4; - break; + SPARC_CPU(uc, mycpu)->env.pc = *(uint64_t *)value; + SPARC_CPU(uc, mycpu)->env.npc = *(uint64_t *)value + 8; + break; + case UC_SPARC_REG_SP: + SPARC_CPU(uc, mycpu)->env.regbase[6] = *(uint64_t *)value; + break; + case UC_SPARC_REG_FP: + SPARC_CPU(uc, mycpu)->env.regbase[22] = *(uint64_t *)value; + break; } } From 657a6c3e256545297849aa56bbb9daf46375f9d8 Mon Sep 17 00:00:00 2001 From: mothran Date: Sat, 12 Sep 2015 10:29:35 -0700 Subject: [PATCH 02/10] modified the sparc reg get/set functions to use the current reg window ptr --- qemu/target-sparc/unicorn.c | 8 ++++---- qemu/target-sparc/unicorn64.c | 8 ++++---- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/qemu/target-sparc/unicorn.c b/qemu/target-sparc/unicorn.c index 19e3ab0e..f070d07d 100644 --- a/qemu/target-sparc/unicorn.c +++ b/qemu/target-sparc/unicorn.c @@ -57,10 +57,10 @@ int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc; break; case UC_SPARC_REG_SP: - *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regbase[6]; + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[6]; break; case UC_SPARC_REG_FP: - *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regbase[22]; + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[22]; break; } } @@ -88,10 +88,10 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4; break; case UC_SPARC_REG_SP: - SPARC_CPU(uc, mycpu)->env.regbase[6] = *(uint32_t *)value; + SPARC_CPU(uc, mycpu)->env.regwptr[6] = *(uint32_t *)value; break; case UC_SPARC_REG_FP: - SPARC_CPU(uc, mycpu)->env.regbase[22] = *(uint32_t *)value; + SPARC_CPU(uc, mycpu)->env.regwptr[22] = *(uint32_t *)value; break; } } diff --git a/qemu/target-sparc/unicorn64.c b/qemu/target-sparc/unicorn64.c index eb88c095..5def992e 100644 --- a/qemu/target-sparc/unicorn64.c +++ b/qemu/target-sparc/unicorn64.c @@ -40,10 +40,10 @@ int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.pc; break; case UC_SPARC_REG_SP: - *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regbase[6]; + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[6]; break; case UC_SPARC_REG_FP: - *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regbase[22]; + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[22]; break; } } @@ -71,10 +71,10 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) SPARC_CPU(uc, mycpu)->env.npc = *(uint64_t *)value + 8; break; case UC_SPARC_REG_SP: - SPARC_CPU(uc, mycpu)->env.regbase[6] = *(uint64_t *)value; + SPARC_CPU(uc, mycpu)->env.regwptr[6] = *(uint64_t *)value; break; case UC_SPARC_REG_FP: - SPARC_CPU(uc, mycpu)->env.regbase[22] = *(uint64_t *)value; + SPARC_CPU(uc, mycpu)->env.regwptr[22] = *(uint64_t *)value; break; } } From 7dc41a8e4e5113753bf430f48d51df4c5a95897f Mon Sep 17 00:00:00 2001 From: mothran Date: Sun, 13 Sep 2015 18:10:28 -0700 Subject: [PATCH 03/10] update the regwptr upon reset --- qemu/target-sparc/unicorn.c | 1 + qemu/target-sparc/unicorn64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/qemu/target-sparc/unicorn.c b/qemu/target-sparc/unicorn.c index f070d07d..02aadd7f 100644 --- a/qemu/target-sparc/unicorn.c +++ b/qemu/target-sparc/unicorn.c @@ -42,6 +42,7 @@ void sparc_reg_reset(struct uc_struct *uc) env->pc = 0; env->npc = 0; + env->regwptr = env->regbase; } int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) diff --git a/qemu/target-sparc/unicorn64.c b/qemu/target-sparc/unicorn64.c index 5def992e..6b62695f 100644 --- a/qemu/target-sparc/unicorn64.c +++ b/qemu/target-sparc/unicorn64.c @@ -25,6 +25,7 @@ void sparc_reg_reset(struct uc_struct *uc) env->pc = 0; env->npc = 0; + env->regwptr = env->regbase; } int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) From 6b521e9e9b43928cdb2ea45bed4f233c90211dd2 Mon Sep 17 00:00:00 2001 From: mothran Date: Mon, 14 Sep 2015 20:03:32 -0700 Subject: [PATCH 04/10] update the sparc reg read/write to include o/l/i registers --- qemu/target-sparc/unicorn.c | 12 ++++++++++++ qemu/target-sparc/unicorn64.c | 12 ++++++++++++ regress/sparc_reg.py | 19 +++++++++++++++++++ 3 files changed, 43 insertions(+) diff --git a/qemu/target-sparc/unicorn.c b/qemu/target-sparc/unicorn.c index 02aadd7f..93bdffdc 100644 --- a/qemu/target-sparc/unicorn.c +++ b/qemu/target-sparc/unicorn.c @@ -51,6 +51,12 @@ int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0]; + else if (regid >= UC_SPARC_REG_O0 && regid <= UC_SPARC_REG_O7) + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[regid - UC_SPARC_REG_O0]; + else if (regid >= UC_SPARC_REG_L0 && regid <= UC_SPARC_REG_L7) + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[8 + regid - UC_SPARC_REG_L0]; + else if (regid >= UC_SPARC_REG_I0 && regid <= UC_SPARC_REG_I7) + *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[16 + regid - UC_SPARC_REG_I0]; else { switch(regid) { default: break; @@ -81,6 +87,12 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(uint32_t *)value; + else if (regid >= UC_SPARC_REG_O0 && regid <= UC_SPARC_REG_O7) + SPARC_CPU(uc, mycpu)->env.regwptr[regid - UC_SPARC_REG_O0] = *(uint32_t *)value; + else if (regid >= UC_SPARC_REG_L0 && regid <= UC_SPARC_REG_L7) + SPARC_CPU(uc, mycpu)->env.regwptr[8 + regid - UC_SPARC_REG_L0] = *(uint32_t *)value; + else if (regid >= UC_SPARC_REG_I0 && regid <= UC_SPARC_REG_I7) + SPARC_CPU(uc, mycpu)->env.regwptr[16 + regid - UC_SPARC_REG_I0] = *(uint32_t *)value; else { switch(regid) { default: break; diff --git a/qemu/target-sparc/unicorn64.c b/qemu/target-sparc/unicorn64.c index 6b62695f..49428fa3 100644 --- a/qemu/target-sparc/unicorn64.c +++ b/qemu/target-sparc/unicorn64.c @@ -34,6 +34,12 @@ int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0]; + else if (regid >= UC_SPARC_REG_O0 && regid <= UC_SPARC_REG_O7) + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[regid - UC_SPARC_REG_O0]; + else if (regid >= UC_SPARC_REG_L0 && regid <= UC_SPARC_REG_L7) + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[8 + regid - UC_SPARC_REG_L0]; + else if (regid >= UC_SPARC_REG_I0 && regid <= UC_SPARC_REG_I7) + *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[16 + regid - UC_SPARC_REG_I0]; else { switch(regid) { default: break; @@ -64,6 +70,12 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7) SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(uint64_t *)value; + else if (regid >= UC_SPARC_REG_O0 && regid <= UC_SPARC_REG_O7) + SPARC_CPU(uc, mycpu)->env.regwptr[regid - UC_SPARC_REG_O0] = *(uint64_t *)value; + else if (regid >= UC_SPARC_REG_L0 && regid <= UC_SPARC_REG_L7) + SPARC_CPU(uc, mycpu)->env.regwptr[8 + regid - UC_SPARC_REG_L0] = *(uint64_t *)value; + else if (regid >= UC_SPARC_REG_I0 && regid <= UC_SPARC_REG_I7) + SPARC_CPU(uc, mycpu)->env.regwptr[16 + regid - UC_SPARC_REG_I0] = *(uint64_t *)value; else { switch(regid) { default: break; diff --git a/regress/sparc_reg.py b/regress/sparc_reg.py index 73858360..33bb03e0 100755 --- a/regress/sparc_reg.py +++ b/regress/sparc_reg.py @@ -6,6 +6,25 @@ from unicorn.sparc_const import * uc = Uc(UC_ARCH_SPARC, UC_MODE_32) uc.reg_write(UC_SPARC_REG_SP, 100) uc.reg_write(UC_SPARC_REG_FP, 100) +uc.reg_write(UC_SPARC_REG_G0, 200) +uc.reg_write(UC_SPARC_REG_O0, 201) +uc.reg_write(UC_SPARC_REG_L0, 202) +uc.reg_write(UC_SPARC_REG_L7, 203) +uc.reg_write(UC_SPARC_REG_I0, 204) + print 'writing sp = 100, fp = 100' print 'sp =', uc.reg_read(UC_SPARC_REG_SP) print 'fp =', uc.reg_read(UC_SPARC_REG_FP) +print 'g0 =', uc.reg_read(UC_SPARC_REG_G0) +print 'o0 =', uc.reg_read(UC_SPARC_REG_O0) +print 'l0 =', uc.reg_read(UC_SPARC_REG_L0) +print 'l7 =', uc.reg_read(UC_SPARC_REG_L7) +print 'i0 =', uc.reg_read(UC_SPARC_REG_I0) + +assert uc.reg_read(UC_SPARC_REG_SP) == 100 +assert uc.reg_read(UC_SPARC_REG_FP) == 100 +assert uc.reg_read(UC_SPARC_REG_G0) == 200 +assert uc.reg_read(UC_SPARC_REG_O0) == 201 +assert uc.reg_read(UC_SPARC_REG_L0) == 202 +assert uc.reg_read(UC_SPARC_REG_L7) == 203 +assert uc.reg_read(UC_SPARC_REG_I0) == 204 \ No newline at end of file From d4d563118106b509efb9730c45dc76d5a34b877e Mon Sep 17 00:00:00 2001 From: mothran Date: Mon, 14 Sep 2015 20:42:41 -0700 Subject: [PATCH 05/10] updated the sparc.h header so the alignment of certain registers was correct --- include/unicorn/sparc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/unicorn/sparc.h b/include/unicorn/sparc.h index 25a1140b..61f453d1 100644 --- a/include/unicorn/sparc.h +++ b/include/unicorn/sparc.h @@ -75,7 +75,6 @@ typedef enum uc_sparc_reg { UC_SPARC_REG_FCC1, UC_SPARC_REG_FCC2, UC_SPARC_REG_FCC3, - UC_SPARC_REG_FP, UC_SPARC_REG_G0, UC_SPARC_REG_G1, UC_SPARC_REG_G2, @@ -90,6 +89,7 @@ typedef enum uc_sparc_reg { UC_SPARC_REG_I3, UC_SPARC_REG_I4, UC_SPARC_REG_I5, + UC_SPARC_REG_FP, UC_SPARC_REG_I7, UC_SPARC_REG_ICC, // Integer condition codes UC_SPARC_REG_L0, @@ -106,8 +106,8 @@ typedef enum uc_sparc_reg { UC_SPARC_REG_O3, UC_SPARC_REG_O4, UC_SPARC_REG_O5, + UC_SPARC_REG_SP, UC_SPARC_REG_O7, - UC_SPARC_REG_SP, UC_SPARC_REG_Y, // special register From f4894a1c77d0568b4ddc08881b08f73cfd310b7e Mon Sep 17 00:00:00 2001 From: mothran Date: Mon, 14 Sep 2015 20:44:50 -0700 Subject: [PATCH 06/10] removed unneed cases in the switch statement --- qemu/target-sparc/unicorn.c | 12 ------------ qemu/target-sparc/unicorn64.c | 12 ------------ 2 files changed, 24 deletions(-) diff --git a/qemu/target-sparc/unicorn.c b/qemu/target-sparc/unicorn.c index 93bdffdc..b8ea29d8 100644 --- a/qemu/target-sparc/unicorn.c +++ b/qemu/target-sparc/unicorn.c @@ -63,12 +63,6 @@ int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) case UC_SPARC_REG_PC: *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.pc; break; - case UC_SPARC_REG_SP: - *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[6]; - break; - case UC_SPARC_REG_FP: - *(int32_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[22]; - break; } } @@ -100,12 +94,6 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) SPARC_CPU(uc, mycpu)->env.pc = *(uint32_t *)value; SPARC_CPU(uc, mycpu)->env.npc = *(uint32_t *)value + 4; break; - case UC_SPARC_REG_SP: - SPARC_CPU(uc, mycpu)->env.regwptr[6] = *(uint32_t *)value; - break; - case UC_SPARC_REG_FP: - SPARC_CPU(uc, mycpu)->env.regwptr[22] = *(uint32_t *)value; - break; } } diff --git a/qemu/target-sparc/unicorn64.c b/qemu/target-sparc/unicorn64.c index 49428fa3..a3700db0 100644 --- a/qemu/target-sparc/unicorn64.c +++ b/qemu/target-sparc/unicorn64.c @@ -46,12 +46,6 @@ int sparc_reg_read(struct uc_struct *uc, unsigned int regid, void *value) case UC_SPARC_REG_PC: *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.pc; break; - case UC_SPARC_REG_SP: - *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[6]; - break; - case UC_SPARC_REG_FP: - *(int64_t *)value = SPARC_CPU(uc, mycpu)->env.regwptr[22]; - break; } } @@ -83,12 +77,6 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value) SPARC_CPU(uc, mycpu)->env.pc = *(uint64_t *)value; SPARC_CPU(uc, mycpu)->env.npc = *(uint64_t *)value + 8; break; - case UC_SPARC_REG_SP: - SPARC_CPU(uc, mycpu)->env.regwptr[6] = *(uint64_t *)value; - break; - case UC_SPARC_REG_FP: - SPARC_CPU(uc, mycpu)->env.regwptr[22] = *(uint64_t *)value; - break; } } From 1638372793df1f160f1994a9d5ae3bd86b6dc56c Mon Sep 17 00:00:00 2001 From: mothran Date: Mon, 14 Sep 2015 20:48:31 -0700 Subject: [PATCH 07/10] fix small whitespace issue --- include/unicorn/sparc.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/unicorn/sparc.h b/include/unicorn/sparc.h index 61f453d1..353dbb34 100644 --- a/include/unicorn/sparc.h +++ b/include/unicorn/sparc.h @@ -106,14 +106,14 @@ typedef enum uc_sparc_reg { UC_SPARC_REG_O3, UC_SPARC_REG_O4, UC_SPARC_REG_O5, - UC_SPARC_REG_SP, + UC_SPARC_REG_SP, UC_SPARC_REG_O7, UC_SPARC_REG_Y, // special register UC_SPARC_REG_XCC, - // pseudo register + // pseudo register UC_SPARC_REG_PC, // program counter register UC_SPARC_REG_ENDING, // <-- mark the end of the list of registers From 69d73aa845aa3100a1064efe6b595928eaf93d11 Mon Sep 17 00:00:00 2001 From: mothran Date: Mon, 14 Sep 2015 21:23:42 -0700 Subject: [PATCH 08/10] added emulated SPARC code for regress/sparc_reg.py, appears to be a bug in G and I registers --- regress/sparc_reg.py | 139 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 119 insertions(+), 20 deletions(-) diff --git a/regress/sparc_reg.py b/regress/sparc_reg.py index 33bb03e0..1a2a16ae 100755 --- a/regress/sparc_reg.py +++ b/regress/sparc_reg.py @@ -3,28 +3,127 @@ from unicorn import * from unicorn.sparc_const import * +PAGE_SIZE = 1 * 1024 * 1024 + uc = Uc(UC_ARCH_SPARC, UC_MODE_32) uc.reg_write(UC_SPARC_REG_SP, 100) -uc.reg_write(UC_SPARC_REG_FP, 100) -uc.reg_write(UC_SPARC_REG_G0, 200) -uc.reg_write(UC_SPARC_REG_O0, 201) -uc.reg_write(UC_SPARC_REG_L0, 202) -uc.reg_write(UC_SPARC_REG_L7, 203) -uc.reg_write(UC_SPARC_REG_I0, 204) +uc.reg_write(UC_SPARC_REG_FP, 200) +uc.reg_write(UC_SPARC_REG_G0, 300) +uc.reg_write(UC_SPARC_REG_O0, 400) +uc.reg_write(UC_SPARC_REG_L0, 500) +uc.reg_write(UC_SPARC_REG_I0, 600) -print 'writing sp = 100, fp = 100' -print 'sp =', uc.reg_read(UC_SPARC_REG_SP) -print 'fp =', uc.reg_read(UC_SPARC_REG_FP) -print 'g0 =', uc.reg_read(UC_SPARC_REG_G0) -print 'o0 =', uc.reg_read(UC_SPARC_REG_O0) -print 'l0 =', uc.reg_read(UC_SPARC_REG_L0) -print 'l7 =', uc.reg_read(UC_SPARC_REG_L7) -print 'i0 =', uc.reg_read(UC_SPARC_REG_I0) + # 0x0: \x80\x00\x20\x01 inc %g0 + # 0x4: \x90\x02\x20\x01 inc %o0 + # 0x8: \xA0\x04\x20\x01 inc %l0 + # 0xc: \xB0\x06\x20\x01 inc %i0 +CODE = "\x80\x00\x20\x01" \ + "\x90\x02\x20\x01" \ + "\xA0\x04\x20\x01" \ + "\xB0\x06\x20\x01" + # 0x0: \x80\x00\x20\x01 add %g0, 1, %g0 + # 0x4: \x90\x02\x20\x01 add %o0, 1, %o0 + # 0x8: \xA0\x04\x20\x01 add %l0, 1, %l0 + # 0xc: \xB0\x06\x20\x01 add %i0, 1, %i0 +CODE2 = "\x80\x00\x20\x01" \ + "\x90\x02\x20\x01" \ + "\xA0\x04\x20\x01" \ + "\xB0\x06\x20\x01" + + +uc.mem_map(0, PAGE_SIZE) +uc.mem_write(0, CODE2) +uc.emu_start(0, len(CODE2), 0, 4) + +def print_registers(mu): + g0 = mu.reg_read(UC_SPARC_REG_G0) + g1 = mu.reg_read(UC_SPARC_REG_G1) + g2 = mu.reg_read(UC_SPARC_REG_G2) + g3 = mu.reg_read(UC_SPARC_REG_G3) + g4 = mu.reg_read(UC_SPARC_REG_G4) + g5 = mu.reg_read(UC_SPARC_REG_G5) + g6 = mu.reg_read(UC_SPARC_REG_G6) + g7 = mu.reg_read(UC_SPARC_REG_G7) + + o0 = mu.reg_read(UC_SPARC_REG_O0) + o1 = mu.reg_read(UC_SPARC_REG_O1) + o2 = mu.reg_read(UC_SPARC_REG_O2) + o3 = mu.reg_read(UC_SPARC_REG_O3) + o4 = mu.reg_read(UC_SPARC_REG_O4) + o5 = mu.reg_read(UC_SPARC_REG_O5) + o6 = mu.reg_read(UC_SPARC_REG_O6) + o7 = mu.reg_read(UC_SPARC_REG_O7) + + l0 = mu.reg_read(UC_SPARC_REG_L0) + l1 = mu.reg_read(UC_SPARC_REG_L1) + l2 = mu.reg_read(UC_SPARC_REG_L2) + l3 = mu.reg_read(UC_SPARC_REG_L3) + l4 = mu.reg_read(UC_SPARC_REG_L4) + l5 = mu.reg_read(UC_SPARC_REG_L5) + l6 = mu.reg_read(UC_SPARC_REG_L6) + l7 = mu.reg_read(UC_SPARC_REG_L7) + + i0 = mu.reg_read(UC_SPARC_REG_I0) + i1 = mu.reg_read(UC_SPARC_REG_I1) + i2 = mu.reg_read(UC_SPARC_REG_I2) + i3 = mu.reg_read(UC_SPARC_REG_I3) + i4 = mu.reg_read(UC_SPARC_REG_I4) + i5 = mu.reg_read(UC_SPARC_REG_I5) + i6 = mu.reg_read(UC_SPARC_REG_I6) + i7 = mu.reg_read(UC_SPARC_REG_I7) + + pc = mu.reg_read(UC_SPARC_REG_PC) + sp = mu.reg_read(UC_SPARC_REG_SP) + fp = mu.reg_read(UC_SPARC_REG_FP) + print(" G0 = %d" % g0) + print(" G1 = %d" % g1) + print(" G2 = %d" % g2) + print(" G3 = %d" % g3) + print(" G4 = %d" % g4) + print(" G5 = %d" % g5) + print(" G6 = %d" % g6) + print(" G7 = %d" % g7) + print("") + print(" O0 = %d" % o0) + print(" O1 = %d" % o1) + print(" O2 = %d" % o2) + print(" O3 = %d" % o3) + print(" O4 = %d" % o4) + print(" O5 = %d" % o5) + print(" O6 = %d" % o6) + print(" O7 = %d" % o7) + print("") + print(" L0 = %d" % l0) + print(" L1 = %d" % l1) + print(" L2 = %d" % l2) + print(" L3 = %d" % l3) + print(" L4 = %d" % l4) + print(" L5 = %d" % l5) + print(" L6 = %d" % l6) + print(" L7 = %d" % l7) + print("") + print(" I0 = %d" % i0) + print(" I1 = %d" % i1) + print(" I2 = %d" % i2) + print(" I3 = %d" % i3) + print(" I4 = %d" % i4) + print(" I5 = %d" % i5) + print(" I6 = %d" % i6) + print(" I7 = %d" % i7) + print("") + print(" PC = %d" % pc) + print(" SP = %d" % sp) + print(" FP = %d" % fp) + print("") + +print_registers(uc) + +assert uc.reg_read(UC_SPARC_REG_PC) == 16 # make sure we executed all 4 instructions assert uc.reg_read(UC_SPARC_REG_SP) == 100 -assert uc.reg_read(UC_SPARC_REG_FP) == 100 -assert uc.reg_read(UC_SPARC_REG_G0) == 200 -assert uc.reg_read(UC_SPARC_REG_O0) == 201 -assert uc.reg_read(UC_SPARC_REG_L0) == 202 -assert uc.reg_read(UC_SPARC_REG_L7) == 203 -assert uc.reg_read(UC_SPARC_REG_I0) == 204 \ No newline at end of file +assert uc.reg_read(UC_SPARC_REG_FP) == 200 + +assert uc.reg_read(UC_SPARC_REG_G0) == 301 +assert uc.reg_read(UC_SPARC_REG_O0) == 401 +assert uc.reg_read(UC_SPARC_REG_L0) == 501 +assert uc.reg_read(UC_SPARC_REG_I0) == 601 \ No newline at end of file From d1e19df64e7012beec0fa638b622976725153734 Mon Sep 17 00:00:00 2001 From: mothran Date: Mon, 14 Sep 2015 23:05:33 -0700 Subject: [PATCH 09/10] update the sparc_reg to test all g/o/l registers --- regress/sparc_reg.py | 108 ++++++++++++++++++++++++++++++++----------- 1 file changed, 80 insertions(+), 28 deletions(-) diff --git a/regress/sparc_reg.py b/regress/sparc_reg.py index 1a2a16ae..6442ebe8 100755 --- a/regress/sparc_reg.py +++ b/regress/sparc_reg.py @@ -8,33 +8,60 @@ PAGE_SIZE = 1 * 1024 * 1024 uc = Uc(UC_ARCH_SPARC, UC_MODE_32) uc.reg_write(UC_SPARC_REG_SP, 100) uc.reg_write(UC_SPARC_REG_FP, 200) -uc.reg_write(UC_SPARC_REG_G0, 300) -uc.reg_write(UC_SPARC_REG_O0, 400) -uc.reg_write(UC_SPARC_REG_L0, 500) -uc.reg_write(UC_SPARC_REG_I0, 600) - - # 0x0: \x80\x00\x20\x01 inc %g0 - # 0x4: \x90\x02\x20\x01 inc %o0 - # 0x8: \xA0\x04\x20\x01 inc %l0 - # 0xc: \xB0\x06\x20\x01 inc %i0 -CODE = "\x80\x00\x20\x01" \ - "\x90\x02\x20\x01" \ - "\xA0\x04\x20\x01" \ - "\xB0\x06\x20\x01" # 0x0: \x80\x00\x20\x01 add %g0, 1, %g0 - # 0x4: \x90\x02\x20\x01 add %o0, 1, %o0 - # 0x8: \xA0\x04\x20\x01 add %l0, 1, %l0 - # 0xc: \xB0\x06\x20\x01 add %i0, 1, %i0 -CODE2 = "\x80\x00\x20\x01" \ - "\x90\x02\x20\x01" \ - "\xA0\x04\x20\x01" \ - "\xB0\x06\x20\x01" + # 0x4: \x82\x00\x60\x01 add %g1, 1, %g1 + # 0x8: \x84\x00\xA0\x01 add %g2, 1, %g2 + # 0xc: \x86\x00\xE0\x01 add %g3, 1, %g3 + # 0x10: \x88\x01\x20\x01 add %g4, 1, %g4 + # 0x14: \x8A\x01\x60\x01 add %g5, 1, %g5 + # 0x18: \x8C\x01\xA0\x01 add %g6, 1, %g6 + # 0x1c: \x8E\x01\xE0\x01 add %g7, 1, %g7 + # 0x20: \x90\x02\x20\x01 add %o0, 1, %o0 + # 0x24: \x92\x02\x60\x01 add %o1, 1, %o1 + # 0x28: \x94\x02\xA0\x01 add %o2, 1, %o2 + # 0x2c: \x96\x02\xE0\x01 add %o3, 1, %o3 + # 0x30: \x98\x03\x20\x01 add %o4, 1, %o4 + # 0x34: \x9A\x03\x60\x01 add %o5, 1, %o5 + # 0x38: \x9C\x03\xA0\x01 add %sp, 1, %sp + # 0x3c: \x9E\x03\xE0\x01 add %o7, 1, %o7 + # 0x40: \xA0\x04\x20\x01 add %l0, 1, %l0 + # 0x44: \xA2\x04\x60\x01 add %l1, 1, %l1 + # 0x48: \xA4\x04\xA0\x01 add %l2, 1, %l2 + # 0x4c: \xA6\x04\xE0\x01 add %l3, 1, %l3 + # 0x50: \xA8\x05\x20\x01 add %l4, 1, %l4 + # 0x54: \xAA\x05\x60\x01 add %l5, 1, %l5 + # 0x58: \xAC\x05\xA0\x01 add %l6, 1, %l6 + # 0x5c: \xAE\x05\xE0\x01 add %l7, 1, %l7 +CODE = "\x80\x00\x20\x01" \ + "\x82\x00\x60\x01" \ + "\x84\x00\xA0\x01" \ + "\x86\x00\xE0\x01" \ + "\x88\x01\x20\x01" \ + "\x8A\x01\x60\x01" \ + "\x8C\x01\xA0\x01" \ + "\x8E\x01\xE0\x01" \ + "\x90\x02\x20\x01" \ + "\x92\x02\x60\x01" \ + "\x94\x02\xA0\x01" \ + "\x96\x02\xE0\x01" \ + "\x98\x03\x20\x01" \ + "\x9A\x03\x60\x01" \ + "\x9C\x03\xA0\x01" \ + "\x9E\x03\xE0\x01" \ + "\xA0\x04\x20\x01" \ + "\xA2\x04\x60\x01" \ + "\xA4\x04\xA0\x01" \ + "\xA6\x04\xE0\x01" \ + "\xA8\x05\x20\x01" \ + "\xAA\x05\x60\x01" \ + "\xAC\x05\xA0\x01" \ + "\xAE\x05\xE0\x01" uc.mem_map(0, PAGE_SIZE) -uc.mem_write(0, CODE2) -uc.emu_start(0, len(CODE2), 0, 4) +uc.mem_write(0, CODE) +uc.emu_start(0, len(CODE), 0, 24) def print_registers(mu): g0 = mu.reg_read(UC_SPARC_REG_G0) @@ -119,11 +146,36 @@ def print_registers(mu): print_registers(uc) -assert uc.reg_read(UC_SPARC_REG_PC) == 16 # make sure we executed all 4 instructions -assert uc.reg_read(UC_SPARC_REG_SP) == 100 +assert uc.reg_read(UC_SPARC_REG_PC) == 96 # make sure we executed all instructions +assert uc.reg_read(UC_SPARC_REG_SP) == 101 assert uc.reg_read(UC_SPARC_REG_FP) == 200 -assert uc.reg_read(UC_SPARC_REG_G0) == 301 -assert uc.reg_read(UC_SPARC_REG_O0) == 401 -assert uc.reg_read(UC_SPARC_REG_L0) == 501 -assert uc.reg_read(UC_SPARC_REG_I0) == 601 \ No newline at end of file +assert uc.reg_read(UC_SPARC_REG_G0) == 0 # G0 is always zero +assert uc.reg_read(UC_SPARC_REG_G1) == 1 +assert uc.reg_read(UC_SPARC_REG_G2) == 1 +assert uc.reg_read(UC_SPARC_REG_G3) == 1 +assert uc.reg_read(UC_SPARC_REG_G4) == 1 +assert uc.reg_read(UC_SPARC_REG_G5) == 1 +assert uc.reg_read(UC_SPARC_REG_G6) == 1 +assert uc.reg_read(UC_SPARC_REG_G7) == 1 + +assert uc.reg_read(UC_SPARC_REG_O0) == 1 +assert uc.reg_read(UC_SPARC_REG_O1) == 1 +assert uc.reg_read(UC_SPARC_REG_O2) == 1 +assert uc.reg_read(UC_SPARC_REG_O3) == 1 +assert uc.reg_read(UC_SPARC_REG_O4) == 1 +assert uc.reg_read(UC_SPARC_REG_O5) == 1 +assert uc.reg_read(UC_SPARC_REG_O6) == 101 +assert uc.reg_read(UC_SPARC_REG_O7) == 1 + +assert uc.reg_read(UC_SPARC_REG_L0) == 1 +assert uc.reg_read(UC_SPARC_REG_L1) == 1 +assert uc.reg_read(UC_SPARC_REG_L2) == 1 +assert uc.reg_read(UC_SPARC_REG_L3) == 1 +assert uc.reg_read(UC_SPARC_REG_L4) == 1 +assert uc.reg_read(UC_SPARC_REG_L5) == 1 +assert uc.reg_read(UC_SPARC_REG_L6) == 1 +assert uc.reg_read(UC_SPARC_REG_L7) == 1 + +assert uc.reg_read(UC_SPARC_REG_O0) == 1 +assert uc.reg_read(UC_SPARC_REG_L0) == 1 \ No newline at end of file From 6962126707a4bb015af22c80b32ac215dcc1e7bd Mon Sep 17 00:00:00 2001 From: mothran Date: Mon, 14 Sep 2015 23:28:09 -0700 Subject: [PATCH 10/10] update sparc_reg.py with %i registers --- regress/sparc_reg.py | 36 ++++++++++++++++++++++++++++++------ 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/regress/sparc_reg.py b/regress/sparc_reg.py index 6442ebe8..99c34cdc 100755 --- a/regress/sparc_reg.py +++ b/regress/sparc_reg.py @@ -33,6 +33,15 @@ uc.reg_write(UC_SPARC_REG_FP, 200) # 0x54: \xAA\x05\x60\x01 add %l5, 1, %l5 # 0x58: \xAC\x05\xA0\x01 add %l6, 1, %l6 # 0x5c: \xAE\x05\xE0\x01 add %l7, 1, %l7 + # 0x0: \xB0\x06\x20\x01 add %i0, 1, %i0 + # 0x4: \xB2\x06\x60\x01 add %i1, 1, %i1 + # 0x8: \xB4\x06\xA0\x01 add %i2, 1, %i2 + # 0xc: \xB6\x06\xE0\x01 add %i3, 1, %i3 + # 0x10: \xB8\x07\x20\x01 add %i4, 1, %i4 + # 0x14: \xBA\x07\x60\x01 add %i5, 1, %i5 + # 0x18: \xBC\x07\xA0\x01 add %fp, 1, %fp + # 0x1c: \xBE\x07\xE0\x01 add %i7, 1, %i7 + CODE = "\x80\x00\x20\x01" \ "\x82\x00\x60\x01" \ @@ -57,11 +66,20 @@ CODE = "\x80\x00\x20\x01" \ "\xA8\x05\x20\x01" \ "\xAA\x05\x60\x01" \ "\xAC\x05\xA0\x01" \ - "\xAE\x05\xE0\x01" + "\xAE\x05\xE0\x01" \ + "\xB0\x06\x20\x01" \ + "\xB2\x06\x60\x01" \ + "\xB4\x06\xA0\x01" \ + "\xB6\x06\xE0\x01" \ + "\xB8\x07\x20\x01" \ + "\xBA\x07\x60\x01" \ + "\xBC\x07\xA0\x01" \ + "\xBE\x07\xE0\x01" + uc.mem_map(0, PAGE_SIZE) uc.mem_write(0, CODE) -uc.emu_start(0, len(CODE), 0, 24) +uc.emu_start(0, len(CODE), 0, 32) def print_registers(mu): g0 = mu.reg_read(UC_SPARC_REG_G0) @@ -146,9 +164,9 @@ def print_registers(mu): print_registers(uc) -assert uc.reg_read(UC_SPARC_REG_PC) == 96 # make sure we executed all instructions +assert uc.reg_read(UC_SPARC_REG_PC) == 128 # make sure we executed all instructions assert uc.reg_read(UC_SPARC_REG_SP) == 101 -assert uc.reg_read(UC_SPARC_REG_FP) == 200 +assert uc.reg_read(UC_SPARC_REG_FP) == 201 assert uc.reg_read(UC_SPARC_REG_G0) == 0 # G0 is always zero assert uc.reg_read(UC_SPARC_REG_G1) == 1 @@ -177,5 +195,11 @@ assert uc.reg_read(UC_SPARC_REG_L5) == 1 assert uc.reg_read(UC_SPARC_REG_L6) == 1 assert uc.reg_read(UC_SPARC_REG_L7) == 1 -assert uc.reg_read(UC_SPARC_REG_O0) == 1 -assert uc.reg_read(UC_SPARC_REG_L0) == 1 \ No newline at end of file +assert uc.reg_read(UC_SPARC_REG_I0) == 1 +assert uc.reg_read(UC_SPARC_REG_I1) == 1 +assert uc.reg_read(UC_SPARC_REG_I2) == 1 +assert uc.reg_read(UC_SPARC_REG_I3) == 1 +assert uc.reg_read(UC_SPARC_REG_I4) == 1 +assert uc.reg_read(UC_SPARC_REG_I5) == 1 +assert uc.reg_read(UC_SPARC_REG_I6) == 201 +assert uc.reg_read(UC_SPARC_REG_I7) == 1 \ No newline at end of file