From d134c623660a709f7000e3eb851333f346d9dab5 Mon Sep 17 00:00:00 2001 From: Ryan Hileman Date: Tue, 8 Sep 2015 00:44:14 -0700 Subject: [PATCH] add regress for #130 --- regress/mips_except.py | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100755 regress/mips_except.py diff --git a/regress/mips_except.py b/regress/mips_except.py new file mode 100755 index 00000000..f24b5b85 --- /dev/null +++ b/regress/mips_except.py @@ -0,0 +1,29 @@ +#!/usr/bin/python +from unicorn import * +from unicorn.mips_const import * + +def hook_intr(uc, intno, _): + print 'interrupt', intno + +CODE = 0x400000 +asm = '0000a48f'.decode('hex') + +uc = Uc(UC_ARCH_MIPS, UC_MODE_MIPS32 + UC_MODE_LITTLE_ENDIAN) +uc.hook_add(UC_HOOK_INTR, hook_intr) +uc.mem_map(CODE, 0x1000) +uc.mem_write(CODE, asm) + +print 'unaligned access (exc 12)' +uc.reg_write(UC_MIPS_REG_SP, 0x01) +uc.emu_start(CODE, CODE + len(asm), 300) +print + +print 'dunno (exc 26)' +uc.reg_write(UC_MIPS_REG_SP, 0xFFFFFFF0) +uc.emu_start(CODE, CODE + len(asm), 200) +print + +print 'unassigned access (exc 28)' +uc.reg_write(UC_MIPS_REG_SP, 0x80000000) +uc.emu_start(CODE, CODE + len(asm), 100) +print