Update bindings

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lazymio 2022-01-05 22:00:59 +01:00
parent 8ad9f8ecb1
commit c671efe798
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GPG Key ID: DFF27E34A47CB873
6 changed files with 48 additions and 42 deletions

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@ -35,13 +35,14 @@ module Arm =
let UC_CPU_ARM_PXA260 = 23
let UC_CPU_ARM_PXA261 = 24
let UC_CPU_ARM_PXA262 = 25
let UC_CPU_ARM_PXA270A0 = 26
let UC_CPU_ARM_PXA270A1 = 27
let UC_CPU_ARM_PXA270B0 = 28
let UC_CPU_ARM_PXA270B1 = 29
let UC_CPU_ARM_PXA270C0 = 30
let UC_CPU_ARM_PXA270C5 = 31
let UC_CPU_ARM_MAX = 32
let UC_CPU_ARM_PXA270 = 26
let UC_CPU_ARM_PXA270A0 = 27
let UC_CPU_ARM_PXA270A1 = 28
let UC_CPU_ARM_PXA270B0 = 29
let UC_CPU_ARM_PXA270B1 = 30
let UC_CPU_ARM_PXA270C0 = 31
let UC_CPU_ARM_PXA270C5 = 32
let UC_CPU_ARM_MAX = 33
// ARM registers

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@ -30,13 +30,14 @@ const (
CPU_ARM_PXA260 = 23
CPU_ARM_PXA261 = 24
CPU_ARM_PXA262 = 25
CPU_ARM_PXA270A0 = 26
CPU_ARM_PXA270A1 = 27
CPU_ARM_PXA270B0 = 28
CPU_ARM_PXA270B1 = 29
CPU_ARM_PXA270C0 = 30
CPU_ARM_PXA270C5 = 31
CPU_ARM_MAX = 32
CPU_ARM_PXA270 = 26
CPU_ARM_PXA270A0 = 27
CPU_ARM_PXA270A1 = 28
CPU_ARM_PXA270B0 = 29
CPU_ARM_PXA270B1 = 30
CPU_ARM_PXA270C0 = 31
CPU_ARM_PXA270C5 = 32
CPU_ARM_MAX = 33
// ARM registers

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@ -32,13 +32,14 @@ public interface ArmConst {
public static final int UC_CPU_ARM_PXA260 = 23;
public static final int UC_CPU_ARM_PXA261 = 24;
public static final int UC_CPU_ARM_PXA262 = 25;
public static final int UC_CPU_ARM_PXA270A0 = 26;
public static final int UC_CPU_ARM_PXA270A1 = 27;
public static final int UC_CPU_ARM_PXA270B0 = 28;
public static final int UC_CPU_ARM_PXA270B1 = 29;
public static final int UC_CPU_ARM_PXA270C0 = 30;
public static final int UC_CPU_ARM_PXA270C5 = 31;
public static final int UC_CPU_ARM_MAX = 32;
public static final int UC_CPU_ARM_PXA270 = 26;
public static final int UC_CPU_ARM_PXA270A0 = 27;
public static final int UC_CPU_ARM_PXA270A1 = 28;
public static final int UC_CPU_ARM_PXA270B0 = 29;
public static final int UC_CPU_ARM_PXA270B1 = 30;
public static final int UC_CPU_ARM_PXA270C0 = 31;
public static final int UC_CPU_ARM_PXA270C5 = 32;
public static final int UC_CPU_ARM_MAX = 33;
// ARM registers

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@ -33,13 +33,14 @@ const
UC_CPU_ARM_PXA260 = 23;
UC_CPU_ARM_PXA261 = 24;
UC_CPU_ARM_PXA262 = 25;
UC_CPU_ARM_PXA270A0 = 26;
UC_CPU_ARM_PXA270A1 = 27;
UC_CPU_ARM_PXA270B0 = 28;
UC_CPU_ARM_PXA270B1 = 29;
UC_CPU_ARM_PXA270C0 = 30;
UC_CPU_ARM_PXA270C5 = 31;
UC_CPU_ARM_MAX = 32;
UC_CPU_ARM_PXA270 = 26;
UC_CPU_ARM_PXA270A0 = 27;
UC_CPU_ARM_PXA270A1 = 28;
UC_CPU_ARM_PXA270B0 = 29;
UC_CPU_ARM_PXA270B1 = 30;
UC_CPU_ARM_PXA270C0 = 31;
UC_CPU_ARM_PXA270C5 = 32;
UC_CPU_ARM_MAX = 33;
// ARM registers

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@ -28,13 +28,14 @@ UC_CPU_ARM_PXA255 = 22
UC_CPU_ARM_PXA260 = 23
UC_CPU_ARM_PXA261 = 24
UC_CPU_ARM_PXA262 = 25
UC_CPU_ARM_PXA270A0 = 26
UC_CPU_ARM_PXA270A1 = 27
UC_CPU_ARM_PXA270B0 = 28
UC_CPU_ARM_PXA270B1 = 29
UC_CPU_ARM_PXA270C0 = 30
UC_CPU_ARM_PXA270C5 = 31
UC_CPU_ARM_MAX = 32
UC_CPU_ARM_PXA270 = 26
UC_CPU_ARM_PXA270A0 = 27
UC_CPU_ARM_PXA270A1 = 28
UC_CPU_ARM_PXA270B0 = 29
UC_CPU_ARM_PXA270B1 = 30
UC_CPU_ARM_PXA270C0 = 31
UC_CPU_ARM_PXA270C5 = 32
UC_CPU_ARM_MAX = 33
# ARM registers

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@ -30,13 +30,14 @@ module UnicornEngine
UC_CPU_ARM_PXA260 = 23
UC_CPU_ARM_PXA261 = 24
UC_CPU_ARM_PXA262 = 25
UC_CPU_ARM_PXA270A0 = 26
UC_CPU_ARM_PXA270A1 = 27
UC_CPU_ARM_PXA270B0 = 28
UC_CPU_ARM_PXA270B1 = 29
UC_CPU_ARM_PXA270C0 = 30
UC_CPU_ARM_PXA270C5 = 31
UC_CPU_ARM_MAX = 32
UC_CPU_ARM_PXA270 = 26
UC_CPU_ARM_PXA270A0 = 27
UC_CPU_ARM_PXA270A1 = 28
UC_CPU_ARM_PXA270B0 = 29
UC_CPU_ARM_PXA270B1 = 30
UC_CPU_ARM_PXA270C0 = 31
UC_CPU_ARM_PXA270C5 = 32
UC_CPU_ARM_MAX = 33
# ARM registers