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zig consts

This commit is contained in:
Matheus C. França 2023-03-23 10:09:41 -03:00
parent 7b8c63dfe6
commit c6158b8628
15 changed files with 3722 additions and 0 deletions
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1
bindings/Makefile
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@ -26,6 +26,7 @@ build:
$(MAKE) -C ruby gen_const
python3 const_generator.py dotnet
python3 const_generator.py pascal
python3 const_generator.py zig
install: build
$(MAKE) -C python install

20
bindings/const_generator.py
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@ -129,6 +129,26 @@ template = {
'comment_open': '//',
'comment_close': '',
},
'zig': {
'header': "// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT\n\npub const %sConst = enum(c_int) {\n",
'footer': "\n};\n",
'line_format': '\t%s = %s,\n',
'out_file': './zig/unicorn/%s_const.zig',
# prefixes for constant filenames of all archs - case sensitive
'arm.h': 'arm',
'arm64.h': 'arm64',
'mips.h': 'mips',
'x86.h': 'x86',
'sparc.h': 'sparc',
'm68k.h': 'm68k',
'ppc.h': 'ppc',
'riscv.h': 'riscv',
's390x.h' : 's390x',
'tricore.h' : 'tricore',
'unicorn.h': 'unicorn',
'comment_open': '//',
'comment_close': '',
},
}
# markup for comments to be added to autogen files

10
bindings/zig/README.md Normal file
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@ -0,0 +1,10 @@
# Unicorn-engine-Zig
[Zig](https://ziglang.org/) bindings for the [Unicorn](http://www.unicorn-engine.org/) emulator with utility functions.
*Unicorn* is a lightweight multi-platform, multi-architecture CPU emulator framework
based on [QEMU](http://www.qemu.org/).
## How to use
Add to your project the file `unicorn/unicorn.zig` that will manage all the available architectures.

337
bindings/zig/unicorn/arm64_const.zig Normal file
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@ -0,0 +1,337 @@
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
pub const arm64Const = enum(c_int) {
// ARM64 CPU
CPU_ARM64_A57 = 0,
CPU_ARM64_A53 = 1,
CPU_ARM64_A72 = 2,
CPU_ARM64_MAX = 3,
CPU_ARM64_ENDING = 4,
// ARM64 registers
ARM64_REG_INVALID = 0,
ARM64_REG_X29 = 1,
ARM64_REG_X30 = 2,
ARM64_REG_NZCV = 3,
ARM64_REG_SP = 4,
ARM64_REG_WSP = 5,
ARM64_REG_WZR = 6,
ARM64_REG_XZR = 7,
ARM64_REG_B0 = 8,
ARM64_REG_B1 = 9,
ARM64_REG_B2 = 10,
ARM64_REG_B3 = 11,
ARM64_REG_B4 = 12,
ARM64_REG_B5 = 13,
ARM64_REG_B6 = 14,
ARM64_REG_B7 = 15,
ARM64_REG_B8 = 16,
ARM64_REG_B9 = 17,
ARM64_REG_B10 = 18,
ARM64_REG_B11 = 19,
ARM64_REG_B12 = 20,
ARM64_REG_B13 = 21,
ARM64_REG_B14 = 22,
ARM64_REG_B15 = 23,
ARM64_REG_B16 = 24,
ARM64_REG_B17 = 25,
ARM64_REG_B18 = 26,
ARM64_REG_B19 = 27,
ARM64_REG_B20 = 28,
ARM64_REG_B21 = 29,
ARM64_REG_B22 = 30,
ARM64_REG_B23 = 31,
ARM64_REG_B24 = 32,
ARM64_REG_B25 = 33,
ARM64_REG_B26 = 34,
ARM64_REG_B27 = 35,
ARM64_REG_B28 = 36,
ARM64_REG_B29 = 37,
ARM64_REG_B30 = 38,
ARM64_REG_B31 = 39,
ARM64_REG_D0 = 40,
ARM64_REG_D1 = 41,
ARM64_REG_D2 = 42,
ARM64_REG_D3 = 43,
ARM64_REG_D4 = 44,
ARM64_REG_D5 = 45,
ARM64_REG_D6 = 46,
ARM64_REG_D7 = 47,
ARM64_REG_D8 = 48,
ARM64_REG_D9 = 49,
ARM64_REG_D10 = 50,
ARM64_REG_D11 = 51,
ARM64_REG_D12 = 52,
ARM64_REG_D13 = 53,
ARM64_REG_D14 = 54,
ARM64_REG_D15 = 55,
ARM64_REG_D16 = 56,
ARM64_REG_D17 = 57,
ARM64_REG_D18 = 58,
ARM64_REG_D19 = 59,
ARM64_REG_D20 = 60,
ARM64_REG_D21 = 61,
ARM64_REG_D22 = 62,
ARM64_REG_D23 = 63,
ARM64_REG_D24 = 64,
ARM64_REG_D25 = 65,
ARM64_REG_D26 = 66,
ARM64_REG_D27 = 67,
ARM64_REG_D28 = 68,
ARM64_REG_D29 = 69,
ARM64_REG_D30 = 70,
ARM64_REG_D31 = 71,
ARM64_REG_H0 = 72,
ARM64_REG_H1 = 73,
ARM64_REG_H2 = 74,
ARM64_REG_H3 = 75,
ARM64_REG_H4 = 76,
ARM64_REG_H5 = 77,
ARM64_REG_H6 = 78,
ARM64_REG_H7 = 79,
ARM64_REG_H8 = 80,
ARM64_REG_H9 = 81,
ARM64_REG_H10 = 82,
ARM64_REG_H11 = 83,
ARM64_REG_H12 = 84,
ARM64_REG_H13 = 85,
ARM64_REG_H14 = 86,
ARM64_REG_H15 = 87,
ARM64_REG_H16 = 88,
ARM64_REG_H17 = 89,
ARM64_REG_H18 = 90,
ARM64_REG_H19 = 91,
ARM64_REG_H20 = 92,
ARM64_REG_H21 = 93,
ARM64_REG_H22 = 94,
ARM64_REG_H23 = 95,
ARM64_REG_H24 = 96,
ARM64_REG_H25 = 97,
ARM64_REG_H26 = 98,
ARM64_REG_H27 = 99,
ARM64_REG_H28 = 100,
ARM64_REG_H29 = 101,
ARM64_REG_H30 = 102,
ARM64_REG_H31 = 103,
ARM64_REG_Q0 = 104,
ARM64_REG_Q1 = 105,
ARM64_REG_Q2 = 106,
ARM64_REG_Q3 = 107,
ARM64_REG_Q4 = 108,
ARM64_REG_Q5 = 109,
ARM64_REG_Q6 = 110,
ARM64_REG_Q7 = 111,
ARM64_REG_Q8 = 112,
ARM64_REG_Q9 = 113,
ARM64_REG_Q10 = 114,
ARM64_REG_Q11 = 115,
ARM64_REG_Q12 = 116,
ARM64_REG_Q13 = 117,
ARM64_REG_Q14 = 118,
ARM64_REG_Q15 = 119,
ARM64_REG_Q16 = 120,
ARM64_REG_Q17 = 121,
ARM64_REG_Q18 = 122,
ARM64_REG_Q19 = 123,
ARM64_REG_Q20 = 124,
ARM64_REG_Q21 = 125,
ARM64_REG_Q22 = 126,
ARM64_REG_Q23 = 127,
ARM64_REG_Q24 = 128,
ARM64_REG_Q25 = 129,
ARM64_REG_Q26 = 130,
ARM64_REG_Q27 = 131,
ARM64_REG_Q28 = 132,
ARM64_REG_Q29 = 133,
ARM64_REG_Q30 = 134,
ARM64_REG_Q31 = 135,
ARM64_REG_S0 = 136,
ARM64_REG_S1 = 137,
ARM64_REG_S2 = 138,
ARM64_REG_S3 = 139,
ARM64_REG_S4 = 140,
ARM64_REG_S5 = 141,
ARM64_REG_S6 = 142,
ARM64_REG_S7 = 143,
ARM64_REG_S8 = 144,
ARM64_REG_S9 = 145,
ARM64_REG_S10 = 146,
ARM64_REG_S11 = 147,
ARM64_REG_S12 = 148,
ARM64_REG_S13 = 149,
ARM64_REG_S14 = 150,
ARM64_REG_S15 = 151,
ARM64_REG_S16 = 152,
ARM64_REG_S17 = 153,
ARM64_REG_S18 = 154,
ARM64_REG_S19 = 155,
ARM64_REG_S20 = 156,
ARM64_REG_S21 = 157,
ARM64_REG_S22 = 158,
ARM64_REG_S23 = 159,
ARM64_REG_S24 = 160,
ARM64_REG_S25 = 161,
ARM64_REG_S26 = 162,
ARM64_REG_S27 = 163,
ARM64_REG_S28 = 164,
ARM64_REG_S29 = 165,
ARM64_REG_S30 = 166,
ARM64_REG_S31 = 167,
ARM64_REG_W0 = 168,
ARM64_REG_W1 = 169,
ARM64_REG_W2 = 170,
ARM64_REG_W3 = 171,
ARM64_REG_W4 = 172,
ARM64_REG_W5 = 173,
ARM64_REG_W6 = 174,
ARM64_REG_W7 = 175,
ARM64_REG_W8 = 176,
ARM64_REG_W9 = 177,
ARM64_REG_W10 = 178,
ARM64_REG_W11 = 179,
ARM64_REG_W12 = 180,
ARM64_REG_W13 = 181,
ARM64_REG_W14 = 182,
ARM64_REG_W15 = 183,
ARM64_REG_W16 = 184,
ARM64_REG_W17 = 185,
ARM64_REG_W18 = 186,
ARM64_REG_W19 = 187,
ARM64_REG_W20 = 188,
ARM64_REG_W21 = 189,
ARM64_REG_W22 = 190,
ARM64_REG_W23 = 191,
ARM64_REG_W24 = 192,
ARM64_REG_W25 = 193,
ARM64_REG_W26 = 194,
ARM64_REG_W27 = 195,
ARM64_REG_W28 = 196,
ARM64_REG_W29 = 197,
ARM64_REG_W30 = 198,
ARM64_REG_X0 = 199,
ARM64_REG_X1 = 200,
ARM64_REG_X2 = 201,
ARM64_REG_X3 = 202,
ARM64_REG_X4 = 203,
ARM64_REG_X5 = 204,
ARM64_REG_X6 = 205,
ARM64_REG_X7 = 206,
ARM64_REG_X8 = 207,
ARM64_REG_X9 = 208,
ARM64_REG_X10 = 209,
ARM64_REG_X11 = 210,
ARM64_REG_X12 = 211,
ARM64_REG_X13 = 212,
ARM64_REG_X14 = 213,
ARM64_REG_X15 = 214,
ARM64_REG_X16 = 215,
ARM64_REG_X17 = 216,
ARM64_REG_X18 = 217,
ARM64_REG_X19 = 218,
ARM64_REG_X20 = 219,
ARM64_REG_X21 = 220,
ARM64_REG_X22 = 221,
ARM64_REG_X23 = 222,
ARM64_REG_X24 = 223,
ARM64_REG_X25 = 224,
ARM64_REG_X26 = 225,
ARM64_REG_X27 = 226,
ARM64_REG_X28 = 227,
ARM64_REG_V0 = 228,
ARM64_REG_V1 = 229,
ARM64_REG_V2 = 230,
ARM64_REG_V3 = 231,
ARM64_REG_V4 = 232,
ARM64_REG_V5 = 233,
ARM64_REG_V6 = 234,
ARM64_REG_V7 = 235,
ARM64_REG_V8 = 236,
ARM64_REG_V9 = 237,
ARM64_REG_V10 = 238,
ARM64_REG_V11 = 239,
ARM64_REG_V12 = 240,
ARM64_REG_V13 = 241,
ARM64_REG_V14 = 242,
ARM64_REG_V15 = 243,
ARM64_REG_V16 = 244,
ARM64_REG_V17 = 245,
ARM64_REG_V18 = 246,
ARM64_REG_V19 = 247,
ARM64_REG_V20 = 248,
ARM64_REG_V21 = 249,
ARM64_REG_V22 = 250,
ARM64_REG_V23 = 251,
ARM64_REG_V24 = 252,
ARM64_REG_V25 = 253,
ARM64_REG_V26 = 254,
ARM64_REG_V27 = 255,
ARM64_REG_V28 = 256,
ARM64_REG_V29 = 257,
ARM64_REG_V30 = 258,
ARM64_REG_V31 = 259,
// pseudo registers
ARM64_REG_PC = 260,
ARM64_REG_CPACR_EL1 = 261,
// thread registers, depreciated, use UC_ARM64_REG_CP_REG instead
ARM64_REG_TPIDR_EL0 = 262,
ARM64_REG_TPIDRRO_EL0 = 263,
ARM64_REG_TPIDR_EL1 = 264,
ARM64_REG_PSTATE = 265,
// exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead
ARM64_REG_ELR_EL0 = 266,
ARM64_REG_ELR_EL1 = 267,
ARM64_REG_ELR_EL2 = 268,
ARM64_REG_ELR_EL3 = 269,
// stack pointers registers, depreciated, use UC_ARM64_REG_CP_REG instead
ARM64_REG_SP_EL0 = 270,
ARM64_REG_SP_EL1 = 271,
ARM64_REG_SP_EL2 = 272,
ARM64_REG_SP_EL3 = 273,
// other CP15 registers, depreciated, use UC_ARM64_REG_CP_REG instead
ARM64_REG_TTBR0_EL1 = 274,
ARM64_REG_TTBR1_EL1 = 275,
ARM64_REG_ESR_EL0 = 276,
ARM64_REG_ESR_EL1 = 277,
ARM64_REG_ESR_EL2 = 278,
ARM64_REG_ESR_EL3 = 279,
ARM64_REG_FAR_EL0 = 280,
ARM64_REG_FAR_EL1 = 281,
ARM64_REG_FAR_EL2 = 282,
ARM64_REG_FAR_EL3 = 283,
ARM64_REG_PAR_EL1 = 284,
ARM64_REG_MAIR_EL1 = 285,
ARM64_REG_VBAR_EL0 = 286,
ARM64_REG_VBAR_EL1 = 287,
ARM64_REG_VBAR_EL2 = 288,
ARM64_REG_VBAR_EL3 = 289,
ARM64_REG_CP_REG = 290,
// floating point control and status registers
ARM64_REG_FPCR = 291,
ARM64_REG_FPSR = 292,
ARM64_REG_ENDING = 293,
// alias registers
ARM64_REG_IP0 = 215,
ARM64_REG_IP1 = 216,
ARM64_REG_FP = 1,
ARM64_REG_LR = 2,
// ARM64 instructions
ARM64_INS_INVALID = 0,
ARM64_INS_MRS = 1,
ARM64_INS_MSR = 2,
ARM64_INS_SYS = 3,
ARM64_INS_SYSL = 4,
ARM64_INS_ENDING = 5,
};

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bindings/zig/unicorn/arm_const.zig Normal file
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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
pub const armConst = enum(c_int) {
// ARM CPU
CPU_ARM_926 = 0,
CPU_ARM_946 = 1,
CPU_ARM_1026 = 2,
CPU_ARM_1136_R2 = 3,
CPU_ARM_1136 = 4,
CPU_ARM_1176 = 5,
CPU_ARM_11MPCORE = 6,
CPU_ARM_CORTEX_M0 = 7,
CPU_ARM_CORTEX_M3 = 8,
CPU_ARM_CORTEX_M4 = 9,
CPU_ARM_CORTEX_M7 = 10,
CPU_ARM_CORTEX_M33 = 11,
CPU_ARM_CORTEX_R5 = 12,
CPU_ARM_CORTEX_R5F = 13,
CPU_ARM_CORTEX_A7 = 14,
CPU_ARM_CORTEX_A8 = 15,
CPU_ARM_CORTEX_A9 = 16,
CPU_ARM_CORTEX_A15 = 17,
CPU_ARM_TI925T = 18,
CPU_ARM_SA1100 = 19,
CPU_ARM_SA1110 = 20,
CPU_ARM_PXA250 = 21,
CPU_ARM_PXA255 = 22,
CPU_ARM_PXA260 = 23,
CPU_ARM_PXA261 = 24,
CPU_ARM_PXA262 = 25,
CPU_ARM_PXA270 = 26,
CPU_ARM_PXA270A0 = 27,
CPU_ARM_PXA270A1 = 28,
CPU_ARM_PXA270B0 = 29,
CPU_ARM_PXA270B1 = 30,
CPU_ARM_PXA270C0 = 31,
CPU_ARM_PXA270C5 = 32,
CPU_ARM_MAX = 33,
CPU_ARM_ENDING = 34,
// ARM registers
ARM_REG_INVALID = 0,
ARM_REG_APSR = 1,
ARM_REG_APSR_NZCV = 2,
ARM_REG_CPSR = 3,
ARM_REG_FPEXC = 4,
ARM_REG_FPINST = 5,
ARM_REG_FPSCR = 6,
ARM_REG_FPSCR_NZCV = 7,
ARM_REG_FPSID = 8,
ARM_REG_ITSTATE = 9,
ARM_REG_LR = 10,
ARM_REG_PC = 11,
ARM_REG_SP = 12,
ARM_REG_SPSR = 13,
ARM_REG_D0 = 14,
ARM_REG_D1 = 15,
ARM_REG_D2 = 16,
ARM_REG_D3 = 17,
ARM_REG_D4 = 18,
ARM_REG_D5 = 19,
ARM_REG_D6 = 20,
ARM_REG_D7 = 21,
ARM_REG_D8 = 22,
ARM_REG_D9 = 23,
ARM_REG_D10 = 24,
ARM_REG_D11 = 25,
ARM_REG_D12 = 26,
ARM_REG_D13 = 27,
ARM_REG_D14 = 28,
ARM_REG_D15 = 29,
ARM_REG_D16 = 30,
ARM_REG_D17 = 31,
ARM_REG_D18 = 32,
ARM_REG_D19 = 33,
ARM_REG_D20 = 34,
ARM_REG_D21 = 35,
ARM_REG_D22 = 36,
ARM_REG_D23 = 37,
ARM_REG_D24 = 38,
ARM_REG_D25 = 39,
ARM_REG_D26 = 40,
ARM_REG_D27 = 41,
ARM_REG_D28 = 42,
ARM_REG_D29 = 43,
ARM_REG_D30 = 44,
ARM_REG_D31 = 45,
ARM_REG_FPINST2 = 46,
ARM_REG_MVFR0 = 47,
ARM_REG_MVFR1 = 48,
ARM_REG_MVFR2 = 49,
ARM_REG_Q0 = 50,
ARM_REG_Q1 = 51,
ARM_REG_Q2 = 52,
ARM_REG_Q3 = 53,
ARM_REG_Q4 = 54,
ARM_REG_Q5 = 55,
ARM_REG_Q6 = 56,
ARM_REG_Q7 = 57,
ARM_REG_Q8 = 58,
ARM_REG_Q9 = 59,
ARM_REG_Q10 = 60,
ARM_REG_Q11 = 61,
ARM_REG_Q12 = 62,
ARM_REG_Q13 = 63,
ARM_REG_Q14 = 64,
ARM_REG_Q15 = 65,
ARM_REG_R0 = 66,
ARM_REG_R1 = 67,
ARM_REG_R2 = 68,
ARM_REG_R3 = 69,
ARM_REG_R4 = 70,
ARM_REG_R5 = 71,
ARM_REG_R6 = 72,
ARM_REG_R7 = 73,
ARM_REG_R8 = 74,
ARM_REG_R9 = 75,
ARM_REG_R10 = 76,
ARM_REG_R11 = 77,
ARM_REG_R12 = 78,
ARM_REG_S0 = 79,
ARM_REG_S1 = 80,
ARM_REG_S2 = 81,
ARM_REG_S3 = 82,
ARM_REG_S4 = 83,
ARM_REG_S5 = 84,
ARM_REG_S6 = 85,
ARM_REG_S7 = 86,
ARM_REG_S8 = 87,
ARM_REG_S9 = 88,
ARM_REG_S10 = 89,
ARM_REG_S11 = 90,
ARM_REG_S12 = 91,
ARM_REG_S13 = 92,
ARM_REG_S14 = 93,
ARM_REG_S15 = 94,
ARM_REG_S16 = 95,
ARM_REG_S17 = 96,
ARM_REG_S18 = 97,
ARM_REG_S19 = 98,
ARM_REG_S20 = 99,
ARM_REG_S21 = 100,
ARM_REG_S22 = 101,
ARM_REG_S23 = 102,
ARM_REG_S24 = 103,
ARM_REG_S25 = 104,
ARM_REG_S26 = 105,
ARM_REG_S27 = 106,
ARM_REG_S28 = 107,
ARM_REG_S29 = 108,
ARM_REG_S30 = 109,
ARM_REG_S31 = 110,
ARM_REG_C1_C0_2 = 111,
ARM_REG_C13_C0_2 = 112,
ARM_REG_C13_C0_3 = 113,
ARM_REG_IPSR = 114,
ARM_REG_MSP = 115,
ARM_REG_PSP = 116,
ARM_REG_CONTROL = 117,
ARM_REG_IAPSR = 118,
ARM_REG_EAPSR = 119,
ARM_REG_XPSR = 120,
ARM_REG_EPSR = 121,
ARM_REG_IEPSR = 122,
ARM_REG_PRIMASK = 123,
ARM_REG_BASEPRI = 124,
ARM_REG_BASEPRI_MAX = 125,
ARM_REG_FAULTMASK = 126,
ARM_REG_APSR_NZCVQ = 127,
ARM_REG_APSR_G = 128,
ARM_REG_APSR_NZCVQG = 129,
ARM_REG_IAPSR_NZCVQ = 130,
ARM_REG_IAPSR_G = 131,
ARM_REG_IAPSR_NZCVQG = 132,
ARM_REG_EAPSR_NZCVQ = 133,
ARM_REG_EAPSR_G = 134,
ARM_REG_EAPSR_NZCVQG = 135,
ARM_REG_XPSR_NZCVQ = 136,
ARM_REG_XPSR_G = 137,
ARM_REG_XPSR_NZCVQG = 138,
ARM_REG_CP_REG = 139,
ARM_REG_ENDING = 140,
// alias registers
ARM_REG_R13 = 12,
ARM_REG_R14 = 10,
ARM_REG_R15 = 11,
ARM_REG_SB = 75,
ARM_REG_SL = 76,
ARM_REG_FP = 77,
ARM_REG_IP = 78,
};

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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
pub const m68kConst = enum(c_int) {
// M68K CPU
CPU_M68K_M5206 = 0,
CPU_M68K_M68000 = 1,
CPU_M68K_M68020 = 2,
CPU_M68K_M68030 = 3,
CPU_M68K_M68040 = 4,
CPU_M68K_M68060 = 5,
CPU_M68K_M5208 = 6,
CPU_M68K_CFV4E = 7,
CPU_M68K_ANY = 8,
CPU_M68K_ENDING = 9,
// M68K registers
M68K_REG_INVALID = 0,
M68K_REG_A0 = 1,
M68K_REG_A1 = 2,
M68K_REG_A2 = 3,
M68K_REG_A3 = 4,
M68K_REG_A4 = 5,
M68K_REG_A5 = 6,
M68K_REG_A6 = 7,
M68K_REG_A7 = 8,
M68K_REG_D0 = 9,
M68K_REG_D1 = 10,
M68K_REG_D2 = 11,
M68K_REG_D3 = 12,
M68K_REG_D4 = 13,
M68K_REG_D5 = 14,
M68K_REG_D6 = 15,
M68K_REG_D7 = 16,
M68K_REG_SR = 17,
M68K_REG_PC = 18,
M68K_REG_ENDING = 19,
};

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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
pub const mipsConst = enum(c_int) {
// MIPS32 CPUS
CPU_MIPS32_4KC = 0,
CPU_MIPS32_4KM = 1,
CPU_MIPS32_4KECR1 = 2,
CPU_MIPS32_4KEMR1 = 3,
CPU_MIPS32_4KEC = 4,
CPU_MIPS32_4KEM = 5,
CPU_MIPS32_24KC = 6,
CPU_MIPS32_24KEC = 7,
CPU_MIPS32_24KF = 8,
CPU_MIPS32_34KF = 9,
CPU_MIPS32_74KF = 10,
CPU_MIPS32_M14K = 11,
CPU_MIPS32_M14KC = 12,
CPU_MIPS32_P5600 = 13,
CPU_MIPS32_MIPS32R6_GENERIC = 14,
CPU_MIPS32_I7200 = 15,
CPU_MIPS32_ENDING = 16,
// MIPS64 CPUS
CPU_MIPS64_R4000 = 0,
CPU_MIPS64_VR5432 = 1,
CPU_MIPS64_5KC = 2,
CPU_MIPS64_5KF = 3,
CPU_MIPS64_20KC = 4,
CPU_MIPS64_MIPS64R2_GENERIC = 5,
CPU_MIPS64_5KEC = 6,
CPU_MIPS64_5KEF = 7,
CPU_MIPS64_I6400 = 8,
CPU_MIPS64_I6500 = 9,
CPU_MIPS64_LOONGSON_2E = 10,
CPU_MIPS64_LOONGSON_2F = 11,
CPU_MIPS64_MIPS64DSPR2 = 12,
CPU_MIPS64_ENDING = 13,
// MIPS registers
MIPS_REG_INVALID = 0,
// General purpose registers
MIPS_REG_PC = 1,
MIPS_REG_0 = 2,
MIPS_REG_1 = 3,
MIPS_REG_2 = 4,
MIPS_REG_3 = 5,
MIPS_REG_4 = 6,
MIPS_REG_5 = 7,
MIPS_REG_6 = 8,
MIPS_REG_7 = 9,
MIPS_REG_8 = 10,
MIPS_REG_9 = 11,
MIPS_REG_10 = 12,
MIPS_REG_11 = 13,
MIPS_REG_12 = 14,
MIPS_REG_13 = 15,
MIPS_REG_14 = 16,
MIPS_REG_15 = 17,
MIPS_REG_16 = 18,
MIPS_REG_17 = 19,
MIPS_REG_18 = 20,
MIPS_REG_19 = 21,
MIPS_REG_20 = 22,
MIPS_REG_21 = 23,
MIPS_REG_22 = 24,
MIPS_REG_23 = 25,
MIPS_REG_24 = 26,
MIPS_REG_25 = 27,
MIPS_REG_26 = 28,
MIPS_REG_27 = 29,
MIPS_REG_28 = 30,
MIPS_REG_29 = 31,
MIPS_REG_30 = 32,
MIPS_REG_31 = 33,
// DSP registers
MIPS_REG_DSPCCOND = 34,
MIPS_REG_DSPCARRY = 35,
MIPS_REG_DSPEFI = 36,
MIPS_REG_DSPOUTFLAG = 37,
MIPS_REG_DSPOUTFLAG16_19 = 38,
MIPS_REG_DSPOUTFLAG20 = 39,
MIPS_REG_DSPOUTFLAG21 = 40,
MIPS_REG_DSPOUTFLAG22 = 41,
MIPS_REG_DSPOUTFLAG23 = 42,
MIPS_REG_DSPPOS = 43,
MIPS_REG_DSPSCOUNT = 44,
// ACC registers
MIPS_REG_AC0 = 45,
MIPS_REG_AC1 = 46,
MIPS_REG_AC2 = 47,
MIPS_REG_AC3 = 48,
// COP registers
MIPS_REG_CC0 = 49,
MIPS_REG_CC1 = 50,
MIPS_REG_CC2 = 51,
MIPS_REG_CC3 = 52,
MIPS_REG_CC4 = 53,
MIPS_REG_CC5 = 54,
MIPS_REG_CC6 = 55,
MIPS_REG_CC7 = 56,
// FPU registers
MIPS_REG_F0 = 57,
MIPS_REG_F1 = 58,
MIPS_REG_F2 = 59,
MIPS_REG_F3 = 60,
MIPS_REG_F4 = 61,
MIPS_REG_F5 = 62,
MIPS_REG_F6 = 63,
MIPS_REG_F7 = 64,
MIPS_REG_F8 = 65,
MIPS_REG_F9 = 66,
MIPS_REG_F10 = 67,
MIPS_REG_F11 = 68,
MIPS_REG_F12 = 69,
MIPS_REG_F13 = 70,
MIPS_REG_F14 = 71,
MIPS_REG_F15 = 72,
MIPS_REG_F16 = 73,
MIPS_REG_F17 = 74,
MIPS_REG_F18 = 75,
MIPS_REG_F19 = 76,
MIPS_REG_F20 = 77,
MIPS_REG_F21 = 78,
MIPS_REG_F22 = 79,
MIPS_REG_F23 = 80,
MIPS_REG_F24 = 81,
MIPS_REG_F25 = 82,
MIPS_REG_F26 = 83,
MIPS_REG_F27 = 84,
MIPS_REG_F28 = 85,
MIPS_REG_F29 = 86,
MIPS_REG_F30 = 87,
MIPS_REG_F31 = 88,
MIPS_REG_FCC0 = 89,
MIPS_REG_FCC1 = 90,
MIPS_REG_FCC2 = 91,
MIPS_REG_FCC3 = 92,
MIPS_REG_FCC4 = 93,
MIPS_REG_FCC5 = 94,
MIPS_REG_FCC6 = 95,
MIPS_REG_FCC7 = 96,
// AFPR128
MIPS_REG_W0 = 97,
MIPS_REG_W1 = 98,
MIPS_REG_W2 = 99,
MIPS_REG_W3 = 100,
MIPS_REG_W4 = 101,
MIPS_REG_W5 = 102,
MIPS_REG_W6 = 103,
MIPS_REG_W7 = 104,
MIPS_REG_W8 = 105,
MIPS_REG_W9 = 106,
MIPS_REG_W10 = 107,
MIPS_REG_W11 = 108,
MIPS_REG_W12 = 109,
MIPS_REG_W13 = 110,
MIPS_REG_W14 = 111,
MIPS_REG_W15 = 112,
MIPS_REG_W16 = 113,
MIPS_REG_W17 = 114,
MIPS_REG_W18 = 115,
MIPS_REG_W19 = 116,
MIPS_REG_W20 = 117,
MIPS_REG_W21 = 118,
MIPS_REG_W22 = 119,
MIPS_REG_W23 = 120,
MIPS_REG_W24 = 121,
MIPS_REG_W25 = 122,
MIPS_REG_W26 = 123,
MIPS_REG_W27 = 124,
MIPS_REG_W28 = 125,
MIPS_REG_W29 = 126,
MIPS_REG_W30 = 127,
MIPS_REG_W31 = 128,
MIPS_REG_HI = 129,
MIPS_REG_LO = 130,
MIPS_REG_P0 = 131,
MIPS_REG_P1 = 132,
MIPS_REG_P2 = 133,
MIPS_REG_MPL0 = 134,
MIPS_REG_MPL1 = 135,
MIPS_REG_MPL2 = 136,
MIPS_REG_CP0_CONFIG3 = 137,
MIPS_REG_CP0_USERLOCAL = 138,
MIPS_REG_CP0_STATUS = 139,
MIPS_REG_ENDING = 140,
MIPS_REG_ZERO = 2,
MIPS_REG_AT = 3,
MIPS_REG_V0 = 4,
MIPS_REG_V1 = 5,
MIPS_REG_A0 = 6,
MIPS_REG_A1 = 7,
MIPS_REG_A2 = 8,
MIPS_REG_A3 = 9,
MIPS_REG_T0 = 10,
MIPS_REG_T1 = 11,
MIPS_REG_T2 = 12,
MIPS_REG_T3 = 13,
MIPS_REG_T4 = 14,
MIPS_REG_T5 = 15,
MIPS_REG_T6 = 16,
MIPS_REG_T7 = 17,
MIPS_REG_S0 = 18,
MIPS_REG_S1 = 19,
MIPS_REG_S2 = 20,
MIPS_REG_S3 = 21,
MIPS_REG_S4 = 22,
MIPS_REG_S5 = 23,
MIPS_REG_S6 = 24,
MIPS_REG_S7 = 25,
MIPS_REG_T8 = 26,
MIPS_REG_T9 = 27,
MIPS_REG_K0 = 28,
MIPS_REG_K1 = 29,
MIPS_REG_GP = 30,
MIPS_REG_SP = 31,
MIPS_REG_FP = 32,
MIPS_REG_S8 = 32,
MIPS_REG_RA = 33,
MIPS_REG_HI0 = 45,
MIPS_REG_HI1 = 46,
MIPS_REG_HI2 = 47,
MIPS_REG_HI3 = 48,
MIPS_REG_LO0 = 45,
MIPS_REG_LO1 = 46,
MIPS_REG_LO2 = 47,
MIPS_REG_LO3 = 48,
};

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bindings/zig/unicorn/ppc_const.zig Normal file
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@ -0,0 +1,408 @@
// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
pub const ppcConst = enum(c_int) {
// PPC CPU
CPU_PPC32_401 = 0,
CPU_PPC32_401A1 = 1,
CPU_PPC32_401B2 = 2,
CPU_PPC32_401C2 = 3,
CPU_PPC32_401D2 = 4,
CPU_PPC32_401E2 = 5,
CPU_PPC32_401F2 = 6,
CPU_PPC32_401G2 = 7,
CPU_PPC32_IOP480 = 8,
CPU_PPC32_COBRA = 9,
CPU_PPC32_403GA = 10,
CPU_PPC32_403GB = 11,
CPU_PPC32_403GC = 12,
CPU_PPC32_403GCX = 13,
CPU_PPC32_405D2 = 14,
CPU_PPC32_405D4 = 15,
CPU_PPC32_405CRA = 16,
CPU_PPC32_405CRB = 17,
CPU_PPC32_405CRC = 18,
CPU_PPC32_405EP = 19,
CPU_PPC32_405EZ = 20,
CPU_PPC32_405GPA = 21,
CPU_PPC32_405GPB = 22,
CPU_PPC32_405GPC = 23,
CPU_PPC32_405GPD = 24,
CPU_PPC32_405GPR = 25,
CPU_PPC32_405LP = 26,
CPU_PPC32_NPE405H = 27,
CPU_PPC32_NPE405H2 = 28,
CPU_PPC32_NPE405L = 29,
CPU_PPC32_NPE4GS3 = 30,
CPU_PPC32_STB03 = 31,
CPU_PPC32_STB04 = 32,
CPU_PPC32_STB25 = 33,
CPU_PPC32_X2VP4 = 34,
CPU_PPC32_X2VP20 = 35,
CPU_PPC32_440_XILINX = 36,
CPU_PPC32_440_XILINX_W_DFPU = 37,
CPU_PPC32_440EPA = 38,
CPU_PPC32_440EPB = 39,
CPU_PPC32_440EPX = 40,
CPU_PPC32_460EXB = 41,
CPU_PPC32_G2 = 42,
CPU_PPC32_G2H4 = 43,
CPU_PPC32_G2GP = 44,
CPU_PPC32_G2LS = 45,
CPU_PPC32_G2HIP3 = 46,
CPU_PPC32_G2HIP4 = 47,
CPU_PPC32_MPC603 = 48,
CPU_PPC32_G2LE = 49,
CPU_PPC32_G2LEGP = 50,
CPU_PPC32_G2LELS = 51,
CPU_PPC32_G2LEGP1 = 52,
CPU_PPC32_G2LEGP3 = 53,
CPU_PPC32_MPC5200_V10 = 54,
CPU_PPC32_MPC5200_V11 = 55,
CPU_PPC32_MPC5200_V12 = 56,
CPU_PPC32_MPC5200B_V20 = 57,
CPU_PPC32_MPC5200B_V21 = 58,
CPU_PPC32_E200Z5 = 59,
CPU_PPC32_E200Z6 = 60,
CPU_PPC32_E300C1 = 61,
CPU_PPC32_E300C2 = 62,
CPU_PPC32_E300C3 = 63,
CPU_PPC32_E300C4 = 64,
CPU_PPC32_MPC8343 = 65,
CPU_PPC32_MPC8343A = 66,
CPU_PPC32_MPC8343E = 67,
CPU_PPC32_MPC8343EA = 68,
CPU_PPC32_MPC8347T = 69,
CPU_PPC32_MPC8347P = 70,
CPU_PPC32_MPC8347AT = 71,
CPU_PPC32_MPC8347AP = 72,
CPU_PPC32_MPC8347ET = 73,
CPU_PPC32_MPC8347EP = 74,
CPU_PPC32_MPC8347EAT = 75,
CPU_PPC32_MPC8347EAP = 76,
CPU_PPC32_MPC8349 = 77,
CPU_PPC32_MPC8349A = 78,
CPU_PPC32_MPC8349E = 79,
CPU_PPC32_MPC8349EA = 80,
CPU_PPC32_MPC8377 = 81,
CPU_PPC32_MPC8377E = 82,
CPU_PPC32_MPC8378 = 83,
CPU_PPC32_MPC8378E = 84,
CPU_PPC32_MPC8379 = 85,
CPU_PPC32_MPC8379E = 86,
CPU_PPC32_E500_V10 = 87,
CPU_PPC32_E500_V20 = 88,
CPU_PPC32_E500V2_V10 = 89,
CPU_PPC32_E500V2_V20 = 90,
CPU_PPC32_E500V2_V21 = 91,
CPU_PPC32_E500V2_V22 = 92,
CPU_PPC32_E500V2_V30 = 93,
CPU_PPC32_E500MC = 94,
CPU_PPC32_MPC8533_V10 = 95,
CPU_PPC32_MPC8533_V11 = 96,
CPU_PPC32_MPC8533E_V10 = 97,
CPU_PPC32_MPC8533E_V11 = 98,
CPU_PPC32_MPC8540_V10 = 99,
CPU_PPC32_MPC8540_V20 = 100,
CPU_PPC32_MPC8540_V21 = 101,
CPU_PPC32_MPC8541_V10 = 102,
CPU_PPC32_MPC8541_V11 = 103,
CPU_PPC32_MPC8541E_V10 = 104,
CPU_PPC32_MPC8541E_V11 = 105,
CPU_PPC32_MPC8543_V10 = 106,
CPU_PPC32_MPC8543_V11 = 107,
CPU_PPC32_MPC8543_V20 = 108,
CPU_PPC32_MPC8543_V21 = 109,
CPU_PPC32_MPC8543E_V10 = 110,
CPU_PPC32_MPC8543E_V11 = 111,
CPU_PPC32_MPC8543E_V20 = 112,
CPU_PPC32_MPC8543E_V21 = 113,
CPU_PPC32_MPC8544_V10 = 114,
CPU_PPC32_MPC8544_V11 = 115,
CPU_PPC32_MPC8544E_V10 = 116,
CPU_PPC32_MPC8544E_V11 = 117,
CPU_PPC32_MPC8545_V20 = 118,
CPU_PPC32_MPC8545_V21 = 119,
CPU_PPC32_MPC8545E_V20 = 120,
CPU_PPC32_MPC8545E_V21 = 121,
CPU_PPC32_MPC8547E_V20 = 122,
CPU_PPC32_MPC8547E_V21 = 123,
CPU_PPC32_MPC8548_V10 = 124,
CPU_PPC32_MPC8548_V11 = 125,
CPU_PPC32_MPC8548_V20 = 126,
CPU_PPC32_MPC8548_V21 = 127,
CPU_PPC32_MPC8548E_V10 = 128,
CPU_PPC32_MPC8548E_V11 = 129,
CPU_PPC32_MPC8548E_V20 = 130,
CPU_PPC32_MPC8548E_V21 = 131,
CPU_PPC32_MPC8555_V10 = 132,
CPU_PPC32_MPC8555_V11 = 133,
CPU_PPC32_MPC8555E_V10 = 134,
CPU_PPC32_MPC8555E_V11 = 135,
CPU_PPC32_MPC8560_V10 = 136,
CPU_PPC32_MPC8560_V20 = 137,
CPU_PPC32_MPC8560_V21 = 138,
CPU_PPC32_MPC8567 = 139,
CPU_PPC32_MPC8567E = 140,
CPU_PPC32_MPC8568 = 141,
CPU_PPC32_MPC8568E = 142,
CPU_PPC32_MPC8572 = 143,
CPU_PPC32_MPC8572E = 144,
CPU_PPC32_E600 = 145,
CPU_PPC32_MPC8610 = 146,
CPU_PPC32_MPC8641 = 147,
CPU_PPC32_MPC8641D = 148,
CPU_PPC32_601_V0 = 149,
CPU_PPC32_601_V1 = 150,
CPU_PPC32_601_V2 = 151,
CPU_PPC32_602 = 152,
CPU_PPC32_603 = 153,
CPU_PPC32_603E_V1_1 = 154,
CPU_PPC32_603E_V1_2 = 155,
CPU_PPC32_603E_V1_3 = 156,
CPU_PPC32_603E_V1_4 = 157,
CPU_PPC32_603E_V2_2 = 158,
CPU_PPC32_603E_V3 = 159,
CPU_PPC32_603E_V4 = 160,
CPU_PPC32_603E_V4_1 = 161,
CPU_PPC32_603E7 = 162,
CPU_PPC32_603E7T = 163,
CPU_PPC32_603E7V = 164,
CPU_PPC32_603E7V1 = 165,
CPU_PPC32_603E7V2 = 166,
CPU_PPC32_603P = 167,
CPU_PPC32_604 = 168,
CPU_PPC32_604E_V1_0 = 169,
CPU_PPC32_604E_V2_2 = 170,
CPU_PPC32_604E_V2_4 = 171,
CPU_PPC32_604R = 172,
CPU_PPC32_740_V1_0 = 173,
CPU_PPC32_750_V1_0 = 174,
CPU_PPC32_740_V2_0 = 175,
CPU_PPC32_750_V2_0 = 176,
CPU_PPC32_740_V2_1 = 177,
CPU_PPC32_750_V2_1 = 178,
CPU_PPC32_740_V2_2 = 179,
CPU_PPC32_750_V2_2 = 180,
CPU_PPC32_740_V3_0 = 181,
CPU_PPC32_750_V3_0 = 182,
CPU_PPC32_740_V3_1 = 183,
CPU_PPC32_750_V3_1 = 184,
CPU_PPC32_740E = 185,
CPU_PPC32_750E = 186,
CPU_PPC32_740P = 187,
CPU_PPC32_750P = 188,
CPU_PPC32_750CL_V1_0 = 189,
CPU_PPC32_750CL_V2_0 = 190,
CPU_PPC32_750CX_V1_0 = 191,
CPU_PPC32_750CX_V2_0 = 192,
CPU_PPC32_750CX_V2_1 = 193,
CPU_PPC32_750CX_V2_2 = 194,
CPU_PPC32_750CXE_V2_1 = 195,
CPU_PPC32_750CXE_V2_2 = 196,
CPU_PPC32_750CXE_V2_3 = 197,
CPU_PPC32_750CXE_V2_4 = 198,
CPU_PPC32_750CXE_V2_4B = 199,
CPU_PPC32_750CXE_V3_0 = 200,
CPU_PPC32_750CXE_V3_1 = 201,
CPU_PPC32_750CXE_V3_1B = 202,
CPU_PPC32_750CXR = 203,
CPU_PPC32_750FL = 204,
CPU_PPC32_750FX_V1_0 = 205,
CPU_PPC32_750FX_V2_0 = 206,
CPU_PPC32_750FX_V2_1 = 207,
CPU_PPC32_750FX_V2_2 = 208,
CPU_PPC32_750FX_V2_3 = 209,
CPU_PPC32_750GL = 210,
CPU_PPC32_750GX_V1_0 = 211,
CPU_PPC32_750GX_V1_1 = 212,
CPU_PPC32_750GX_V1_2 = 213,
CPU_PPC32_750L_V2_0 = 214,
CPU_PPC32_750L_V2_1 = 215,
CPU_PPC32_750L_V2_2 = 216,
CPU_PPC32_750L_V3_0 = 217,
CPU_PPC32_750L_V3_2 = 218,
CPU_PPC32_745_V1_0 = 219,
CPU_PPC32_755_V1_0 = 220,
CPU_PPC32_745_V1_1 = 221,
CPU_PPC32_755_V1_1 = 222,
CPU_PPC32_745_V2_0 = 223,
CPU_PPC32_755_V2_0 = 224,
CPU_PPC32_745_V2_1 = 225,
CPU_PPC32_755_V2_1 = 226,
CPU_PPC32_745_V2_2 = 227,
CPU_PPC32_755_V2_2 = 228,
CPU_PPC32_745_V2_3 = 229,
CPU_PPC32_755_V2_3 = 230,
CPU_PPC32_745_V2_4 = 231,
CPU_PPC32_755_V2_4 = 232,
CPU_PPC32_745_V2_5 = 233,
CPU_PPC32_755_V2_5 = 234,
CPU_PPC32_745_V2_6 = 235,
CPU_PPC32_755_V2_6 = 236,
CPU_PPC32_745_V2_7 = 237,
CPU_PPC32_755_V2_7 = 238,
CPU_PPC32_745_V2_8 = 239,
CPU_PPC32_755_V2_8 = 240,
CPU_PPC32_7400_V1_0 = 241,
CPU_PPC32_7400_V1_1 = 242,
CPU_PPC32_7400_V2_0 = 243,
CPU_PPC32_7400_V2_1 = 244,
CPU_PPC32_7400_V2_2 = 245,
CPU_PPC32_7400_V2_6 = 246,
CPU_PPC32_7400_V2_7 = 247,
CPU_PPC32_7400_V2_8 = 248,
CPU_PPC32_7400_V2_9 = 249,
CPU_PPC32_7410_V1_0 = 250,
CPU_PPC32_7410_V1_1 = 251,
CPU_PPC32_7410_V1_2 = 252,
CPU_PPC32_7410_V1_3 = 253,
CPU_PPC32_7410_V1_4 = 254,
CPU_PPC32_7448_V1_0 = 255,
CPU_PPC32_7448_V1_1 = 256,
CPU_PPC32_7448_V2_0 = 257,
CPU_PPC32_7448_V2_1 = 258,
CPU_PPC32_7450_V1_0 = 259,
CPU_PPC32_7450_V1_1 = 260,
CPU_PPC32_7450_V1_2 = 261,
CPU_PPC32_7450_V2_0 = 262,
CPU_PPC32_7450_V2_1 = 263,
CPU_PPC32_7441_V2_1 = 264,
CPU_PPC32_7441_V2_3 = 265,
CPU_PPC32_7451_V2_3 = 266,
CPU_PPC32_7441_V2_10 = 267,
CPU_PPC32_7451_V2_10 = 268,
CPU_PPC32_7445_V1_0 = 269,
CPU_PPC32_7455_V1_0 = 270,
CPU_PPC32_7445_V2_1 = 271,
CPU_PPC32_7455_V2_1 = 272,
CPU_PPC32_7445_V3_2 = 273,
CPU_PPC32_7455_V3_2 = 274,
CPU_PPC32_7445_V3_3 = 275,
CPU_PPC32_7455_V3_3 = 276,
CPU_PPC32_7445_V3_4 = 277,
CPU_PPC32_7455_V3_4 = 278,
CPU_PPC32_7447_V1_0 = 279,
CPU_PPC32_7457_V1_0 = 280,
CPU_PPC32_7447_V1_1 = 281,
CPU_PPC32_7457_V1_1 = 282,
CPU_PPC32_7457_V1_2 = 283,
CPU_PPC32_7447A_V1_0 = 284,
CPU_PPC32_7457A_V1_0 = 285,
CPU_PPC32_7447A_V1_1 = 286,
CPU_PPC32_7457A_V1_1 = 287,
CPU_PPC32_7447A_V1_2 = 288,
CPU_PPC32_7457A_V1_2 = 289,
CPU_PPC32_ENDING = 290,
// PPC64 CPU
CPU_PPC64_E5500 = 0,
CPU_PPC64_E6500 = 1,
CPU_PPC64_970_V2_2 = 2,
CPU_PPC64_970FX_V1_0 = 3,
CPU_PPC64_970FX_V2_0 = 4,
CPU_PPC64_970FX_V2_1 = 5,
CPU_PPC64_970FX_V3_0 = 6,
CPU_PPC64_970FX_V3_1 = 7,
CPU_PPC64_970MP_V1_0 = 8,
CPU_PPC64_970MP_V1_1 = 9,
CPU_PPC64_POWER5_V2_1 = 10,
CPU_PPC64_POWER7_V2_3 = 11,
CPU_PPC64_POWER7_V2_1 = 12,
CPU_PPC64_POWER8E_V2_1 = 13,
CPU_PPC64_POWER8_V2_0 = 14,
CPU_PPC64_POWER8NVL_V1_0 = 15,
CPU_PPC64_POWER9_V1_0 = 16,
CPU_PPC64_POWER9_V2_0 = 17,
CPU_PPC64_POWER10_V1_0 = 18,
CPU_PPC64_ENDING = 19,
// PPC registers
PPC_REG_INVALID = 0,
// General purpose registers
PPC_REG_PC = 1,
PPC_REG_0 = 2,
PPC_REG_1 = 3,
PPC_REG_2 = 4,
PPC_REG_3 = 5,
PPC_REG_4 = 6,
PPC_REG_5 = 7,
PPC_REG_6 = 8,
PPC_REG_7 = 9,
PPC_REG_8 = 10,
PPC_REG_9 = 11,
PPC_REG_10 = 12,
PPC_REG_11 = 13,
PPC_REG_12 = 14,
PPC_REG_13 = 15,
PPC_REG_14 = 16,
PPC_REG_15 = 17,
PPC_REG_16 = 18,
PPC_REG_17 = 19,
PPC_REG_18 = 20,
PPC_REG_19 = 21,
PPC_REG_20 = 22,
PPC_REG_21 = 23,
PPC_REG_22 = 24,
PPC_REG_23 = 25,
PPC_REG_24 = 26,
PPC_REG_25 = 27,
PPC_REG_26 = 28,
PPC_REG_27 = 29,
PPC_REG_28 = 30,
PPC_REG_29 = 31,
PPC_REG_30 = 32,
PPC_REG_31 = 33,
PPC_REG_CR0 = 34,
PPC_REG_CR1 = 35,
PPC_REG_CR2 = 36,
PPC_REG_CR3 = 37,
PPC_REG_CR4 = 38,
PPC_REG_CR5 = 39,
PPC_REG_CR6 = 40,
PPC_REG_CR7 = 41,
PPC_REG_FPR0 = 42,
PPC_REG_FPR1 = 43,
PPC_REG_FPR2 = 44,
PPC_REG_FPR3 = 45,
PPC_REG_FPR4 = 46,
PPC_REG_FPR5 = 47,
PPC_REG_FPR6 = 48,
PPC_REG_FPR7 = 49,
PPC_REG_FPR8 = 50,
PPC_REG_FPR9 = 51,
PPC_REG_FPR10 = 52,
PPC_REG_FPR11 = 53,
PPC_REG_FPR12 = 54,
PPC_REG_FPR13 = 55,
PPC_REG_FPR14 = 56,
PPC_REG_FPR15 = 57,
PPC_REG_FPR16 = 58,
PPC_REG_FPR17 = 59,
PPC_REG_FPR18 = 60,
PPC_REG_FPR19 = 61,
PPC_REG_FPR20 = 62,
PPC_REG_FPR21 = 63,
PPC_REG_FPR22 = 64,
PPC_REG_FPR23 = 65,
PPC_REG_FPR24 = 66,
PPC_REG_FPR25 = 67,
PPC_REG_FPR26 = 68,
PPC_REG_FPR27 = 69,
PPC_REG_FPR28 = 70,
PPC_REG_FPR29 = 71,
PPC_REG_FPR30 = 72,
PPC_REG_FPR31 = 73,
PPC_REG_LR = 74,
PPC_REG_XER = 75,
PPC_REG_CTR = 76,
PPC_REG_MSR = 77,
PPC_REG_FPSCR = 78,
PPC_REG_CR = 79,
PPC_REG_ENDING = 80,
};

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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
pub const riscvConst = enum(c_int) {
// RISCV32 CPU
CPU_RISCV32_ANY = 0,
CPU_RISCV32_BASE32 = 1,
CPU_RISCV32_SIFIVE_E31 = 2,
CPU_RISCV32_SIFIVE_U34 = 3,
CPU_RISCV32_ENDING = 4,
// RISCV64 CPU
CPU_RISCV64_ANY = 0,
CPU_RISCV64_BASE64 = 1,
CPU_RISCV64_SIFIVE_E51 = 2,
CPU_RISCV64_SIFIVE_U54 = 3,
CPU_RISCV64_ENDING = 4,
// RISCV registers
RISCV_REG_INVALID = 0,
// General purpose registers
RISCV_REG_X0 = 1,
RISCV_REG_X1 = 2,
RISCV_REG_X2 = 3,
RISCV_REG_X3 = 4,
RISCV_REG_X4 = 5,
RISCV_REG_X5 = 6,
RISCV_REG_X6 = 7,
RISCV_REG_X7 = 8,
RISCV_REG_X8 = 9,
RISCV_REG_X9 = 10,
RISCV_REG_X10 = 11,
RISCV_REG_X11 = 12,
RISCV_REG_X12 = 13,
RISCV_REG_X13 = 14,
RISCV_REG_X14 = 15,
RISCV_REG_X15 = 16,
RISCV_REG_X16 = 17,
RISCV_REG_X17 = 18,
RISCV_REG_X18 = 19,
RISCV_REG_X19 = 20,
RISCV_REG_X20 = 21,
RISCV_REG_X21 = 22,
RISCV_REG_X22 = 23,
RISCV_REG_X23 = 24,
RISCV_REG_X24 = 25,
RISCV_REG_X25 = 26,
RISCV_REG_X26 = 27,
RISCV_REG_X27 = 28,
RISCV_REG_X28 = 29,
RISCV_REG_X29 = 30,
RISCV_REG_X30 = 31,
RISCV_REG_X31 = 32,
// RISCV CSR
RISCV_REG_USTATUS = 33,
RISCV_REG_UIE = 34,
RISCV_REG_UTVEC = 35,
RISCV_REG_USCRATCH = 36,
RISCV_REG_UEPC = 37,
RISCV_REG_UCAUSE = 38,
RISCV_REG_UTVAL = 39,
RISCV_REG_UIP = 40,
RISCV_REG_FFLAGS = 41,
RISCV_REG_FRM = 42,
RISCV_REG_FCSR = 43,
RISCV_REG_CYCLE = 44,
RISCV_REG_TIME = 45,
RISCV_REG_INSTRET = 46,
RISCV_REG_HPMCOUNTER3 = 47,
RISCV_REG_HPMCOUNTER4 = 48,
RISCV_REG_HPMCOUNTER5 = 49,
RISCV_REG_HPMCOUNTER6 = 50,
RISCV_REG_HPMCOUNTER7 = 51,
RISCV_REG_HPMCOUNTER8 = 52,
RISCV_REG_HPMCOUNTER9 = 53,
RISCV_REG_HPMCOUNTER10 = 54,
RISCV_REG_HPMCOUNTER11 = 55,
RISCV_REG_HPMCOUNTER12 = 56,
RISCV_REG_HPMCOUNTER13 = 57,
RISCV_REG_HPMCOUNTER14 = 58,
RISCV_REG_HPMCOUNTER15 = 59,
RISCV_REG_HPMCOUNTER16 = 60,
RISCV_REG_HPMCOUNTER17 = 61,
RISCV_REG_HPMCOUNTER18 = 62,
RISCV_REG_HPMCOUNTER19 = 63,
RISCV_REG_HPMCOUNTER20 = 64,
RISCV_REG_HPMCOUNTER21 = 65,
RISCV_REG_HPMCOUNTER22 = 66,
RISCV_REG_HPMCOUNTER23 = 67,
RISCV_REG_HPMCOUNTER24 = 68,
RISCV_REG_HPMCOUNTER25 = 69,
RISCV_REG_HPMCOUNTER26 = 70,
RISCV_REG_HPMCOUNTER27 = 71,
RISCV_REG_HPMCOUNTER28 = 72,
RISCV_REG_HPMCOUNTER29 = 73,
RISCV_REG_HPMCOUNTER30 = 74,
RISCV_REG_HPMCOUNTER31 = 75,
RISCV_REG_CYCLEH = 76,
RISCV_REG_TIMEH = 77,
RISCV_REG_INSTRETH = 78,
RISCV_REG_HPMCOUNTER3H = 79,
RISCV_REG_HPMCOUNTER4H = 80,
RISCV_REG_HPMCOUNTER5H = 81,
RISCV_REG_HPMCOUNTER6H = 82,
RISCV_REG_HPMCOUNTER7H = 83,
RISCV_REG_HPMCOUNTER8H = 84,
RISCV_REG_HPMCOUNTER9H = 85,
RISCV_REG_HPMCOUNTER10H = 86,
RISCV_REG_HPMCOUNTER11H = 87,
RISCV_REG_HPMCOUNTER12H = 88,
RISCV_REG_HPMCOUNTER13H = 89,
RISCV_REG_HPMCOUNTER14H = 90,
RISCV_REG_HPMCOUNTER15H = 91,
RISCV_REG_HPMCOUNTER16H = 92,
RISCV_REG_HPMCOUNTER17H = 93,
RISCV_REG_HPMCOUNTER18H = 94,
RISCV_REG_HPMCOUNTER19H = 95,
RISCV_REG_HPMCOUNTER20H = 96,
RISCV_REG_HPMCOUNTER21H = 97,
RISCV_REG_HPMCOUNTER22H = 98,
RISCV_REG_HPMCOUNTER23H = 99,
RISCV_REG_HPMCOUNTER24H = 100,
RISCV_REG_HPMCOUNTER25H = 101,
RISCV_REG_HPMCOUNTER26H = 102,
RISCV_REG_HPMCOUNTER27H = 103,
RISCV_REG_HPMCOUNTER28H = 104,
RISCV_REG_HPMCOUNTER29H = 105,
RISCV_REG_HPMCOUNTER30H = 106,
RISCV_REG_HPMCOUNTER31H = 107,
RISCV_REG_MCYCLE = 108,
RISCV_REG_MINSTRET = 109,
RISCV_REG_MCYCLEH = 110,
RISCV_REG_MINSTRETH = 111,
RISCV_REG_MVENDORID = 112,
RISCV_REG_MARCHID = 113,
RISCV_REG_MIMPID = 114,
RISCV_REG_MHARTID = 115,
RISCV_REG_MSTATUS = 116,
RISCV_REG_MISA = 117,
RISCV_REG_MEDELEG = 118,
RISCV_REG_MIDELEG = 119,
RISCV_REG_MIE = 120,
RISCV_REG_MTVEC = 121,
RISCV_REG_MCOUNTEREN = 122,
RISCV_REG_MSTATUSH = 123,
RISCV_REG_MUCOUNTEREN = 124,
RISCV_REG_MSCOUNTEREN = 125,
RISCV_REG_MHCOUNTEREN = 126,
RISCV_REG_MSCRATCH = 127,
RISCV_REG_MEPC = 128,
RISCV_REG_MCAUSE = 129,
RISCV_REG_MTVAL = 130,
RISCV_REG_MIP = 131,
RISCV_REG_MBADADDR = 132,
RISCV_REG_SSTATUS = 133,
RISCV_REG_SEDELEG = 134,
RISCV_REG_SIDELEG = 135,
RISCV_REG_SIE = 136,
RISCV_REG_STVEC = 137,
RISCV_REG_SCOUNTEREN = 138,
RISCV_REG_SSCRATCH = 139,
RISCV_REG_SEPC = 140,
RISCV_REG_SCAUSE = 141,
RISCV_REG_STVAL = 142,
RISCV_REG_SIP = 143,
RISCV_REG_SBADADDR = 144,
RISCV_REG_SPTBR = 145,
RISCV_REG_SATP = 146,
RISCV_REG_HSTATUS = 147,
RISCV_REG_HEDELEG = 148,
RISCV_REG_HIDELEG = 149,
RISCV_REG_HIE = 150,
RISCV_REG_HCOUNTEREN = 151,
RISCV_REG_HTVAL = 152,
RISCV_REG_HIP = 153,
RISCV_REG_HTINST = 154,
RISCV_REG_HGATP = 155,
RISCV_REG_HTIMEDELTA = 156,
RISCV_REG_HTIMEDELTAH = 157,
// Floating-point registers
RISCV_REG_F0 = 158,
RISCV_REG_F1 = 159,
RISCV_REG_F2 = 160,
RISCV_REG_F3 = 161,
RISCV_REG_F4 = 162,
RISCV_REG_F5 = 163,
RISCV_REG_F6 = 164,
RISCV_REG_F7 = 165,
RISCV_REG_F8 = 166,
RISCV_REG_F9 = 167,
RISCV_REG_F10 = 168,
RISCV_REG_F11 = 169,
RISCV_REG_F12 = 170,
RISCV_REG_F13 = 171,
RISCV_REG_F14 = 172,
RISCV_REG_F15 = 173,
RISCV_REG_F16 = 174,
RISCV_REG_F17 = 175,
RISCV_REG_F18 = 176,
RISCV_REG_F19 = 177,
RISCV_REG_F20 = 178,
RISCV_REG_F21 = 179,
RISCV_REG_F22 = 180,
RISCV_REG_F23 = 181,
RISCV_REG_F24 = 182,
RISCV_REG_F25 = 183,
RISCV_REG_F26 = 184,
RISCV_REG_F27 = 185,
RISCV_REG_F28 = 186,
RISCV_REG_F29 = 187,
RISCV_REG_F30 = 188,
RISCV_REG_F31 = 189,
RISCV_REG_PC = 190,
RISCV_REG_ENDING = 191,
// Alias registers
RISCV_REG_ZERO = 1,
RISCV_REG_RA = 2,
RISCV_REG_SP = 3,
RISCV_REG_GP = 4,
RISCV_REG_TP = 5,
RISCV_REG_T0 = 6,
RISCV_REG_T1 = 7,
RISCV_REG_T2 = 8,
RISCV_REG_S0 = 9,
RISCV_REG_FP = 9,
RISCV_REG_S1 = 10,
RISCV_REG_A0 = 11,
RISCV_REG_A1 = 12,
RISCV_REG_A2 = 13,
RISCV_REG_A3 = 14,
RISCV_REG_A4 = 15,
RISCV_REG_A5 = 16,
RISCV_REG_A6 = 17,
RISCV_REG_A7 = 18,
RISCV_REG_S2 = 19,
RISCV_REG_S3 = 20,
RISCV_REG_S4 = 21,
RISCV_REG_S5 = 22,
RISCV_REG_S6 = 23,
RISCV_REG_S7 = 24,
RISCV_REG_S8 = 25,
RISCV_REG_S9 = 26,
RISCV_REG_S10 = 27,
RISCV_REG_S11 = 28,
RISCV_REG_T3 = 29,
RISCV_REG_T4 = 30,
RISCV_REG_T5 = 31,
RISCV_REG_T6 = 32,
RISCV_REG_FT0 = 158,
RISCV_REG_FT1 = 159,
RISCV_REG_FT2 = 160,
RISCV_REG_FT3 = 161,
RISCV_REG_FT4 = 162,
RISCV_REG_FT5 = 163,
RISCV_REG_FT6 = 164,
RISCV_REG_FT7 = 165,
RISCV_REG_FS0 = 166,
RISCV_REG_FS1 = 167,
RISCV_REG_FA0 = 168,
RISCV_REG_FA1 = 169,
RISCV_REG_FA2 = 170,
RISCV_REG_FA3 = 171,
RISCV_REG_FA4 = 172,
RISCV_REG_FA5 = 173,
RISCV_REG_FA6 = 174,
RISCV_REG_FA7 = 175,
RISCV_REG_FS2 = 176,
RISCV_REG_FS3 = 177,
RISCV_REG_FS4 = 178,
RISCV_REG_FS5 = 179,
RISCV_REG_FS6 = 180,
RISCV_REG_FS7 = 181,
RISCV_REG_FS8 = 182,
RISCV_REG_FS9 = 183,
RISCV_REG_FS10 = 184,
RISCV_REG_FS11 = 185,
RISCV_REG_FT8 = 186,
RISCV_REG_FT9 = 187,
RISCV_REG_FT10 = 188,
RISCV_REG_FT11 = 189,
};

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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
pub const s390xConst = enum(c_int) {
// S390X CPU
CPU_S390X_Z900 = 0,
CPU_S390X_Z900_2 = 1,
CPU_S390X_Z900_3 = 2,
CPU_S390X_Z800 = 3,
CPU_S390X_Z990 = 4,
CPU_S390X_Z990_2 = 5,
CPU_S390X_Z990_3 = 6,
CPU_S390X_Z890 = 7,
CPU_S390X_Z990_4 = 8,
CPU_S390X_Z890_2 = 9,
CPU_S390X_Z990_5 = 10,
CPU_S390X_Z890_3 = 11,
CPU_S390X_Z9EC = 12,
CPU_S390X_Z9EC_2 = 13,
CPU_S390X_Z9BC = 14,
CPU_S390X_Z9EC_3 = 15,
CPU_S390X_Z9BC_2 = 16,
CPU_S390X_Z10EC = 17,
CPU_S390X_Z10EC_2 = 18,
CPU_S390X_Z10BC = 19,
CPU_S390X_Z10EC_3 = 20,
CPU_S390X_Z10BC_2 = 21,
CPU_S390X_Z196 = 22,
CPU_S390X_Z196_2 = 23,
CPU_S390X_Z114 = 24,
CPU_S390X_ZEC12 = 25,
CPU_S390X_ZEC12_2 = 26,
CPU_S390X_ZBC12 = 27,
CPU_S390X_Z13 = 28,
CPU_S390X_Z13_2 = 29,
CPU_S390X_Z13S = 30,
CPU_S390X_Z14 = 31,
CPU_S390X_Z14_2 = 32,
CPU_S390X_Z14ZR1 = 33,
CPU_S390X_GEN15A = 34,
CPU_S390X_GEN15B = 35,
CPU_S390X_QEMU = 36,
CPU_S390X_MAX = 37,
CPU_S390X_ENDING = 38,
// S390X registers
S390X_REG_INVALID = 0,
// General purpose registers
S390X_REG_R0 = 1,
S390X_REG_R1 = 2,
S390X_REG_R2 = 3,
S390X_REG_R3 = 4,
S390X_REG_R4 = 5,
S390X_REG_R5 = 6,
S390X_REG_R6 = 7,
S390X_REG_R7 = 8,
S390X_REG_R8 = 9,
S390X_REG_R9 = 10,
S390X_REG_R10 = 11,
S390X_REG_R11 = 12,
S390X_REG_R12 = 13,
S390X_REG_R13 = 14,
S390X_REG_R14 = 15,
S390X_REG_R15 = 16,
// Floating point registers
S390X_REG_F0 = 17,
S390X_REG_F1 = 18,
S390X_REG_F2 = 19,
S390X_REG_F3 = 20,
S390X_REG_F4 = 21,
S390X_REG_F5 = 22,
S390X_REG_F6 = 23,
S390X_REG_F7 = 24,
S390X_REG_F8 = 25,
S390X_REG_F9 = 26,
S390X_REG_F10 = 27,
S390X_REG_F11 = 28,
S390X_REG_F12 = 29,
S390X_REG_F13 = 30,
S390X_REG_F14 = 31,
S390X_REG_F15 = 32,
S390X_REG_F16 = 33,
S390X_REG_F17 = 34,
S390X_REG_F18 = 35,
S390X_REG_F19 = 36,
S390X_REG_F20 = 37,
S390X_REG_F21 = 38,
S390X_REG_F22 = 39,
S390X_REG_F23 = 40,
S390X_REG_F24 = 41,
S390X_REG_F25 = 42,
S390X_REG_F26 = 43,
S390X_REG_F27 = 44,
S390X_REG_F28 = 45,
S390X_REG_F29 = 46,
S390X_REG_F30 = 47,
S390X_REG_F31 = 48,
// Access registers
S390X_REG_A0 = 49,
S390X_REG_A1 = 50,
S390X_REG_A2 = 51,
S390X_REG_A3 = 52,
S390X_REG_A4 = 53,
S390X_REG_A5 = 54,
S390X_REG_A6 = 55,
S390X_REG_A7 = 56,
S390X_REG_A8 = 57,
S390X_REG_A9 = 58,
S390X_REG_A10 = 59,
S390X_REG_A11 = 60,
S390X_REG_A12 = 61,
S390X_REG_A13 = 62,
S390X_REG_A14 = 63,
S390X_REG_A15 = 64,
S390X_REG_PC = 65,
S390X_REG_PSWM = 66,
S390X_REG_ENDING = 67,
// Alias registers
};

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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
pub const sparcConst = enum(c_int) {
// SPARC32 CPU
CPU_SPARC32_FUJITSU_MB86904 = 0,
CPU_SPARC32_FUJITSU_MB86907 = 1,
CPU_SPARC32_TI_MICROSPARC_I = 2,
CPU_SPARC32_TI_MICROSPARC_II = 3,
CPU_SPARC32_TI_MICROSPARC_IIEP = 4,
CPU_SPARC32_TI_SUPERSPARC_40 = 5,
CPU_SPARC32_TI_SUPERSPARC_50 = 6,
CPU_SPARC32_TI_SUPERSPARC_51 = 7,
CPU_SPARC32_TI_SUPERSPARC_60 = 8,
CPU_SPARC32_TI_SUPERSPARC_61 = 9,
CPU_SPARC32_TI_SUPERSPARC_II = 10,
CPU_SPARC32_LEON2 = 11,
CPU_SPARC32_LEON3 = 12,
CPU_SPARC32_ENDING = 13,
// SPARC64 CPU
CPU_SPARC64_FUJITSU = 0,
CPU_SPARC64_FUJITSU_III = 1,
CPU_SPARC64_FUJITSU_IV = 2,
CPU_SPARC64_FUJITSU_V = 3,
CPU_SPARC64_TI_ULTRASPARC_I = 4,
CPU_SPARC64_TI_ULTRASPARC_II = 5,
CPU_SPARC64_TI_ULTRASPARC_III = 6,
CPU_SPARC64_TI_ULTRASPARC_IIE = 7,
CPU_SPARC64_SUN_ULTRASPARC_III = 8,
CPU_SPARC64_SUN_ULTRASPARC_III_CU = 9,
CPU_SPARC64_SUN_ULTRASPARC_IIII = 10,
CPU_SPARC64_SUN_ULTRASPARC_IV = 11,
CPU_SPARC64_SUN_ULTRASPARC_IV_PLUS = 12,
CPU_SPARC64_SUN_ULTRASPARC_IIII_PLUS = 13,
CPU_SPARC64_SUN_ULTRASPARC_T1 = 14,
CPU_SPARC64_SUN_ULTRASPARC_T2 = 15,
CPU_SPARC64_NEC_ULTRASPARC_I = 16,
CPU_SPARC64_ENDING = 17,
// SPARC registers
SPARC_REG_INVALID = 0,
SPARC_REG_F0 = 1,
SPARC_REG_F1 = 2,
SPARC_REG_F2 = 3,
SPARC_REG_F3 = 4,
SPARC_REG_F4 = 5,
SPARC_REG_F5 = 6,
SPARC_REG_F6 = 7,
SPARC_REG_F7 = 8,
SPARC_REG_F8 = 9,
SPARC_REG_F9 = 10,
SPARC_REG_F10 = 11,
SPARC_REG_F11 = 12,
SPARC_REG_F12 = 13,
SPARC_REG_F13 = 14,
SPARC_REG_F14 = 15,
SPARC_REG_F15 = 16,
SPARC_REG_F16 = 17,
SPARC_REG_F17 = 18,
SPARC_REG_F18 = 19,
SPARC_REG_F19 = 20,
SPARC_REG_F20 = 21,
SPARC_REG_F21 = 22,
SPARC_REG_F22 = 23,
SPARC_REG_F23 = 24,
SPARC_REG_F24 = 25,
SPARC_REG_F25 = 26,
SPARC_REG_F26 = 27,
SPARC_REG_F27 = 28,
SPARC_REG_F28 = 29,
SPARC_REG_F29 = 30,
SPARC_REG_F30 = 31,
SPARC_REG_F31 = 32,
SPARC_REG_F32 = 33,
SPARC_REG_F34 = 34,
SPARC_REG_F36 = 35,
SPARC_REG_F38 = 36,
SPARC_REG_F40 = 37,
SPARC_REG_F42 = 38,
SPARC_REG_F44 = 39,
SPARC_REG_F46 = 40,
SPARC_REG_F48 = 41,
SPARC_REG_F50 = 42,
SPARC_REG_F52 = 43,
SPARC_REG_F54 = 44,
SPARC_REG_F56 = 45,
SPARC_REG_F58 = 46,
SPARC_REG_F60 = 47,
SPARC_REG_F62 = 48,
SPARC_REG_FCC0 = 49,
SPARC_REG_FCC1 = 50,
SPARC_REG_FCC2 = 51,
SPARC_REG_FCC3 = 52,
SPARC_REG_G0 = 53,
SPARC_REG_G1 = 54,
SPARC_REG_G2 = 55,
SPARC_REG_G3 = 56,
SPARC_REG_G4 = 57,
SPARC_REG_G5 = 58,
SPARC_REG_G6 = 59,
SPARC_REG_G7 = 60,
SPARC_REG_I0 = 61,
SPARC_REG_I1 = 62,
SPARC_REG_I2 = 63,
SPARC_REG_I3 = 64,
SPARC_REG_I4 = 65,
SPARC_REG_I5 = 66,
SPARC_REG_FP = 67,
SPARC_REG_I7 = 68,
SPARC_REG_ICC = 69,
SPARC_REG_L0 = 70,
SPARC_REG_L1 = 71,
SPARC_REG_L2 = 72,
SPARC_REG_L3 = 73,
SPARC_REG_L4 = 74,
SPARC_REG_L5 = 75,
SPARC_REG_L6 = 76,
SPARC_REG_L7 = 77,
SPARC_REG_O0 = 78,
SPARC_REG_O1 = 79,
SPARC_REG_O2 = 80,
SPARC_REG_O3 = 81,
SPARC_REG_O4 = 82,
SPARC_REG_O5 = 83,
SPARC_REG_SP = 84,
SPARC_REG_O7 = 85,
SPARC_REG_Y = 86,
SPARC_REG_XCC = 87,
SPARC_REG_PC = 88,
SPARC_REG_ENDING = 89,
SPARC_REG_O6 = 84,
SPARC_REG_I6 = 67,
};

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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
pub const tricoreConst = enum(c_int) {
// TRICORE CPU
CPU_TRICORE_TC1796 = 0,
CPU_TRICORE_TC1797 = 1,
CPU_TRICORE_TC27X = 2,
CPU_TRICORE_ENDING = 3,
// TRICORE registers
TRICORE_REG_INVALID = 0,
TRICORE_REG_A0 = 1,
TRICORE_REG_A1 = 2,
TRICORE_REG_A2 = 3,
TRICORE_REG_A3 = 4,
TRICORE_REG_A4 = 5,
TRICORE_REG_A5 = 6,
TRICORE_REG_A6 = 7,
TRICORE_REG_A7 = 8,
TRICORE_REG_A8 = 9,
TRICORE_REG_A9 = 10,
TRICORE_REG_A10 = 11,
TRICORE_REG_A11 = 12,
TRICORE_REG_A12 = 13,
TRICORE_REG_A13 = 14,
TRICORE_REG_A14 = 15,
TRICORE_REG_A15 = 16,
TRICORE_REG_D0 = 17,
TRICORE_REG_D1 = 18,
TRICORE_REG_D2 = 19,
TRICORE_REG_D3 = 20,
TRICORE_REG_D4 = 21,
TRICORE_REG_D5 = 22,
TRICORE_REG_D6 = 23,
TRICORE_REG_D7 = 24,
TRICORE_REG_D8 = 25,
TRICORE_REG_D9 = 26,
TRICORE_REG_D10 = 27,
TRICORE_REG_D11 = 28,
TRICORE_REG_D12 = 29,
TRICORE_REG_D13 = 30,
TRICORE_REG_D14 = 31,
TRICORE_REG_D15 = 32,
TRICORE_REG_PCXI = 33,
TRICORE_REG_PSW = 34,
TRICORE_REG_PSW_USB_C = 35,
TRICORE_REG_PSW_USB_V = 36,
TRICORE_REG_PSW_USB_SV = 37,
TRICORE_REG_PSW_USB_AV = 38,
TRICORE_REG_PSW_USB_SAV = 39,
TRICORE_REG_PC = 40,
TRICORE_REG_SYSCON = 41,
TRICORE_REG_CPU_ID = 42,
TRICORE_REG_BIV = 43,
TRICORE_REG_BTV = 44,
TRICORE_REG_ISP = 45,
TRICORE_REG_ICR = 46,
TRICORE_REG_FCX = 47,
TRICORE_REG_LCX = 48,
TRICORE_REG_COMPAT = 49,
TRICORE_REG_DPR0_U = 50,
TRICORE_REG_DPR1_U = 51,
TRICORE_REG_DPR2_U = 52,
TRICORE_REG_DPR3_U = 53,
TRICORE_REG_DPR0_L = 54,
TRICORE_REG_DPR1_L = 55,
TRICORE_REG_DPR2_L = 56,
TRICORE_REG_DPR3_L = 57,
TRICORE_REG_CPR0_U = 58,
TRICORE_REG_CPR1_U = 59,
TRICORE_REG_CPR2_U = 60,
TRICORE_REG_CPR3_U = 61,
TRICORE_REG_CPR0_L = 62,
TRICORE_REG_CPR1_L = 63,
TRICORE_REG_CPR2_L = 64,
TRICORE_REG_CPR3_L = 65,
TRICORE_REG_DPM0 = 66,
TRICORE_REG_DPM1 = 67,
TRICORE_REG_DPM2 = 68,
TRICORE_REG_DPM3 = 69,
TRICORE_REG_CPM0 = 70,
TRICORE_REG_CPM1 = 71,
TRICORE_REG_CPM2 = 72,
TRICORE_REG_CPM3 = 73,
TRICORE_REG_MMU_CON = 74,
TRICORE_REG_MMU_ASI = 75,
TRICORE_REG_MMU_TVA = 76,
TRICORE_REG_MMU_TPA = 77,
TRICORE_REG_MMU_TPX = 78,
TRICORE_REG_MMU_TFA = 79,
TRICORE_REG_BMACON = 80,
TRICORE_REG_SMACON = 81,
TRICORE_REG_DIEAR = 82,
TRICORE_REG_DIETR = 83,
TRICORE_REG_CCDIER = 84,
TRICORE_REG_MIECON = 85,
TRICORE_REG_PIEAR = 86,
TRICORE_REG_PIETR = 87,
TRICORE_REG_CCPIER = 88,
TRICORE_REG_DBGSR = 89,
TRICORE_REG_EXEVT = 90,
TRICORE_REG_CREVT = 91,
TRICORE_REG_SWEVT = 92,
TRICORE_REG_TR0EVT = 93,
TRICORE_REG_TR1EVT = 94,
TRICORE_REG_DMS = 95,
TRICORE_REG_DCX = 96,
TRICORE_REG_DBGTCR = 97,
TRICORE_REG_CCTRL = 98,
TRICORE_REG_CCNT = 99,
TRICORE_REG_ICNT = 100,
TRICORE_REG_M1CNT = 101,
TRICORE_REG_M2CNT = 102,
TRICORE_REG_M3CNT = 103,
TRICORE_REG_ENDING = 104,
TRICORE_REG_GA0 = 1,
TRICORE_REG_GA1 = 2,
TRICORE_REG_GA8 = 9,
TRICORE_REG_GA9 = 10,
TRICORE_REG_SP = 11,
TRICORE_REG_LR = 12,
TRICORE_REG_IA = 16,
TRICORE_REG_ID = 32,
};

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// Architectures
pub const arm = @import("arm_const.zig");
pub const arm64 = @import("arm64_const.zig");
pub const m68k = @import("m68k_const.zig");
pub const mips = @import("mips_const.zig");
pub const ppc = @import("ppc_const.zig");
pub const riscv = @import("riscv_const.zig");
pub const tricore = @import("tricore_const.zig");
pub const sparc = @import("sparc_const.zig");
pub const s390x = @import("s390x_const.zig");
pub const x86 = @import("x86_const.zig");
// Unicorn
pub const unicorn = @import("unicorn_const.zig");

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// For Unicorn Engine. AUTO-GENERATED FILE, DO NOT EDIT
pub const unicornConst = enum(c_int) {
API_MAJOR = 2,
API_MINOR = 0,
API_PATCH = 1,
API_EXTRA = 255,
VERSION_MAJOR = 2,
VERSION_MINOR = 0,
VERSION_PATCH = 1,
VERSION_EXTRA = 255,
SECOND_SCALE = 1000000,
MILISECOND_SCALE = 1000,
ARCH_ARM = 1,
ARCH_ARM64 = 2,
ARCH_MIPS = 3,
ARCH_X86 = 4,
ARCH_PPC = 5,
ARCH_SPARC = 6,
ARCH_M68K = 7,
ARCH_RISCV = 8,
ARCH_S390X = 9,
ARCH_TRICORE = 10,
ARCH_MAX = 11,
MODE_LITTLE_ENDIAN = 0,
MODE_BIG_ENDIAN = 1073741824,
MODE_ARM = 0,
MODE_THUMB = 16,
MODE_MCLASS = 32,
MODE_V8 = 64,
MODE_ARMBE8 = 1024,
MODE_ARM926 = 128,
MODE_ARM946 = 256,
MODE_ARM1176 = 512,
MODE_MICRO = 16,
MODE_MIPS3 = 32,
MODE_MIPS32R6 = 64,
MODE_MIPS32 = 4,
MODE_MIPS64 = 8,
MODE_16 = 2,
MODE_32 = 4,
MODE_64 = 8,
MODE_PPC32 = 4,
MODE_PPC64 = 8,
MODE_QPX = 16,
MODE_SPARC32 = 4,
MODE_SPARC64 = 8,
MODE_V9 = 16,
MODE_RISCV32 = 4,
MODE_RISCV64 = 8,
ERR_OK = 0,
ERR_NOMEM = 1,
ERR_ARCH = 2,
ERR_HANDLE = 3,
ERR_MODE = 4,
ERR_VERSION = 5,
ERR_READ_UNMAPPED = 6,
ERR_WRITE_UNMAPPED = 7,
ERR_FETCH_UNMAPPED = 8,
ERR_HOOK = 9,
ERR_INSN_INVALID = 10,
ERR_MAP = 11,
ERR_WRITE_PROT = 12,
ERR_READ_PROT = 13,
ERR_FETCH_PROT = 14,
ERR_ARG = 15,
ERR_READ_UNALIGNED = 16,
ERR_WRITE_UNALIGNED = 17,
ERR_FETCH_UNALIGNED = 18,
ERR_HOOK_EXIST = 19,
ERR_RESOURCE = 20,
ERR_EXCEPTION = 21,
MEM_READ = 16,
MEM_WRITE = 17,
MEM_FETCH = 18,
MEM_READ_UNMAPPED = 19,
MEM_WRITE_UNMAPPED = 20,
MEM_FETCH_UNMAPPED = 21,
MEM_WRITE_PROT = 22,
MEM_READ_PROT = 23,
MEM_FETCH_PROT = 24,
MEM_READ_AFTER = 25,
TCG_OP_SUB = 0,
TCG_OP_FLAG_CMP = 1,
TCG_OP_FLAG_DIRECT = 2,
HOOK_INTR = 1,
HOOK_INSN = 2,
HOOK_CODE = 4,
HOOK_BLOCK = 8,
HOOK_MEM_READ_UNMAPPED = 16,
HOOK_MEM_WRITE_UNMAPPED = 32,
HOOK_MEM_FETCH_UNMAPPED = 64,
HOOK_MEM_READ_PROT = 128,
HOOK_MEM_WRITE_PROT = 256,
HOOK_MEM_FETCH_PROT = 512,
HOOK_MEM_READ = 1024,
HOOK_MEM_WRITE = 2048,
HOOK_MEM_FETCH = 4096,
HOOK_MEM_READ_AFTER = 8192,
HOOK_INSN_INVALID = 16384,
HOOK_EDGE_GENERATED = 32768,
HOOK_TCG_OPCODE = 65536,
HOOK_MEM_UNMAPPED = 112,
HOOK_MEM_PROT = 896,
HOOK_MEM_READ_INVALID = 144,
HOOK_MEM_WRITE_INVALID = 288,
HOOK_MEM_FETCH_INVALID = 576,
HOOK_MEM_INVALID = 1008,
HOOK_MEM_VALID = 7168,
QUERY_MODE = 1,
QUERY_PAGE_SIZE = 2,
QUERY_ARCH = 3,
QUERY_TIMEOUT = 4,
CTL_IO_NONE = 0,
CTL_IO_WRITE = 1,
CTL_IO_READ = 2,
CTL_IO_READ_WRITE = 3,
CTL_UC_MODE = 0,
CTL_UC_PAGE_SIZE = 1,
CTL_UC_ARCH = 2,
CTL_UC_TIMEOUT = 3,
CTL_UC_USE_EXITS = 4,
CTL_UC_EXITS_CNT = 5,
CTL_UC_EXITS = 6,
CTL_CPU_MODEL = 7,
CTL_TB_REQUEST_CACHE = 8,
CTL_TB_REMOVE_CACHE = 9,
CTL_TB_FLUSH = 10,
PROT_NONE = 0,
PROT_READ = 1,
PROT_WRITE = 2,
PROT_EXEC = 4,
PROT_ALL = 7,
};

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