From 59fb8a27339161706f40308af4b7096b2f6c7a18 Mon Sep 17 00:00:00 2001
From: Sven Bartscher <sven.bartscher@credativ.de>
Date: Tue, 30 Nov 2021 16:09:24 +0100
Subject: [PATCH] rust: Add RISCV CSR registers

The addition of these registers in the C base caused the rust values
for all floating point registers and the PC to point to some of the
CSR registers instead.
---
 bindings/rust/src/riscv.rs | 195 ++++++++++++++++++++++++++++++-------
 1 file changed, 161 insertions(+), 34 deletions(-)

diff --git a/bindings/rust/src/riscv.rs b/bindings/rust/src/riscv.rs
index 1d7e0db1..76f74914 100644
--- a/bindings/rust/src/riscv.rs
+++ b/bindings/rust/src/riscv.rs
@@ -41,41 +41,168 @@ pub enum RegisterRISCV {
     X30 = 31,
     X31 = 32,
 
+    // CSR
+    USTATUS = 33,
+    UIE = 34,
+    UTVEC = 35,
+    USCRATCH = 36,
+    UEPC = 37,
+    UCAUSE = 38,
+    UTVAL = 39,
+    UIP = 40,
+    FFLAGS = 41,
+    FRM = 42,
+    FCSR = 43,
+    CYCLE = 44,
+    TIME = 45,
+    INSTRET = 46,
+    HPMCOUNTER3 = 47,
+    HPMCOUNTER4 = 48,
+    HPMCOUNTER5 = 49,
+    HPMCOUNTER6 = 50,
+    HPMCOUNTER7 = 51,
+    HPMCOUNTER8 = 52,
+    HPMCOUNTER9 = 53,
+    HPMCOUNTER10 = 54,
+    HPMCOUNTER11 = 55,
+    HPMCOUNTER12 = 56,
+    HPMCOUNTER13 = 57,
+    HPMCOUNTER14 = 58,
+    HPMCOUNTER15 = 59,
+    HPMCOUNTER16 = 60,
+    HPMCOUNTER17 = 61,
+    HPMCOUNTER18 = 62,
+    HPMCOUNTER19 = 63,
+    HPMCOUNTER20 = 64,
+    HPMCOUNTER21 = 65,
+    HPMCOUNTER22 = 66,
+    HPMCOUNTER23 = 67,
+    HPMCOUNTER24 = 68,
+    HPMCOUNTER25 = 69,
+    HPMCOUNTER26 = 70,
+    HPMCOUNTER27 = 71,
+    HPMCOUNTER28 = 72,
+    HPMCOUNTER29 = 73,
+    HPMCOUNTER30 = 74,
+    HPMCOUNTER31 = 75,
+    CYCLEH = 76,
+    TIMEH = 77,
+    INSTRETH = 78,
+    HPMCOUNTER3H = 79,
+    HPMCOUNTER4H = 80,
+    HPMCOUNTER5H = 81,
+    HPMCOUNTER6H = 82,
+    HPMCOUNTER7H = 83,
+    HPMCOUNTER8H = 84,
+    HPMCOUNTER9H = 85,
+    HPMCOUNTER10H = 86,
+    HPMCOUNTER11H = 87,
+    HPMCOUNTER12H = 88,
+    HPMCOUNTER13H = 89,
+    HPMCOUNTER14H = 90,
+    HPMCOUNTER15H = 91,
+    HPMCOUNTER16H = 92,
+    HPMCOUNTER17H = 93,
+    HPMCOUNTER18H = 94,
+    HPMCOUNTER19H = 95,
+    HPMCOUNTER20H = 96,
+    HPMCOUNTER21H = 97,
+    HPMCOUNTER22H = 98,
+    HPMCOUNTER23H = 99,
+    HPMCOUNTER24H = 100,
+    HPMCOUNTER25H = 101,
+    HPMCOUNTER26H = 102,
+    HPMCOUNTER27H = 103,
+    HPMCOUNTER28H = 104,
+    HPMCOUNTER29H = 105,
+    HPMCOUNTER30H = 106,
+    HPMCOUNTER31H = 107,
+    MCYCLE = 108,
+    MINSTRET = 109,
+    MCYCLEH = 110,
+    MINSTRETH = 111,
+    MVENDORID = 112,
+    MARCHID = 113,
+    MIMPID = 114,
+    MHARTID = 115,
+    MSTATUS = 116,
+    MISA = 117,
+    MEDELEG = 118,
+    MIDELEG = 119,
+    MIE = 120,
+    MTVEC = 121,
+    MCOUNTEREN = 122,
+    MSTATUSH = 123,
+    MUCOUNTEREN = 124,
+    MSCOUNTEREN = 125,
+    MHCOUNTEREN = 126,
+    MSCRATCH = 127,
+    MEPC = 128,
+    MCAUSE = 129,
+    MTVAL = 130,
+    MIP = 131,
+    MBADADDR = 132,
+    SSTATUS = 133,
+    SEDELEG = 134,
+    SIDELEG = 135,
+    SIE = 136,
+    STVEC = 137,
+    SCOUNTEREN = 138,
+    SSCRATCH = 139,
+    SEPC = 140,
+    SCAUSE = 141,
+    STVAL = 142,
+    SIP = 143,
+    SBADADDR = 144,
+    SPTBR = 145,
+    SATP = 146,
+    HSTATUS = 147,
+    HEDELEG = 148,
+    HIDELEG = 149,
+    HIE = 150,
+    HCOUNTEREN = 151,
+    HTVAL = 152,
+    HIP = 153,
+    HTINST = 154,
+    HGATP = 155,
+    HTIMEDELTA = 156,
+    HTIMEDELTAH = 157,
+
     // Floating-point registers
-    F0 = 33,
-    F1 = 34,
-    F2 = 35,
-    F3 = 36,
-    F4 = 37,
-    F5 = 38,
-    F6 = 39,
-    F7 = 40,
-    F8 = 41,
-    F9 = 42,
-    F10 = 43,
-    F11 = 44,
-    F12 = 45,
-    F13 = 46,
-    F14 = 47,
-    F15 = 48,
-    F16 = 49,
-    F17 = 50,
-    F18 = 51,
-    F19 = 52,
-    F20 = 53,
-    F21 = 54,
-    F22 = 55,
-    F23 = 56,
-    F24 = 57,
-    F25 = 58,
-    F26 = 59,
-    F27 = 60,
-    F28 = 61,
-    F29 = 62,
-    F30 = 63,
-    F31 = 64,
-    PC = 65,
-    ENDING = 66,
+    F0 = 158,
+    F1 = 159,
+    F2 = 160,
+    F3 = 161,
+    F4 = 162,
+    F5 = 163,
+    F6 = 164,
+    F7 = 165,
+    F8 = 166,
+    F9 = 167,
+    F10 = 168,
+    F11 = 169,
+    F12 = 170,
+    F13 = 171,
+    F14 = 172,
+    F15 = 173,
+    F16 = 174,
+    F17 = 175,
+    F18 = 176,
+    F19 = 177,
+    F20 = 178,
+    F21 = 179,
+    F22 = 180,
+    F23 = 181,
+    F24 = 182,
+    F25 = 183,
+    F26 = 184,
+    F27 = 185,
+    F28 = 186,
+    F29 = 187,
+    F30 = 188,
+    F31 = 189,
+    PC = 190,
+    ENDING = 191,
 }
 
 impl RegisterRISCV {