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remove apci, default-congfigs (#1288)

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* remove apic files. update make and cmake.

* remove default-configs dir.

* fix a mem-leak bug. remove owner arg in memory.
This commit is contained in:
Chen Huitao 2020-06-08 08:21:44 +08:00 committed by GitHub
parent a8f724010b
commit c09adf5b7b
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GPG Key ID: 4AEE18F83AFDEB23
32 changed files with 65 additions and 396 deletions
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2
CMakeLists.txt
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@ -282,8 +282,6 @@ add_library(x86_64-softmmu
qemu/exec.c
qemu/fpu/softfloat.c
qemu/hw/i386/pc.c
qemu/hw/intc/apic.c
qemu/hw/intc/apic_common.c
qemu/ioport.c
qemu/memory.c
qemu/memory_mapping.c

1
Makefile
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@ -36,7 +36,6 @@ endif
UC_TARGET_OBJ_X86 = $(call UC_GET_OBJ,obj-,qemu/Makefile.target, qemu/x86_64-softmmu/)
UC_TARGET_OBJ_X86 += $(call UC_GET_OBJ,obj-,qemu/hw/i386/Makefile.objs, qemu/x86_64-softmmu/hw/i386/)
UC_TARGET_OBJ_X86 += $(call UC_GET_OBJ,obj-,qemu/hw/intc/Makefile.objs, qemu/x86_64-softmmu/hw/intc/)
UC_TARGET_OBJ_X86 += $(call UC_GET_OBJ,obj-,qemu/target-i386/Makefile.objs, qemu/x86_64-softmmu/target-i386/)
UC_TARGET_OBJ_ARM = $(call UC_GET_OBJ,obj-,qemu/Makefile.target, qemu/arm-softmmu/)

4
qemu/Makefile
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@ -61,8 +61,8 @@ endif
-include $(SUBDIR_DEVICES_MAK_DEP)
%/config-devices.mak: default-configs/%.mak
$(call quiet-command, cp $< $@, " GEN $@")
%/config-devices.mak:
$(call quiet-command, touch $@, " GEN $@")
ifneq ($(wildcard config-host.mak),)
include $(SRC_PATH)/Makefile.objs

1
qemu/Makefile.objs
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@ -7,6 +7,5 @@ common-obj-y += vl.o qemu-timer.o
common-obj-y += ../uc.o ../list.o glib_compat.o
common-obj-y += qemu-log.o
common-obj-y += tcg-runtime.o
common-obj-y += hw/
common-obj-y += qom/

14
qemu/configure vendored
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@ -587,17 +587,9 @@ esac
QEMU_CFLAGS="$CPU_CFLAGS $QEMU_CFLAGS"
EXTRA_CFLAGS="$CPU_CFLAGS $EXTRA_CFLAGS"
default_target_list=""
mak_wilds=""
if [ "$softmmu" = "yes" ]; then
mak_wilds="${mak_wilds} $source_path/default-configs/*-softmmu.mak"
fi
for config in $mak_wilds; do
default_target_list="${default_target_list} $(basename "$config" .mak)"
done
default_target_list="aarch64eb-softmmu aarch64-softmmu armeb-softmmu \
arm-softmmu m68k-softmmu mips64el-softmmu mips64-softmmu mipsel-softmmu \
mips-softmmu ppc-softmmu sparc64-softmmu sparc-softmmu x86_64-softmmu"
if test x"$show_help" = x"yes" ; then
cat << EOF

0
qemu/default-configs/aarch64-softmmu.mak
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0
qemu/default-configs/aarch64eb-softmmu.mak
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0
qemu/default-configs/arm-softmmu.mak
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0
qemu/default-configs/armeb-softmmu.mak
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0
qemu/default-configs/m68k-softmmu.mak
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0
qemu/default-configs/mips-softmmu.mak
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0
qemu/default-configs/mips64-softmmu.mak
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0
qemu/default-configs/mips64el-softmmu.mak
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0
qemu/default-configs/mipsel-softmmu.mak
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0
qemu/default-configs/ppc-softmmu.mak
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0
qemu/default-configs/sparc-softmmu.mak
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0
qemu/default-configs/sparc64-softmmu.mak
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3
qemu/default-configs/x86_64-softmmu.mak
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@ -1,3 +0,0 @@
# Default configuration for x86_64-softmmu
CONFIG_APIC=y

12
qemu/exec.c
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@ -1378,12 +1378,12 @@ static const MemoryRegionOps notdirty_mem_ops = {
static void io_mem_init(struct uc_struct* uc)
{
memory_region_init_io(uc, &uc->io_mem_rom, NULL, &unassigned_mem_ops, NULL, NULL, UINT64_MAX);
memory_region_init_io(uc, &uc->io_mem_unassigned, NULL, &unassigned_mem_ops, NULL,
memory_region_init_io(uc, &uc->io_mem_rom, &unassigned_mem_ops, NULL, NULL, UINT64_MAX);
memory_region_init_io(uc, &uc->io_mem_unassigned, &unassigned_mem_ops, NULL,
NULL, UINT64_MAX);
memory_region_init_io(uc, &uc->io_mem_notdirty, NULL, &notdirty_mem_ops, NULL,
memory_region_init_io(uc, &uc->io_mem_notdirty, &notdirty_mem_ops, NULL,
NULL, UINT64_MAX);
//memory_region_init_io(uc, &uc->io_mem_watch, NULL, &watch_mem_ops, NULL,
//memory_region_init_io(uc, &uc->io_mem_watch, &watch_mem_ops, NULL,
// NULL, UINT64_MAX);
}
@ -1395,7 +1395,7 @@ static subpage_t *subpage_init(AddressSpace *as, hwaddr base)
mmio->as = as;
mmio->base = base;
memory_region_init_io(as->uc, &mmio->iomem, NULL, &subpage_ops, mmio,
memory_region_init_io(as->uc, &mmio->iomem, &subpage_ops, mmio,
NULL, TARGET_PAGE_SIZE);
mmio->iomem.subpage = true;
#if defined(DEBUG_SUBPAGE)
@ -1522,7 +1522,7 @@ void address_space_destroy_dispatch(AddressSpace *as)
static void memory_map_init(struct uc_struct *uc)
{
uc->system_memory = g_malloc(sizeof(*(uc->system_memory)));
memory_region_init(uc, uc->system_memory, NULL, "system", UINT64_MAX);
memory_region_init(uc, uc->system_memory, "system", UINT64_MAX);
address_space_init(uc, &uc->as, uc->system_memory, "memory");
}

1
qemu/hw/Makefile.objs
View File

@ -1,3 +1,2 @@
devices-dirs-$(CONFIG_SOFTMMU) += intc/
common-obj-y += $(devices-dirs-y)
obj-y += $(devices-dirs-y)

4
qemu/hw/i386/pc.c
View File

@ -46,6 +46,7 @@ uint64_t cpu_get_tsc(CPUX86State *env)
static cpu_set_smm_t smm_set;
static void *smm_arg;
#if 0
void cpu_smm_register(cpu_set_smm_t callback, void *arg)
{
assert(smm_set == NULL);
@ -53,6 +54,7 @@ void cpu_smm_register(cpu_set_smm_t callback, void *arg)
smm_set = callback;
smm_arg = arg;
}
#endif
void cpu_smm_update(CPUX86State *env)
{
@ -63,6 +65,7 @@ void cpu_smm_update(CPUX86State *env)
}
}
#if 0
/* IRQ handling */
int cpu_get_pic_interrupt(CPUX86State *env)
{
@ -90,4 +93,5 @@ DeviceState *cpu_get_current_apic(struct uc_struct *uc)
return NULL;
}
}
#endif

1
qemu/hw/intc/Makefile.objs
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@ -1 +0,0 @@
obj-$(CONFIG_APIC) += apic.o apic_common.o

52
qemu/hw/intc/apic.c
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@ -1,52 +0,0 @@
/*
* APIC support
*
* Copyright (c) 2004-2005 Fabrice Bellard
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>
*/
/* Modified for Unicorn Engine by Chen Huitao<chenhuitao@hfmrit.com>, 2020 */
#include "qemu/thread.h"
#include "hw/i386/apic_internal.h"
#include "hw/i386/apic.h"
#include "qemu/host-utils.h"
#include "hw/i386/pc.h"
#include "exec/address-spaces.h"
#define MAX_APIC_WORDS 8
#define SYNC_FROM_VAPIC 0x1
#define SYNC_TO_VAPIC 0x2
#define SYNC_ISR_IRR_TO_VAPIC 0x4
void apic_poll_irq(DeviceState *dev)
{
}
void apic_sipi(DeviceState *dev)
{
}
int apic_get_interrupt(DeviceState *dev)
{
return 0;
}
int apic_accept_pic_intr(DeviceState *dev)
{
return 0;
}

281
qemu/hw/intc/apic_common.c
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@ -1,281 +0,0 @@
/*
* APIC support - common bits of emulated and KVM kernel model
*
* Copyright (c) 2004-2005 Fabrice Bellard
* Copyright (c) 2011 Jan Kiszka, Siemens AG
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>
*/
/* Modified for Unicorn Engine by Chen Huitao<chenhuitao@hfmrit.com>, 2020 */
#include "hw/i386/apic.h"
#include "hw/i386/apic_internal.h"
#if 0
#include "hw/qdev.h"
#endif
#include "uc_priv.h"
void cpu_set_apic_base(struct uc_struct *uc, DeviceState *dev, uint64_t val)
{
if (dev) {
APICCommonState *s = APIC_COMMON(uc, dev);
APICCommonClass *info = APIC_COMMON_GET_CLASS(uc, s);
info->set_base(s, val);
}
}
uint64_t cpu_get_apic_base(struct uc_struct *uc, DeviceState *dev)
{
if (dev) {
APICCommonState *s = APIC_COMMON(uc, dev);
return s->apicbase;
} else {
return MSR_IA32_APICBASE_BSP;
}
}
void cpu_set_apic_tpr(struct uc_struct *uc, DeviceState *dev, uint8_t val)
{
APICCommonState *s;
APICCommonClass *info;
if (!dev) {
return;
}
s = APIC_COMMON(uc, dev);
info = APIC_COMMON_GET_CLASS(uc, s);
info->set_tpr(s, val);
}
uint8_t cpu_get_apic_tpr(struct uc_struct *uc, DeviceState *dev)
{
APICCommonState *s;
APICCommonClass *info;
if (!dev) {
return 0;
}
s = APIC_COMMON(uc, dev);
info = APIC_COMMON_GET_CLASS(uc, s);
return info->get_tpr(s);
}
void apic_enable_vapic(struct uc_struct *uc, DeviceState *dev, hwaddr paddr)
{
APICCommonState *s = APIC_COMMON(uc, dev);
APICCommonClass *info = APIC_COMMON_GET_CLASS(uc, s);
s->vapic_paddr = paddr;
info->vapic_base_update(s);
}
void apic_handle_tpr_access_report(DeviceState *dev, target_ulong ip,
TPRAccess access)
{
//APICCommonState *s = APIC_COMMON(NULL, dev);
//vapic_report_tpr_access(s->vapic, CPU(s->cpu), ip, access);
}
bool apic_next_timer(APICCommonState *s, int64_t current_time)
{
int64_t d;
/* We need to store the timer state separately to support APIC
* implementations that maintain a non-QEMU timer, e.g. inside the
* host kernel. This open-coded state allows us to migrate between
* both models. */
s->timer_expiry = -1;
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
return false;
}
d = (current_time - s->initial_count_load_time) >> s->count_shift;
if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
if (!s->initial_count) {
return false;
}
d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
((uint64_t)s->initial_count + 1);
} else {
if (d >= s->initial_count) {
return false;
}
d = (uint64_t)s->initial_count + 1;
}
s->next_time = s->initial_count_load_time + (d << s->count_shift);
s->timer_expiry = s->next_time;
return true;
}
void apic_init_reset(struct uc_struct *uc, DeviceState *dev)
{
APICCommonState *s = APIC_COMMON(uc, dev);
APICCommonClass *info = APIC_COMMON_GET_CLASS(uc, s);
int i;
if (!s) {
return;
}
s->tpr = 0;
s->spurious_vec = 0xff;
s->log_dest = 0;
s->dest_mode = 0xf;
memset(s->isr, 0, sizeof(s->isr));
memset(s->tmr, 0, sizeof(s->tmr));
memset(s->irr, 0, sizeof(s->irr));
for (i = 0; i < APIC_LVT_NB; i++) {
s->lvt[i] = APIC_LVT_MASKED;
}
s->esr = 0;
memset(s->icr, 0, sizeof(s->icr));
s->divide_conf = 0;
s->count_shift = 0;
s->initial_count = 0;
s->initial_count_load_time = 0;
s->next_time = 0;
s->wait_for_sipi = !cpu_is_bsp(s->cpu);
if (s->timer) {
// timer_del(s->timer);
}
s->timer_expiry = -1;
if (info->reset) {
info->reset(s);
}
}
void apic_designate_bsp(struct uc_struct *uc, DeviceState *dev)
{
APICCommonState *s;
if (dev == NULL) {
return;
}
s = APIC_COMMON(uc, dev);
s->apicbase |= MSR_IA32_APICBASE_BSP;
}
#if 0
static void apic_reset_common(struct uc_struct *uc, DeviceState *dev)
{
APICCommonState *s = APIC_COMMON(uc, dev);
APICCommonClass *info = APIC_COMMON_GET_CLASS(uc, s);
bool bsp;
bsp = cpu_is_bsp(s->cpu);
s->apicbase = APIC_DEFAULT_ADDRESS |
(bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
s->vapic_paddr = 0;
info->vapic_base_update(s);
apic_init_reset(uc, dev);
if (bsp) {
/*
* LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
* time typically by BIOS, so PIC interrupt can be delivered to the
* processor when local APIC is enabled.
*/
s->lvt[APIC_LVT_LINT0] = 0x700;
}
}
static int apic_common_realize(struct uc_struct *uc, DeviceState *dev, Error **errp)
{
APICCommonState *s = APIC_COMMON(uc, dev);
APICCommonClass *info;
if (uc->apic_no >= MAX_APICS) {
error_setg(errp, "%s initialization failed.",
object_get_typename(OBJECT(dev)));
return -1;
}
s->idx = uc->apic_no++;
info = APIC_COMMON_GET_CLASS(uc, s);
info->realize(uc, dev, errp);
if (!uc->mmio_registered) {
ICCBus *b = ICC_BUS(uc, qdev_get_parent_bus(dev));
memory_region_add_subregion(b->apic_address_space, 0, &s->io_memory);
uc->mmio_registered = true;
}
/* Note: We need at least 1M to map the VAPIC option ROM */
if (!uc->vapic && s->vapic_control & VAPIC_ENABLE_MASK) {
// ram_size >= 1024 * 1024) { // FIXME
uc->vapic = NULL;
}
s->vapic = uc->vapic;
if (uc->apic_report_tpr_access && info->enable_tpr_reporting) {
info->enable_tpr_reporting(s, true);
}
return 0;
}
static void apic_common_class_init(struct uc_struct *uc, ObjectClass *klass, void *data)
{
ICCDeviceClass *idc = ICC_DEVICE_CLASS(uc, klass);
DeviceClass *dc = DEVICE_CLASS(uc, klass);
dc->reset = apic_reset_common;
idc->realize = apic_common_realize;
/*
* Reason: APIC and CPU need to be wired up by
* x86_cpu_apic_create()
*/
dc->cannot_instantiate_with_device_add_yet = true;
//printf("... init apic common class\n");
}
static const TypeInfo apic_common_type = {
TYPE_APIC_COMMON,
TYPE_DEVICE,
sizeof(APICCommonClass),
sizeof(APICCommonState),
NULL,
NULL,
NULL,
NULL,
NULL,
apic_common_class_init,
NULL,
NULL,
true,
};
void apic_common_register_types(struct uc_struct *uc)
{
//printf("... register apic common\n");
type_register_static(uc, &apic_common_type);
}
#endif

21
qemu/include/exec/memory.h
View File

@ -26,20 +26,10 @@
#include "exec/hwaddr.h"
#include "qemu/queue.h"
#include "qemu/int128.h"
#if 0
#include "qapi/error.h"
#include "qom/object.h"
#endif
#define MAX_PHYS_ADDR_SPACE_BITS 62
#define MAX_PHYS_ADDR (((hwaddr)1 << MAX_PHYS_ADDR_SPACE_BITS) - 1)
#if 0
#define TYPE_MEMORY_REGION "qemu:memory-region"
#define MEMORY_REGION(uc, obj) \
OBJECT_CHECK(uc, MemoryRegion, (obj), TYPE_MEMORY_REGION)
#endif
typedef struct MemoryRegionOps MemoryRegionOps;
typedef struct MemoryRegionMmio MemoryRegionMmio;
@ -132,9 +122,6 @@ struct MemoryRegionIOMMUOps {
};
struct MemoryRegion {
#if 0
Object parent_obj;
#endif
/* All fields are private - violators will be prosecuted */
const MemoryRegionOps *ops;
const MemoryRegionIOMMUOps *iommu_ops;
@ -253,7 +240,6 @@ static inline MemoryRegionSection MemoryRegionSection_make(MemoryRegion *mr, Add
* @size: size of the region; any subregions beyond this size will be clipped
*/
void memory_region_init(struct uc_struct *uc, MemoryRegion *mr,
void *owner,
const char *name,
uint64_t size);
@ -301,7 +287,6 @@ void memory_region_unref(MemoryRegion *mr);
* @size: size of the region.
*/
void memory_region_init_io(struct uc_struct *uc, MemoryRegion *mr,
void *owner,
const MemoryRegionOps *ops,
void *opaque,
const char *name,
@ -319,7 +304,6 @@ void memory_region_init_io(struct uc_struct *uc, MemoryRegion *mr,
* @errp: pointer to Error*, to store an error if it happens.
*/
void memory_region_init_ram(struct uc_struct *uc, MemoryRegion *mr,
void *owner,
const char *name,
uint64_t size,
uint32_t perms);
@ -336,7 +320,6 @@ void memory_region_init_ram(struct uc_struct *uc, MemoryRegion *mr,
* @ptr: memory to be mapped; must contain at least @size bytes.
*/
void memory_region_init_ram_ptr(struct uc_struct *uc, MemoryRegion *mr,
void *owner,
const char *name,
uint64_t size,
void *ptr);
@ -354,7 +337,6 @@ void memory_region_init_ram_ptr(struct uc_struct *uc, MemoryRegion *mr,
* @size: size of the region.
*/
void memory_region_init_alias(struct uc_struct *uc, MemoryRegion *mr,
void *owner,
const char *name,
MemoryRegion *orig,
hwaddr offset,
@ -372,7 +354,6 @@ void memory_region_init_alias(struct uc_struct *uc, MemoryRegion *mr,
* @errp: pointer to Error*, to store an error if it happens.
*/
void memory_region_init_rom_device(MemoryRegion *mr,
void *owner,
const MemoryRegionOps *ops,
void *opaque,
const char *name,
@ -392,7 +373,6 @@ void memory_region_init_rom_device(MemoryRegion *mr,
* @size: size of the region.
*/
void memory_region_init_reservation(struct uc_struct *uc, MemoryRegion *mr,
void *owner,
const char *name,
uint64_t size);
@ -410,7 +390,6 @@ void memory_region_init_reservation(struct uc_struct *uc, MemoryRegion *mr,
* @size: size of the region.
*/
void memory_region_init_iommu(MemoryRegion *mr,
void *owner,
const MemoryRegionIOMMUOps *ops,
const char *name,
uint64_t size);

2
qemu/include/hw/i386/pc.h
View File

@ -6,6 +6,8 @@
#include "uc_priv.h"
typedef void (*cpu_set_smm_t)(int smm, void *arg);
#if 0
void cpu_smm_register(cpu_set_smm_t callback, void *arg);
#endif
#endif

20
qemu/memory.c
View File

@ -51,7 +51,7 @@ MemoryRegion *memory_map(struct uc_struct *uc, hwaddr begin, size_t size, uint32
{
MemoryRegion *ram = g_new(MemoryRegion, 1);
memory_region_init_ram(uc, ram, NULL, "pc.ram", size, perms);
memory_region_init_ram(uc, ram, "pc.ram", size, perms);
if (ram->ram_addr == -1)
// out of memory
return NULL;
@ -68,7 +68,7 @@ MemoryRegion *memory_map_ptr(struct uc_struct *uc, hwaddr begin, size_t size, ui
{
MemoryRegion *ram = g_new(MemoryRegion, 1);
memory_region_init_ram_ptr(uc, ram, NULL, "pc.ram", size, ptr);
memory_region_init_ram_ptr(uc, ram, "pc.ram", size, ptr);
ram->perms = perms;
if (ram->ram_addr == -1)
// out of memory
@ -121,6 +121,9 @@ int memory_free(struct uc_struct *uc)
mr->enabled = false;
memory_region_del_subregion(get_system_memory(uc), mr);
mr->destructor(mr);
/* destroy subregion */
g_free((void *)(mr->name));
g_free(mr);
}
return 0;
@ -765,7 +768,6 @@ static void memory_region_destructor_ram_from_ptr(MemoryRegion *mr)
}
void memory_region_init(struct uc_struct *uc, MemoryRegion *mr,
void *owner,
const char *name,
uint64_t size)
{
@ -903,13 +905,12 @@ static bool memory_region_dispatch_write(MemoryRegion *mr,
}
void memory_region_init_io(struct uc_struct *uc, MemoryRegion *mr,
void *owner,
const MemoryRegionOps *ops,
void *opaque,
const char *name,
uint64_t size)
{
memory_region_init(uc, mr, owner, name, size);
memory_region_init(uc, mr, name, size);
mr->ops = ops;
mr->opaque = opaque;
mr->terminates = true;
@ -917,12 +918,11 @@ void memory_region_init_io(struct uc_struct *uc, MemoryRegion *mr,
}
void memory_region_init_ram(struct uc_struct *uc, MemoryRegion *mr,
void *owner,
const char *name,
uint64_t size,
uint32_t perms)
{
memory_region_init(uc, mr, owner, name, size);
memory_region_init(uc, mr, name, size);
mr->ram = true;
if (!(perms & UC_PROT_WRITE)) {
mr->readonly = true;
@ -934,12 +934,11 @@ void memory_region_init_ram(struct uc_struct *uc, MemoryRegion *mr,
}
void memory_region_init_ram_ptr(struct uc_struct *uc, MemoryRegion *mr,
void *owner,
const char *name,
uint64_t size,
void *ptr)
{
memory_region_init(uc, mr, owner, name, size);
memory_region_init(uc, mr, name, size);
mr->ram = true;
mr->terminates = true;
mr->destructor = memory_region_destructor_ram_from_ptr;
@ -955,13 +954,12 @@ void memory_region_set_skip_dump(MemoryRegion *mr)
}
void memory_region_init_alias(struct uc_struct *uc, MemoryRegion *mr,
void *owner,
const char *name,
MemoryRegion *orig,
hwaddr offset,
uint64_t size)
{
memory_region_init(uc, mr, owner, name, size);
memory_region_init(uc, mr, name, size);
memory_region_ref(orig);
mr->destructor = memory_region_destructor_alias;
mr->alias = orig;

8
qemu/target-i386/cpu.c
View File

@ -30,9 +30,11 @@
#include "hw/hw.h"
#include "sysemu/sysemu.h"
#if 0
#ifndef CONFIG_USER_ONLY
#include "hw/i386/apic_internal.h"
#endif
#endif
#include "uc_priv.h"
/* Cache topology CPUID constants: */
@ -2147,6 +2149,7 @@ static void x86_cpu_reset(CPUState *s)
memset(env->mtrr_var, 0, sizeof(env->mtrr_var));
memset(env->mtrr_fixed, 0, sizeof(env->mtrr_fixed));
#if 0
#if !defined(CONFIG_USER_ONLY)
/* We hard-wire the BSP to the first CPU. */
if (s->cpu_index == 0) {
@ -2155,14 +2158,17 @@ static void x86_cpu_reset(CPUState *s)
s->halted = !cpu_is_bsp(cpu);
#endif
#endif
}
#if 0
#ifndef CONFIG_USER_ONLY
bool cpu_is_bsp(X86CPU *cpu)
{
return (cpu_get_apic_base((&cpu->env)->uc, cpu->apic_state) & MSR_IA32_APICBASE_BSP) != 0;
}
#endif
#endif
static void mce_init(X86CPU *cpu)
{
@ -2367,7 +2373,9 @@ static bool x86_cpu_has_work(CPUState *cs)
#if !defined(CONFIG_USER_ONLY)
if (cs->interrupt_request & CPU_INTERRUPT_POLL) {
#if 0
apic_poll_irq(cpu->apic_state);
#endif
cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL);
}
#endif

2
qemu/target-i386/cpu.h
View File

@ -1279,9 +1279,11 @@ void optimize_flags_init(struct uc_struct *);
#include "exec/cpu-all.h"
#include "svm.h"
#if 0
#if !defined(CONFIG_USER_ONLY)
#include "hw/i386/apic.h"
#endif
#endif
#include "exec/exec-all.h"

9
qemu/target-i386/helper.c
View File

@ -1061,7 +1061,10 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
cpu_restore_state(cs, cs->mem_io_pc);
#if 0
/* do nothing */
apic_handle_tpr_access_report(cpu->apic_state, env->eip, access);
#endif
}
#endif /* !CONFIG_USER_ONLY */
@ -1113,12 +1116,18 @@ void do_cpu_init(X86CPU *cpu)
offsetof(CPUX86State, start_init_save));
g_free(save);
#if 0
/* do nothing */
apic_init_reset(env->uc, cpu->apic_state);
#endif
}
void do_cpu_sipi(X86CPU *cpu)
{
#if 0
/* do nothing */
apic_sipi(cpu->apic_state);
#endif
}
#else
void do_cpu_init(X86CPU *cpu)

15
qemu/target-i386/misc_helper.c
View File

@ -112,7 +112,9 @@ target_ulong helper_read_crN(CPUX86State *env, int reg)
break;
case 8:
if (!(env->hflags2 & HF2_VINTR_MASK)) {
val = cpu_get_apic_tpr(env->uc, x86_env_get_cpu(env)->apic_state);
/* val = cpu_get_apic_tpr(env->uc, x86_env_get_cpu(env)->apic_state);
cpu_get_apic_tpr() always return 0 when apic_state is NULL. */
val = 0;
} else {
val = env->v_tpr;
}
@ -135,9 +137,12 @@ void helper_write_crN(CPUX86State *env, int reg, target_ulong t0)
cpu_x86_update_cr4(env, (uint32_t)t0);
break;
case 8:
#if 0
/* do nothing when apic_state is NULL. */
if (!(env->hflags2 & HF2_VINTR_MASK)) {
cpu_set_apic_tpr(env->uc, x86_env_get_cpu(env)->apic_state, (uint8_t)t0);
}
#endif
env->v_tpr = t0 & 0x0f;
break;
default:
@ -245,7 +250,10 @@ void helper_wrmsr(CPUX86State *env)
env->sysenter_eip = val;
break;
case MSR_IA32_APICBASE:
#if 0
/* do nothing when apic_state is NULL. */
cpu_set_apic_base(env->uc, x86_env_get_cpu(env)->apic_state, val);
#endif
break;
case MSR_EFER:
{
@ -396,7 +404,10 @@ void helper_rdmsr(CPUX86State *env)
val = env->sysenter_eip;
break;
case MSR_IA32_APICBASE:
val = cpu_get_apic_base(env->uc, x86_env_get_cpu(env)->apic_state);
/* val = cpu_get_apic_base(env->uc, x86_env_get_cpu(env)->apic_state);
cpu_get_apic_base() always return MSR_IA32_APICBASE_BSP
when apic_state is NULL.*/
val = MSR_IA32_APICBASE_BSP;
break;
case MSR_EFER:
val = env->efer;

8
qemu/target-i386/seg_helper.c
View File

@ -1296,7 +1296,10 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
#if !defined(CONFIG_USER_ONLY)
if (interrupt_request & CPU_INTERRUPT_POLL) {
cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
#if 0
/* do nothing */
apic_poll_irq(cpu->apic_state);
#endif
}
#endif
if (interrupt_request & CPU_INTERRUPT_SIPI) {
@ -1328,7 +1331,10 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0);
cs->interrupt_request &= ~(CPU_INTERRUPT_HARD |
CPU_INTERRUPT_VIRQ);
intno = cpu_get_pic_interrupt(env);
/* intno = cpu_get_pic_interrupt(env);
cpu_get_pic_interrupt() always return 0
when apic_state is NULL.*/
intno = 0;
qemu_log_mask(CPU_LOG_TB_IN_ASM,
"Servicing hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);