Invalidate tb cache once mapping is removed
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2849bc010a
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@ -1018,11 +1018,13 @@ static void uc_invalidate_tb(struct uc_struct *uc, uint64_t start_addr, size_t l
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return;
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}
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// GPA to GVA
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// GPA to ram addr
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// https://raw.githubusercontent.com/android/platform_external_qemu/master/docs/QEMU-MEMORY-MANAGEMENT.TXT
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// start_addr : GPA
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// addr: GVA
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// start (returned): ram addr
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// (GPA -> HVA via memory_region_get_ram_addr(mr) + GPA + block->host,
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// HVA->HPA via host mmu)
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// GVA -> GPA via tlb & softmmu
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// HVA -> HPA via host mmu)
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start = get_page_addr_code(uc->cpu->env_ptr, start_addr) & (target_ulong)(-1);
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uc->nested_level--;
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@ -153,10 +153,13 @@ void memory_unmap(struct uc_struct *uc, MemoryRegion *mr)
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int i;
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hwaddr addr;
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// Make sure all pages associated with the MemoryRegion are flushed
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// Only need to do this if we are in a running state
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if (uc->cpu) {
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for (addr = mr->addr; addr < mr->end; addr += uc->target_page_size) {
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// We also need to remove all tb cache
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uc->uc_invalidate_tb(uc, mr->addr, mr->size);
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// Make sure all pages associated with the MemoryRegion are flushed
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// Only need to do this if we are in a running state
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for (addr = mr->addr; (int64_t)(mr->end - addr) > 0; addr += uc->target_page_size) {
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tlb_flush_page(uc->cpu, addr);
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}
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}
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@ -2,6 +2,7 @@
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#include "unicorn/unicorn.h"
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#include "unicorn_test.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include <stdio.h>
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const uint64_t code_start = 0x1000;
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@ -473,6 +474,55 @@ static void test_arm64_mmu(void)
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free(data);
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}
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static void test_arm64_pc_wrap(void)
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{
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uc_engine *uc;
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// add x1 x2
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char add_x1_x2[] = "\x20\x00\x02\x8b";
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// add x1 x3
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char add_x1_x3[] = "\x20\x00\x03\x8b";
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uint64_t x0, x1, x2, x3;
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uint64_t pc = 0xFFFFFFFFFFFFFFFCULL;
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uint64_t page = 0xFFFFFFFFFFFFF000ULL;
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OK(uc_open(UC_ARCH_ARM64, UC_MODE_ARM, &uc));
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OK(uc_mem_map(uc, page, 4096, UC_PROT_READ | UC_PROT_EXEC));
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OK(uc_mem_write(uc, pc, add_x1_x2, sizeof(add_x1_x2) - 1));
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x1 = 1;
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x2 = 2;
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OK(uc_reg_write(uc, UC_ARM64_REG_X1, &x1));
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OK(uc_reg_write(uc, UC_ARM64_REG_X2, &x2));
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OK(uc_emu_start(uc, pc, pc + 4, 0, 1));
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OK(uc_mem_unmap(uc, page, 4096));
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OK(uc_reg_read(uc, UC_ARM64_REG_X0, &x0));
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TEST_CHECK( (x0 == 1 + 2) );
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OK(uc_mem_map(uc, page, 4096, UC_PROT_READ | UC_PROT_EXEC));
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OK(uc_mem_write(uc, pc, add_x1_x3, sizeof(add_x1_x3) - 1));
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x1 = 5;
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x2 = 0;
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x3 = 5;
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OK(uc_reg_write(uc, UC_ARM64_REG_X1, &x1));
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OK(uc_reg_write(uc, UC_ARM64_REG_X2, &x2));
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OK(uc_reg_write(uc, UC_ARM64_REG_X3, &x3));
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OK(uc_emu_start(uc, pc, pc + 4, 0, 1));
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OK(uc_mem_unmap(uc, page, 4096));
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OK(uc_reg_read(uc, UC_ARM64_REG_X0, &x0));
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TEST_CHECK( (x0 == 5 + 5) );
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OK(uc_close(uc));
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}
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TEST_LIST = {{"test_arm64_until", test_arm64_until},
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{"test_arm64_code_patching", test_arm64_code_patching},
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{"test_arm64_code_patching_count", test_arm64_code_patching_count},
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@ -487,4 +537,5 @@ TEST_LIST = {{"test_arm64_until", test_arm64_until},
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{"test_arm64_block_invalid_mem_read_write_sync",
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test_arm64_block_invalid_mem_read_write_sync},
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{"test_arm64_mmu", test_arm64_mmu},
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{"test_arm64_pc_wrap", test_arm64_pc_wrap},
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{NULL, NULL}};
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