Fix RISCV test_riscv32_fp_move test
RISCV FP registers are 64-bit in size, even in 32-bit mode, because they can hold doubles. The test even uses the double-precision instruction fmv.d. Thus, the reads should be reading 64-bit registers.
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@ -222,8 +222,8 @@ static void test_riscv32_fp_move(void)
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uc_engine *uc;
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uc_engine *uc;
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char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
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char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
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uint32_t r_f1 = 0x1234;
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uint64_t r_f1 = 0x123456781a2b3c4dULL;
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uint32_t r_f3 = 0x5678;
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uint64_t r_f3 = 0x56780246aaaabbbbULL;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
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sizeof(code) - 1);
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sizeof(code) - 1);
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@ -238,8 +238,8 @@ static void test_riscv32_fp_move(void)
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OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3));
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OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3));
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TEST_CHECK(r_f1 == 0x1234);
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TEST_CHECK(r_f1 == 0x123456781a2b3c4dULL);
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TEST_CHECK(r_f3 == 0x1234);
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TEST_CHECK(r_f3 == 0x123456781a2b3c4dULL);
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uc_close(uc);
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uc_close(uc);
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}
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}
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@ -249,8 +249,8 @@ static void test_riscv64_fp_move(void)
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uc_engine *uc;
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uc_engine *uc;
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char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
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char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
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uint64_t r_f1 = 0x12341234;
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uint64_t r_f1 = 0x123456781a2b3c4dULL;
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uint64_t r_f3 = 0x56785678;
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uint64_t r_f3 = 0x56780246aaaabbbbULL;
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
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sizeof(code) - 1);
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sizeof(code) - 1);
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@ -265,8 +265,8 @@ static void test_riscv64_fp_move(void)
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OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F1, &r_f1));
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OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3));
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OK(uc_reg_read(uc, UC_RISCV_REG_F3, &r_f3));
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TEST_CHECK(r_f1 == 0x12341234);
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TEST_CHECK(r_f1 == 0x123456781a2b3c4dULL);
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TEST_CHECK(r_f3 == 0x12341234);
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TEST_CHECK(r_f3 == 0x123456781a2b3c4dULL);
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uc_close(uc);
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uc_close(uc);
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}
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}
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