added tests with enter/leave
This commit is contained in:
samothtronicien
parent
1ecc5abdbc
commit
ae8e34173a
@ -13,7 +13,7 @@ endif
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ALL_TESTS = test_sanity test_x86 test_mem_map test_mem_high test_mem_map_ptr \
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test_tb_x86 test_multihook test_pc_change test_x86_soft_paging \
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test_hookcounts test_hang test_x86_shl
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test_hookcounts test_hang test_x86_shl_enter_leave
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.PHONY: all
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all: ${ALL_TESTS}
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@ -36,7 +36,7 @@ test: ${ALL_TESTS}
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./test_x86_soft_paging
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./test_hookcounts
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./test_hang
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./test_x86_shl
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./test_x86_shl_enter_leave
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test_sanity: test_sanity.c
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test_x86: test_x86.c
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@ -49,7 +49,7 @@ test_pc_change: test_pc_change.c
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test_x86_soft_paging: test_x86_soft_paging.c
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test_hookcounts: test_hookcounts.c
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test_hang: test_hang.c
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test_x86_shl: test_x86_shl.c
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test_x86_shl_enter_leave: test_x86_shl_enter_leave.c
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${ALL_TESTS}:
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${CC} ${CFLAGS} -o $@ $^
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487
tests/unit/test_x86_shl_enter_leave.c
Normal file
487
tests/unit/test_x86_shl_enter_leave.c
Normal file
@ -0,0 +1,487 @@
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#include <stdint.h>
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#include <inttypes.h>
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#include "unicorn_test.h"
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#define OK(x) uc_assert_success(x)
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#define CF_MASK (1<<0)
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#define PF_MASK (1<<2)
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#define ZF_MASK (1<<6)
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#define SF_MASK (1<<7)
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#define OF_MASK (1<<11)
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#define ALL_MASK (OF_MASK|SF_MASK|ZF_MASK|PF_MASK|CF_MASK)
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#define NO_MASK 0xFFFFFFFF
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typedef struct _reg_value
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{
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uint32_t regId, regValue, mask;
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} reg_value;
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typedef struct _instruction
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{
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const char* asmStr;
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const uint8_t* code;
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uint32_t codeSize;
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const reg_value* values;
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uint32_t nbValues;
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uint32_t addr;
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} instruction;
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typedef struct _block
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{
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instruction* insts[255];
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uint32_t nbInsts;
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uint32_t size;
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} block;
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/******************************************************************************/
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#define CAT2(X, Y) X ## Y
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#define CAT(X, Y) CAT2(X, Y)
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#define ADD_INSTRUCTION(BLOCK, CODE_ASM, CODE, REGVALUES) \
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const uint8_t CAT(code, __LINE__)[] = CODE; \
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const reg_value CAT(regValues, __LINE__)[] = REGVALUES; \
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inst = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, CAT(regValues, __LINE__), sizeof(CAT(regValues, __LINE__)) / sizeof(reg_value)); \
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addInstructionToBlock(BLOCK, inst);
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#define V(...) { __VA_ARGS__ }
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/******************************************************************************/
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instruction* newInstruction(const uint8_t * _code, uint32_t _codeSize, const char* _asmStr, const reg_value* _values, uint32_t _nbValues);
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void addInstructionToBlock(block* _b, instruction* _i);
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uint32_t loadBlock(uc_engine *_uc, block* _block, uint32_t _at);
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void freeBlock(block* _block);
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const char* getRegisterName(uint32_t _regid);
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uint32_t getRegisterValue(uc_engine *uc, uint32_t _regid);
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instruction* getInstruction(block * _block, uint32_t _addr);
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/******************************************************************************/
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void hook_code_test_i386_shl(uc_engine *uc, uint64_t address, uint32_t size, void *user_data)
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{
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uint32_t i;
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block* b = (block*)user_data;
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instruction* currInst = getInstruction(b, (uint32_t)address);
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assert_true(currInst != NULL);
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print_message("|\teip=%08x - %s\n", (uint32_t)address, currInst->asmStr);
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for (i = 0; i < currInst->nbValues; i++)
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{
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if (currInst->values[i].regId == UC_X86_REG_INVALID) continue;
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uint32_t regValue = getRegisterValue(uc, currInst->values[i].regId);
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print_message("|\t\ttesting %s : ", getRegisterName(currInst->values[i].regId));
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assert_int_equal(regValue & currInst->values[i].mask, currInst->values[i].regValue);
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print_message("ok\n");
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}
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if (currInst->code[0] == 0xCC)
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OK(uc_emu_stop(uc));
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}
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bool hook_mem_invalid(uc_engine *uc, uc_mem_type type, uint64_t addr, int size, int64_t value, void *user_data)
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{
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switch (type)
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{
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default:
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print_message("hook_mem_invalid: UC_HOOK_MEM_INVALID type: %d at 0x%" PRIx64 "\n", type, addr); break;
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case UC_MEM_READ_UNMAPPED:
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print_message("hook_mem_invalid: Read from invalid memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break;
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case UC_MEM_WRITE_UNMAPPED:
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print_message("hook_mem_invalid: Write to invalid memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break;
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case UC_MEM_FETCH_PROT:
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print_message("hook_mem_invalid: Fetch from non-executable memory at 0x%" PRIx64 "\n", addr); break;
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case UC_MEM_WRITE_PROT:
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print_message("hook_mem_invalid: Write to non-writeable memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break;
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case UC_MEM_READ_PROT:
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print_message("hook_mem_invalid: Read from non-readable memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break;
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}
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return false;
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}
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#define ADDR_CODE 0x100000
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#define ADDR_STACK 0x200000
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static void test_i386_shl_cl(void **state)
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{
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uc_engine *uc;
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uc_hook trace1;
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// Initialize emulator in X86-32bit mode
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OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
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OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
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{
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block block;
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instruction* inst;
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block.nbInsts = 0;
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ADD_INSTRUCTION(&block, "mov ebx, 3Ch",
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V(0xBB, 0x3C, 0x00, 0x00, 0x00),
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V(V(UC_X86_REG_INVALID, 0x0, NO_MASK)));
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ADD_INSTRUCTION(&block, "mov cl, 2",
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V(0xB1, 0x02),
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V(V(UC_X86_REG_EBX, 0x3C, NO_MASK)));
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ADD_INSTRUCTION(&block, "shl ebx, cl",
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V(0xD3, 0xE3),
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V(V(UC_X86_REG_EBX, 0x3C, NO_MASK), V(UC_X86_REG_CL, 0x2, NO_MASK)));
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ADD_INSTRUCTION(&block, "lahf",
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V(0x9F),
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V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_CL, 0x2, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK)));
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ADD_INSTRUCTION(&block, "int3",
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V(0xCC),
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V(V(UC_X86_REG_AH, 0x4, PF_MASK), V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_CL, 0x2, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK)));
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loadBlock(uc, &block, ADDR_CODE);
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// initialize machine registers
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uint32_t zero = 0;
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OK(uc_reg_write(uc, UC_X86_REG_EAX, &zero));
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OK(uc_reg_write(uc, UC_X86_REG_EBX, &zero));
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OK(uc_reg_write(uc, UC_X86_REG_ECX, &zero));
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OK(uc_reg_write(uc, UC_X86_REG_EDX, &zero));
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OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &block, 1, 0));
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OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
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// emulate machine code in infinite time
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OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + block.size, 0, 0));
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freeBlock(&block);
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}
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uc_close(uc);
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}
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static void test_i386_shl_imm(void **state)
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{
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uc_engine *uc;
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uc_hook trace1;
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// Initialize emulator in X86-32bit mode
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OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
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OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
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{
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block block;
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instruction* inst;
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block.nbInsts = 0;
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ADD_INSTRUCTION(&block, "mov ebx, 3Ch",
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V(0xBB, 0x3C, 0x00, 0x00, 0x00),
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V(V(UC_X86_REG_INVALID, 0x0, NO_MASK)));
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ADD_INSTRUCTION(&block, "shl ebx, 2",
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V(0xC1, 0xE3, 0x02),
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V(V(UC_X86_REG_EBX, 0x3C, NO_MASK)));
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ADD_INSTRUCTION(&block, "lahf",
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V(0x9F),
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V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK)));
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ADD_INSTRUCTION(&block, "int3",
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V(0xCC),
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V(V(UC_X86_REG_AH, 0x4, PF_MASK), V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK)));
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loadBlock(uc, &block, ADDR_CODE);
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// initialize machine registers
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uint32_t zero = 0;
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OK(uc_reg_write(uc, UC_X86_REG_EAX, &zero));
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OK(uc_reg_write(uc, UC_X86_REG_EBX, &zero));
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OK(uc_reg_write(uc, UC_X86_REG_ECX, &zero));
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OK(uc_reg_write(uc, UC_X86_REG_EDX, &zero));
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OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &block, 1, 0));
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OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
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// emulate machine code in infinite time
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OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + block.size, 0, 0));
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freeBlock(&block);
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}
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uc_close(uc);
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}
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static void test_i386_enter_leave(void **state)
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{
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uc_engine *uc;
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uc_hook trace1;
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// Initialize emulator in X86-32bit mode
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OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
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OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
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OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL));
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{
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block block;
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instruction* inst;
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block.nbInsts = 0;
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ADD_INSTRUCTION(&block, "mov esp, 0x200000",
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V(0xBC, 0x00, 0x00, 0x20, 0x00),
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V(V(UC_X86_REG_INVALID, 0x0, NO_MASK)));
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ADD_INSTRUCTION(&block, "mov eax, 1",
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V(0xB8, 0x01, 0x00, 0x00, 0x00),
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V(V(UC_X86_REG_ESP, 0x200000, NO_MASK)));
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ADD_INSTRUCTION(&block, "call 0x100015",
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V(0xE8, 0x06, 0x00, 0x00, 0x00),
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V(V(UC_X86_REG_EAX, 0x1, NO_MASK), V(UC_X86_REG_ESP, 0x200000, NO_MASK)));
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ADD_INSTRUCTION(&block, "mov eax, 3",
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V(0xB8, 0x03, 0x00, 0x00, 0x00),
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V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
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ADD_INSTRUCTION(&block, "int3",
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V(0xCC),
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V(V(UC_X86_REG_EAX, 0x3, NO_MASK)));
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ADD_INSTRUCTION(&block, "enter 0x10,0",
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V(0xC8, 0x10, 0x00, 0x00),
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V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
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ADD_INSTRUCTION(&block, "mov eax, 2",
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V(0xB8, 0x02, 0x00, 0x00, 0x00),
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V(V(UC_X86_REG_ESP, 0x200000 - 4 - 4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK)));
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ADD_INSTRUCTION(&block, "leave",
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V(0xC9),
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V(V(UC_X86_REG_EAX, 0x2, NO_MASK), V(UC_X86_REG_INVALID, 0x0, NO_MASK)));
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ADD_INSTRUCTION(&block, "mov eax, 2",
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V(0xB8, 0x02, 0x00, 0x00, 0x00),
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V(V(UC_X86_REG_INVALID, 0x0, NO_MASK)));
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ADD_INSTRUCTION(&block, "ret",
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V(0xC3),
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V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
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loadBlock(uc, &block, ADDR_CODE);
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// initialize machine registers
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uint32_t zero = 0;
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OK(uc_reg_write(uc, UC_X86_REG_EAX, &zero));
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OK(uc_reg_write(uc, UC_X86_REG_EBX, &zero));
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OK(uc_reg_write(uc, UC_X86_REG_ECX, &zero));
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OK(uc_reg_write(uc, UC_X86_REG_EDX, &zero));
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OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &block, 1, 0));
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OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
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// emulate machine code in infinite time
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OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + block.size, 0, 0));
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freeBlock(&block);
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}
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uc_close(uc);
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}
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static void test_i386_enter_nested_leave(void **state)
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{
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uc_engine *uc;
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uc_hook trace1;
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// Initialize emulator in X86-32bit mode
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OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
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OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
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OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL));
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{
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block block;
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instruction* inst;
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block.nbInsts = 0;
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ADD_INSTRUCTION(&block, "mov esp, 0x200000",
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V(0xBC, 0x00, 0x00, 0x20, 0x00),
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V(V(UC_X86_REG_INVALID, 0x0, NO_MASK)));
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ADD_INSTRUCTION(&block, "mov eax, 1",
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V(0xB8, 0x01, 0x00, 0x00, 0x00),
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V(V(UC_X86_REG_ESP, 0x200000, NO_MASK)));
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ADD_INSTRUCTION(&block, "call 0x100015",
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V(0xE8, 0x06, 0x00, 0x00, 0x00),
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V(V(UC_X86_REG_EAX, 0x1, NO_MASK), V(UC_X86_REG_ESP, 0x200000, NO_MASK)));
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ADD_INSTRUCTION(&block, "mov eax, 3",
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V(0xB8, 0x03, 0x00, 0x00, 0x00),
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V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
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ADD_INSTRUCTION(&block, "int3",
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V(0xCC),
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V(V(UC_X86_REG_EAX, 0x3, NO_MASK)));
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ADD_INSTRUCTION(&block, "enter 0x10,1",
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V(0xC8, 0x10, 0x00, 0x01),
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V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
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ADD_INSTRUCTION(&block, "mov eax, 2",
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V(0xB8, 0x02, 0x00, 0x00, 0x00),
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V(V(UC_X86_REG_ESP, 0x200000 - 4 - 2*4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK)));
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ADD_INSTRUCTION(&block, "leave",
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V(0xC9),
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V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
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ADD_INSTRUCTION(&block, "ret",
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V(0xC3),
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V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
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loadBlock(uc, &block, ADDR_CODE);
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// initialize machine registers
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uint32_t zero = 0;
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OK(uc_reg_write(uc, UC_X86_REG_EAX, &zero));
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OK(uc_reg_write(uc, UC_X86_REG_EBX, &zero));
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OK(uc_reg_write(uc, UC_X86_REG_ECX, &zero));
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OK(uc_reg_write(uc, UC_X86_REG_EDX, &zero));
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OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &block, 1, 0));
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OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
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// emulate machine code in infinite time
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OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + block.size, 0, 0));
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freeBlock(&block);
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}
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uc_close(uc);
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}
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/******************************************************************************/
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int main(void) {
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const struct CMUnitTest tests[] = {
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cmocka_unit_test(test_i386_shl_cl),
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cmocka_unit_test(test_i386_shl_imm),
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cmocka_unit_test(test_i386_enter_leave),
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cmocka_unit_test(test_i386_enter_nested_leave),
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};
|
||||
return cmocka_run_group_tests(tests, NULL, NULL);
|
||||
}
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
instruction* newInstruction(const uint8_t * _code, uint32_t _codeSize, const char* _asmStr, const reg_value* _values, uint32_t _nbValues)
|
||||
{
|
||||
instruction* inst = (instruction*)malloc(sizeof(instruction));
|
||||
|
||||
inst->asmStr = _asmStr;
|
||||
inst->code = _code;
|
||||
inst->codeSize = _codeSize;
|
||||
inst->values = _values;
|
||||
inst->nbValues = _nbValues;
|
||||
|
||||
return inst;
|
||||
}
|
||||
|
||||
void addInstructionToBlock(block* _b, instruction* _i)
|
||||
{
|
||||
_b->insts[_b->nbInsts++] = _i;
|
||||
}
|
||||
|
||||
uint32_t loadBlock(uc_engine *_uc, block* _block, uint32_t _at)
|
||||
{
|
||||
uint32_t i, j, offset;
|
||||
|
||||
for (i = 0, offset = 0; i < _block->nbInsts; i++)
|
||||
{
|
||||
const uint32_t codeSize = _block->insts[i]->codeSize;
|
||||
const uint8_t* code = _block->insts[i]->code;
|
||||
_block->insts[i]->addr = _at + offset;
|
||||
print_message("load: %08X: ", _block->insts[i]->addr);
|
||||
for (j = 0; j < codeSize; j++) print_message("%02X ", code[j]);
|
||||
for (j = 0; j < 15 - codeSize; j++) print_message(" ");
|
||||
print_message("%s\n", _block->insts[i]->asmStr);
|
||||
OK(uc_mem_write(_uc, _at + offset, code, codeSize));
|
||||
offset += codeSize;
|
||||
}
|
||||
_block->size = offset;
|
||||
return offset;
|
||||
}
|
||||
|
||||
void freeBlock(block* _block)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < _block->nbInsts; i++)
|
||||
free(_block->insts[i]);
|
||||
}
|
||||
|
||||
instruction* getInstruction(block* _block, uint32_t _addr)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0; i < _block->nbInsts; i++)
|
||||
{
|
||||
if (_block->insts[i]->addr == _addr)
|
||||
return _block->insts[i];
|
||||
}
|
||||
return NULL;
|
||||
}
|
||||
|
||||
const char* getRegisterName(uint32_t _regid)
|
||||
{
|
||||
switch (_regid)
|
||||
{
|
||||
//8
|
||||
case UC_X86_REG_AH: return "AH";
|
||||
case UC_X86_REG_AL: return "AL";
|
||||
case UC_X86_REG_BH: return "BH";
|
||||
case UC_X86_REG_BL: return "BL";
|
||||
case UC_X86_REG_CL: return "CL";
|
||||
case UC_X86_REG_CH: return "CH";
|
||||
case UC_X86_REG_DH: return "DH";
|
||||
case UC_X86_REG_DL: return "DL";
|
||||
//16
|
||||
case UC_X86_REG_AX: return "AX";
|
||||
case UC_X86_REG_BX: return "BX";
|
||||
case UC_X86_REG_CX: return "CX";
|
||||
case UC_X86_REG_DX: return "DX";
|
||||
//32
|
||||
case UC_X86_REG_EAX: return "EAX";
|
||||
case UC_X86_REG_EBX: return "EBX";
|
||||
case UC_X86_REG_ECX: return "ECX";
|
||||
case UC_X86_REG_EDX: return "EDX";
|
||||
case UC_X86_REG_EDI: return "EDI";
|
||||
case UC_X86_REG_ESI: return "ESI";
|
||||
case UC_X86_REG_EBP: return "EBP";
|
||||
case UC_X86_REG_ESP: return "ESP";
|
||||
case UC_X86_REG_EIP: return "EIP";
|
||||
case UC_X86_REG_EFLAGS: return "EFLAGS";
|
||||
|
||||
default: fail();
|
||||
}
|
||||
return "UNKNOWN";
|
||||
}
|
||||
|
||||
uint32_t getRegisterValue(uc_engine *uc, uint32_t _regid)
|
||||
{
|
||||
switch (_regid)
|
||||
{
|
||||
//8
|
||||
case UC_X86_REG_AH: case UC_X86_REG_AL:
|
||||
case UC_X86_REG_BH: case UC_X86_REG_BL:
|
||||
case UC_X86_REG_CL: case UC_X86_REG_CH:
|
||||
case UC_X86_REG_DH: case UC_X86_REG_DL:
|
||||
{
|
||||
uint8_t val = 0;
|
||||
OK(uc_reg_read(uc, _regid, &val));
|
||||
return val;
|
||||
}
|
||||
//16
|
||||
case UC_X86_REG_AX: case UC_X86_REG_BX:
|
||||
case UC_X86_REG_CX: case UC_X86_REG_DX:
|
||||
{
|
||||
uint16_t val = 0;
|
||||
OK(uc_reg_read(uc, _regid, &val));
|
||||
return val;
|
||||
}
|
||||
//32
|
||||
case UC_X86_REG_EAX: case UC_X86_REG_EBX:
|
||||
case UC_X86_REG_ECX: case UC_X86_REG_EDX:
|
||||
case UC_X86_REG_EDI: case UC_X86_REG_ESI:
|
||||
case UC_X86_REG_EBP: case UC_X86_REG_ESP:
|
||||
case UC_X86_REG_EIP: case UC_X86_REG_EFLAGS:
|
||||
{
|
||||
uint32_t val = 0;
|
||||
OK(uc_reg_read(uc, _regid, &val));
|
||||
return val;
|
||||
}
|
||||
|
||||
default: fail();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user