This commit is contained in:
feliam 2016-03-09 18:27:59 -03:00
parent ff66a72d7b
commit a5f2a64de5

View File

@ -156,7 +156,6 @@ def uc_arch_supported(query):
return _uc.uc_arch_supported(query) return _uc.uc_arch_supported(query)
class uc_x86_mmr(ctypes.Structure): class uc_x86_mmr(ctypes.Structure):
'''Memory-Management Register for instructions IDTR, GDTR, LDTR, TR.''' '''Memory-Management Register for instructions IDTR, GDTR, LDTR, TR.'''
_fields_ = [ _fields_ = [
@ -166,6 +165,7 @@ class uc_x86_mmr(ctypes.Structure):
("flags", ctypes.c_uint32), # not used by GDTR and IDTR ("flags", ctypes.c_uint32), # not used by GDTR and IDTR
] ]
class uc_x86_float80(ctypes.Structure): class uc_x86_float80(ctypes.Structure):
'''Float80''' '''Float80'''
_fields_ = [ _fields_ = [
@ -173,6 +173,7 @@ class uc_x86_float80(ctypes.Structure):
("exponent", ctypes.c_uint16), ("exponent", ctypes.c_uint16),
] ]
class Uc(object): class Uc(object):
def __init__(self, arch, mode): def __init__(self, arch, mode):
# verify version compatibility with the core before doing anything # verify version compatibility with the core before doing anything