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Merge branch 'master' into java_dev

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This commit is contained in:
Chris Eagle 2015-09-03 22:34:00 -07:00
commit a53eae3a29
13 changed files with 206 additions and 166 deletions
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24
bindings/go/unicorn/unicorn_const.go
View File

@ -41,20 +41,22 @@ const (
UC_ERR_VERSION = 5
UC_ERR_MEM_READ = 6
UC_ERR_MEM_WRITE = 7
UC_ERR_CODE_INVALID = 8
UC_ERR_HOOK = 9
UC_ERR_INSN_INVALID = 10
UC_ERR_MAP = 11
UC_ERR_WRITE_PROT = 12
UC_ERR_READ_PROT = 13
UC_ERR_EXEC_PROT = 14
UC_ERR_INVAL = 15
UC_ERR_MEM_FETCH = 8
UC_ERR_CODE_INVALID = 9
UC_ERR_HOOK = 10
UC_ERR_INSN_INVALID = 11
UC_ERR_MAP = 12
UC_ERR_WRITE_PROT = 13
UC_ERR_READ_PROT = 14
UC_ERR_EXEC_PROT = 15
UC_ERR_INVAL = 16
UC_MEM_READ = 16
UC_MEM_WRITE = 17
UC_MEM_READ_WRITE = 18
UC_MEM_WRITE_PROT = 19
UC_MEM_READ_PROT = 20
UC_MEM_EXEC_PROT = 21
UC_MEM_EXEC = 19
UC_MEM_WRITE_PROT = 20
UC_MEM_READ_PROT = 21
UC_MEM_EXEC_PROT = 22
UC_HOOK_INTR = 32
UC_HOOK_INSN = 33
UC_HOOK_CODE = 34

24
bindings/python/unicorn/unicorn_const.py
View File

@ -39,20 +39,22 @@ UC_ERR_MODE = 4
UC_ERR_VERSION = 5
UC_ERR_MEM_READ = 6
UC_ERR_MEM_WRITE = 7
UC_ERR_CODE_INVALID = 8
UC_ERR_HOOK = 9
UC_ERR_INSN_INVALID = 10
UC_ERR_MAP = 11
UC_ERR_WRITE_PROT = 12
UC_ERR_READ_PROT = 13
UC_ERR_EXEC_PROT = 14
UC_ERR_INVAL = 15
UC_ERR_MEM_FETCH = 8
UC_ERR_CODE_INVALID = 9
UC_ERR_HOOK = 10
UC_ERR_INSN_INVALID = 11
UC_ERR_MAP = 12
UC_ERR_WRITE_PROT = 13
UC_ERR_READ_PROT = 14
UC_ERR_EXEC_PROT = 15
UC_ERR_INVAL = 16
UC_MEM_READ = 16
UC_MEM_WRITE = 17
UC_MEM_READ_WRITE = 18
UC_MEM_WRITE_PROT = 19
UC_MEM_READ_PROT = 20
UC_MEM_EXEC_PROT = 21
UC_MEM_EXEC = 19
UC_MEM_WRITE_PROT = 20
UC_MEM_READ_PROT = 21
UC_MEM_EXEC_PROT = 22
UC_HOOK_INTR = 32
UC_HOOK_INSN = 33
UC_HOOK_CODE = 34

2
include/unicorn/unicorn.h
View File

@ -113,6 +113,7 @@ typedef enum uc_err {
UC_ERR_VERSION, // Unsupported version (bindings)
UC_ERR_MEM_READ, // Quit emulation due to invalid memory READ: uc_emu_start()
UC_ERR_MEM_WRITE, // Quit emulation due to invalid memory WRITE: uc_emu_start()
UC_ERR_MEM_FETCH, // Quit emulation due to invalid memory FETCH: uc_emu_start()
UC_ERR_CODE_INVALID, // Quit emulation due to invalid code address: uc_emu_start()
UC_ERR_HOOK, // Invalid hook type: uc_hook_add()
UC_ERR_INSN_INVALID, // Quit emulation due to invalid instruction: uc_emu_start()
@ -152,6 +153,7 @@ typedef enum uc_mem_type {
UC_MEM_READ = 16, // Memory is read from
UC_MEM_WRITE, // Memory is written to
UC_MEM_READ_WRITE, // Memory is accessed (either READ or WRITE)
UC_MEM_EXEC, // Unmapped memory is fetched, but unmapped (invalid memory access)
UC_MEM_WRITE_PROT, // write to write protected memory
UC_MEM_READ_PROT, // read from read protected memory
UC_MEM_EXEC_PROT, // fetch from non-executable memory

48
qemu/softmmu_template.h
View File

@ -182,8 +182,24 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
MemoryRegion *mr = memory_mapping(uc, addr);
#if defined(SOFTMMU_CODE_ACCESS)
// Unicorn: callback on fetch from unmapped memory
if (mr == NULL) { // memory is not mapped
if (uc->hook_mem_idx != 0 && ((uc_cb_eventmem_t)uc->hook_callbacks[uc->hook_mem_idx].callback)(
uc, UC_MEM_EXEC, addr, DATA_SIZE, 0,
uc->hook_callbacks[uc->hook_mem_idx].user_data)) {
env->invalid_error = UC_ERR_OK;
mr = memory_mapping(uc, addr); // FIXME: what if mr is still NULL at this time?
} else {
env->invalid_addr = addr;
env->invalid_error = UC_ERR_MEM_FETCH;
// printf("***** Invalid fetch (unmapped memory) at " TARGET_FMT_lx "\n", addr);
cpu_exit(uc->current_cpu);
return 0;
}
}
// Unicorn: callback on fetch from NX
if (mr != NULL && !(mr->perms & UC_PROT_EXEC)) { //non-executable
if (mr != NULL && !(mr->perms & UC_PROT_EXEC)) { // non-executable
if (uc->hook_mem_idx != 0 && ((uc_cb_eventmem_t)uc->hook_callbacks[uc->hook_mem_idx].callback)(
uc, UC_MEM_EXEC_PROT, addr, DATA_SIZE, 0,
uc->hook_callbacks[uc->hook_mem_idx].user_data)) {
@ -199,7 +215,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
#endif
// Unicorn: callback on memory read
if (env->uc->hook_mem_read && READ_ACCESS_TYPE == MMU_DATA_LOAD) {
if (READ_ACCESS_TYPE == MMU_DATA_LOAD && env->uc->hook_mem_read) {
struct hook_struct *trace = hook_find(env->uc, UC_HOOK_MEM_READ, addr);
if (trace) {
((uc_cb_hookmem_t)trace->callback)(env->uc, UC_MEM_READ,
@ -208,7 +224,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
}
// Unicorn: callback on invalid memory
if (env->uc->hook_mem_idx && mr == NULL) {
if (READ_ACCESS_TYPE == MMU_DATA_LOAD && env->uc->hook_mem_idx && mr == NULL) {
if (!((uc_cb_eventmem_t)env->uc->hook_callbacks[env->uc->hook_mem_idx].callback)(
env->uc, UC_MEM_READ, addr, DATA_SIZE, 0,
env->uc->hook_callbacks[env->uc->hook_mem_idx].user_data)) {
@ -224,7 +240,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
}
// Unicorn: callback on non-readable memory
if (mr != NULL && !(mr->perms & UC_PROT_READ)) { //non-readable
if (READ_ACCESS_TYPE == MMU_DATA_LOAD && mr != NULL && !(mr->perms & UC_PROT_READ)) { //non-readable
if (uc->hook_mem_idx != 0 && ((uc_cb_eventmem_t)uc->hook_callbacks[uc->hook_mem_idx].callback)(
uc, UC_MEM_READ_PROT, addr, DATA_SIZE, 0,
uc->hook_callbacks[uc->hook_mem_idx].user_data)) {
@ -340,8 +356,24 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
MemoryRegion *mr = memory_mapping(uc, addr);
#if defined(SOFTMMU_CODE_ACCESS)
// Unicorn: callback on fetch from unmapped memory
if (mr == NULL) { // memory is not mapped
if (uc->hook_mem_idx != 0 && ((uc_cb_eventmem_t)uc->hook_callbacks[uc->hook_mem_idx].callback)(
uc, UC_MEM_EXEC, addr, DATA_SIZE, 0,
uc->hook_callbacks[uc->hook_mem_idx].user_data)) {
env->invalid_error = UC_ERR_OK;
mr = memory_mapping(uc, addr); // FIXME: what if mr is still NULL at this time?
} else {
env->invalid_addr = addr;
env->invalid_error = UC_ERR_MEM_FETCH;
// printf("***** Invalid fetch (unmapped memory) at " TARGET_FMT_lx "\n", addr);
cpu_exit(uc->current_cpu);
return 0;
}
}
// Unicorn: callback on fetch from NX
if (mr != NULL && !(mr->perms & UC_PROT_EXEC)) { //non-executable
if (mr != NULL && !(mr->perms & UC_PROT_EXEC)) { // non-executable
if (uc->hook_mem_idx != 0 && ((uc_cb_eventmem_t)uc->hook_callbacks[uc->hook_mem_idx].callback)(
uc, UC_MEM_EXEC_PROT, addr, DATA_SIZE, 0,
uc->hook_callbacks[uc->hook_mem_idx].user_data)) {
@ -357,7 +389,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
#endif
// Unicorn: callback on memory read
if (env->uc->hook_mem_read && READ_ACCESS_TYPE == MMU_DATA_LOAD) {
if (READ_ACCESS_TYPE == MMU_DATA_LOAD && env->uc->hook_mem_read) {
struct hook_struct *trace = hook_find(env->uc, UC_HOOK_MEM_READ, addr);
if (trace) {
((uc_cb_hookmem_t)trace->callback)(env->uc, UC_MEM_READ,
@ -366,7 +398,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
}
// Unicorn: callback on invalid memory
if (env->uc->hook_mem_idx && mr == NULL) {
if (READ_ACCESS_TYPE == MMU_DATA_LOAD && env->uc->hook_mem_idx && mr == NULL) {
if (!((uc_cb_eventmem_t)env->uc->hook_callbacks[env->uc->hook_mem_idx].callback)(
env->uc, UC_MEM_READ, addr, DATA_SIZE, 0,
env->uc->hook_callbacks[env->uc->hook_mem_idx].user_data)) {
@ -382,7 +414,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
}
// Unicorn: callback on non-readable memory
if (mr != NULL && !(mr->perms & UC_PROT_READ)) { //non-readable
if (READ_ACCESS_TYPE == MMU_DATA_LOAD && mr != NULL && !(mr->perms & UC_PROT_READ)) { //non-readable
if (uc->hook_mem_idx != 0 && ((uc_cb_eventmem_t)uc->hook_callbacks[uc->hook_mem_idx].callback)(
uc, UC_MEM_READ_PROT, addr, DATA_SIZE, 0,
uc->hook_callbacks[uc->hook_mem_idx].user_data)) {

6
qemu/target-arm/unicorn_aarch64.c
View File

@ -67,15 +67,15 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
CPUState *mycpu = first_cpu;
if (regid >= UC_ARM64_REG_X0 && regid <= UC_ARM64_REG_X28)
ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0] = *(int64_t *)value;
ARM_CPU(uc, mycpu)->env.xregs[regid - UC_ARM64_REG_X0] = *(uint64_t *)value;
else {
switch(regid) {
default: break;
case UC_ARM64_REG_X29:
ARM_CPU(uc, mycpu)->env.xregs[29] = *(int64_t *)value;
ARM_CPU(uc, mycpu)->env.xregs[29] = *(uint64_t *)value;
break;
case UC_ARM64_REG_X30:
ARM_CPU(uc, mycpu)->env.xregs[30] = *(int64_t *)value;
ARM_CPU(uc, mycpu)->env.xregs[30] = *(uint64_t *)value;
break;
case UC_ARM64_REG_PC:
ARM_CPU(uc, mycpu)->env.pc = *(uint64_t *)value;

8
qemu/target-arm/unicorn_arm.c
View File

@ -88,20 +88,20 @@ int arm_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
case UC_MODE_ARM:
case UC_MODE_THUMB:
if (regid >= UC_ARM_REG_R0 && regid <= UC_ARM_REG_R12)
ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0] = *(int32_t *)value;
ARM_CPU(uc, mycpu)->env.regs[regid - UC_ARM_REG_R0] = *(uint32_t *)value;
else {
switch(regid) {
//case UC_ARM_REG_SP:
case UC_ARM_REG_R13:
ARM_CPU(uc, mycpu)->env.regs[13] = *(int32_t *)value;
ARM_CPU(uc, mycpu)->env.regs[13] = *(uint32_t *)value;
break;
//case UC_ARM_REG_LR:
case UC_ARM_REG_R14:
ARM_CPU(uc, mycpu)->env.regs[14] = *(int32_t *)value;
ARM_CPU(uc, mycpu)->env.regs[14] = *(uint32_t *)value;
break;
//case UC_ARM_REG_PC:
case UC_ARM_REG_R15:
ARM_CPU(uc, mycpu)->env.regs[15] = *(int32_t *)value;
ARM_CPU(uc, mycpu)->env.regs[15] = *(uint32_t *)value;
break;
}
}

240
qemu/target-i386/unicorn.c
View File

@ -552,19 +552,19 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
switch(regid) {
default: break;
case UC_X86_REG_ES:
X86_CPU(uc, mycpu)->env.segs[R_ES].selector = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_ES].selector = *(uint16_t *)value;
return 0;
case UC_X86_REG_SS:
X86_CPU(uc, mycpu)->env.segs[R_SS].selector = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_SS].selector = *(uint16_t *)value;
return 0;
case UC_X86_REG_DS:
X86_CPU(uc, mycpu)->env.segs[R_DS].selector = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_DS].selector = *(uint16_t *)value;
return 0;
case UC_X86_REG_FS:
X86_CPU(uc, mycpu)->env.segs[R_FS].selector = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_FS].selector = *(uint16_t *)value;
return 0;
case UC_X86_REG_GS:
X86_CPU(uc, mycpu)->env.segs[R_GS].selector = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_GS].selector = *(uint16_t *)value;
return 0;
}
// fall-thru
@ -573,109 +573,109 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
default:
break;
case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(int32_t *)value;
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint32_t *)value;
break;
case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(int32_t *)value;
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint32_t *)value;
break;
case UC_X86_REG_EFLAGS:
X86_CPU(uc, mycpu)->env.eflags = *(int32_t *)value;
X86_CPU(uc, mycpu)->env.eflags = *(uint32_t *)value;
break;
case UC_X86_REG_EAX:
X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(int32_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(uint32_t *)value;
break;
case UC_X86_REG_AX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint16_t *)value);
break;
case UC_X86_REG_AH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int8_t *)value);
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
break;
case UC_X86_REG_AL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
break;
case UC_X86_REG_EBX:
X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(int32_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(uint32_t *)value;
break;
case UC_X86_REG_BX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint16_t *)value);
break;
case UC_X86_REG_BH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int8_t *)value);
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
break;
case UC_X86_REG_BL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
break;
case UC_X86_REG_ECX:
X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(int32_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(uint32_t *)value;
break;
case UC_X86_REG_CX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint16_t *)value);
break;
case UC_X86_REG_CH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int8_t *)value);
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
break;
case UC_X86_REG_CL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
break;
case UC_X86_REG_EDX:
X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(int32_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(uint32_t *)value;
break;
case UC_X86_REG_DX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint16_t *)value);
break;
case UC_X86_REG_DH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int8_t *)value);
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
break;
case UC_X86_REG_DL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
break;
case UC_X86_REG_ESP:
X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(int32_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(uint32_t *)value;
break;
case UC_X86_REG_SP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint16_t *)value);
break;
case UC_X86_REG_EBP:
X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(int32_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(uint32_t *)value;
break;
case UC_X86_REG_BP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint16_t *)value);
break;
case UC_X86_REG_ESI:
X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(int32_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(uint32_t *)value;
break;
case UC_X86_REG_SI:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint16_t *)value);
break;
case UC_X86_REG_EDI:
X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(int32_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(uint32_t *)value;
break;
case UC_X86_REG_DI:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint16_t *)value);
break;
case UC_X86_REG_EIP:
X86_CPU(uc, mycpu)->env.eip = *(int32_t *)value;
X86_CPU(uc, mycpu)->env.eip = *(uint32_t *)value;
break;
case UC_X86_REG_IP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(uint16_t *)value);
break;
case UC_X86_REG_CS:
X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(uint16_t *)value;
break;
case UC_X86_REG_DS:
X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(uint16_t *)value;
break;
case UC_X86_REG_SS:
X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(uint16_t *)value;
break;
case UC_X86_REG_ES:
X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(uint16_t *)value;
break;
case UC_X86_REG_FS:
X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(uint16_t *)value;
break;
case UC_X86_REG_GS:
X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint16_t *)value;
break;
}
break;
@ -686,244 +686,244 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
default:
break;
case UC_X86_REG_CR0 ... UC_X86_REG_CR4:
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint64_t *)value;
break;
case UC_X86_REG_DR0 ... UC_X86_REG_DR7:
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint64_t *)value;
break;
case UC_X86_REG_EFLAGS:
X86_CPU(uc, mycpu)->env.eflags = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.eflags = *(uint64_t *)value;
break;
case UC_X86_REG_RAX:
X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_EAX] = *(uint64_t *)value;
break;
case UC_X86_REG_EAX:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint32_t *)value);
break;
case UC_X86_REG_AX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint16_t *)value);
break;
case UC_X86_REG_AH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int8_t *)value);
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
break;
case UC_X86_REG_AL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EAX], *(uint8_t *)value);
break;
case UC_X86_REG_RBX:
X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_EBX] = *(uint64_t *)value;
break;
case UC_X86_REG_EBX:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint32_t *)value);
break;
case UC_X86_REG_BX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint16_t *)value);
break;
case UC_X86_REG_BH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int8_t *)value);
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
break;
case UC_X86_REG_BL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBX], *(uint8_t *)value);
break;
case UC_X86_REG_RCX:
X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_ECX] = *(uint64_t *)value;
break;
case UC_X86_REG_ECX:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint32_t *)value);
break;
case UC_X86_REG_CX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint16_t *)value);
break;
case UC_X86_REG_CH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int8_t *)value);
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
break;
case UC_X86_REG_CL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ECX], *(uint8_t *)value);
break;
case UC_X86_REG_RDX:
X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_EDX] = *(uint64_t *)value;
break;
case UC_X86_REG_EDX:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint32_t *)value);
break;
case UC_X86_REG_DX:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint16_t *)value);
break;
case UC_X86_REG_DH:
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int8_t *)value);
WRITE_BYTE_H(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
break;
case UC_X86_REG_DL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDX], *(uint8_t *)value);
break;
case UC_X86_REG_RSP:
X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_ESP] = *(uint64_t *)value;
break;
case UC_X86_REG_ESP:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint32_t *)value);
break;
case UC_X86_REG_SP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint16_t *)value);
break;
case UC_X86_REG_SPL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESP], *(uint8_t *)value);
break;
case UC_X86_REG_RBP:
X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_EBP] = *(uint64_t *)value;
break;
case UC_X86_REG_EBP:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint32_t *)value);
break;
case UC_X86_REG_BP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint16_t *)value);
break;
case UC_X86_REG_BPL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EBP], *(uint8_t *)value);
break;
case UC_X86_REG_RSI:
X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_ESI] = *(uint64_t *)value;
break;
case UC_X86_REG_ESI:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint32_t *)value);
break;
case UC_X86_REG_SI:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint16_t *)value);
break;
case UC_X86_REG_SIL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_ESI], *(uint8_t *)value);
break;
case UC_X86_REG_RDI:
X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[R_EDI] = *(uint64_t *)value;
break;
case UC_X86_REG_EDI:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint32_t *)value);
break;
case UC_X86_REG_DI:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint16_t *)value);
break;
case UC_X86_REG_DIL:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[R_EDI], *(uint8_t *)value);
break;
case UC_X86_REG_RIP:
X86_CPU(uc, mycpu)->env.eip = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.eip = *(uint64_t *)value;
break;
case UC_X86_REG_EIP:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.eip, *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.eip, *(uint32_t *)value);
break;
case UC_X86_REG_IP:
WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.eip, *(uint16_t *)value);
break;
case UC_X86_REG_CS:
X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_CS].base = *(uint16_t *)value;
break;
case UC_X86_REG_DS:
X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_DS].base = *(uint16_t *)value;
break;
case UC_X86_REG_SS:
X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_SS].base = *(uint16_t *)value;
break;
case UC_X86_REG_ES:
X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_ES].base = *(uint16_t *)value;
break;
case UC_X86_REG_FS:
X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_FS].base = *(uint16_t *)value;
break;
case UC_X86_REG_GS:
X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(int16_t *)value;
X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint16_t *)value;
break;
case UC_X86_REG_R8:
X86_CPU(uc, mycpu)->env.regs[8] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[8] = *(uint64_t *)value;
break;
case UC_X86_REG_R8D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[8], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[8], *(uint32_t *)value);
break;
case UC_X86_REG_R8W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[8], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[8], *(uint16_t *)value);
break;
case UC_X86_REG_R8B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[8], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[8], *(uint8_t *)value);
break;
case UC_X86_REG_R9:
X86_CPU(uc, mycpu)->env.regs[9] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[9] = *(uint64_t *)value;
break;
case UC_X86_REG_R9D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[9], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[9], *(uint32_t *)value);
break;
case UC_X86_REG_R9W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[9], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[9], *(uint16_t *)value);
break;
case UC_X86_REG_R9B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[9], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[9], *(uint8_t *)value);
break;
case UC_X86_REG_R10:
X86_CPU(uc, mycpu)->env.regs[10] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[10] = *(uint64_t *)value;
break;
case UC_X86_REG_R10D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[10], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[10], *(uint32_t *)value);
break;
case UC_X86_REG_R10W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[10], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[10], *(uint16_t *)value);
break;
case UC_X86_REG_R10B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[10], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[10], *(uint8_t *)value);
break;
case UC_X86_REG_R11:
X86_CPU(uc, mycpu)->env.regs[11] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[11] = *(uint64_t *)value;
break;
case UC_X86_REG_R11D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[11], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[11], *(uint32_t *)value);
break;
case UC_X86_REG_R11W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[11], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[11], *(uint16_t *)value);
break;
case UC_X86_REG_R11B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[11], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[11], *(uint8_t *)value);
break;
case UC_X86_REG_R12:
X86_CPU(uc, mycpu)->env.regs[12] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[12] = *(uint64_t *)value;
break;
case UC_X86_REG_R12D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[12], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[12], *(uint32_t *)value);
break;
case UC_X86_REG_R12W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[12], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[12], *(uint16_t *)value);
break;
case UC_X86_REG_R12B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[12], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[12], *(uint8_t *)value);
break;
case UC_X86_REG_R13:
X86_CPU(uc, mycpu)->env.regs[13] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[13] = *(uint64_t *)value;
break;
case UC_X86_REG_R13D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[13], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[13], *(uint32_t *)value);
break;
case UC_X86_REG_R13W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[13], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[13], *(uint16_t *)value);
break;
case UC_X86_REG_R13B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[13], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[13], *(uint8_t *)value);
break;
case UC_X86_REG_R14:
X86_CPU(uc, mycpu)->env.regs[14] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[14] = *(uint64_t *)value;
break;
case UC_X86_REG_R14D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[14], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[14], *(uint32_t *)value);
break;
case UC_X86_REG_R14W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[14], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[14], *(uint16_t *)value);
break;
case UC_X86_REG_R14B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[14], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[14], *(uint8_t *)value);
break;
case UC_X86_REG_R15:
X86_CPU(uc, mycpu)->env.regs[15] = *(int64_t *)value;
X86_CPU(uc, mycpu)->env.regs[15] = *(uint64_t *)value;
break;
case UC_X86_REG_R15D:
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[15], *(int32_t *)value);
WRITE_DWORD(X86_CPU(uc, mycpu)->env.regs[15], *(uint32_t *)value);
break;
case UC_X86_REG_R15W:
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[15], *(int16_t *)value);
WRITE_WORD(X86_CPU(uc, mycpu)->env.regs[15], *(uint16_t *)value);
break;
case UC_X86_REG_R15B:
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15], *(int8_t *)value);
WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15], *(uint8_t *)value);
break;
}
break;

4
qemu/target-m68k/unicorn.c
View File

@ -62,9 +62,9 @@ int m68k_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
CPUState *mycpu = first_cpu;
if (regid >= UC_M68K_REG_A0 && regid <= UC_M68K_REG_A7)
M68K_CPU(uc, mycpu)->env.aregs[regid - UC_M68K_REG_A0] = *(int32_t *)value;
M68K_CPU(uc, mycpu)->env.aregs[regid - UC_M68K_REG_A0] = *(uint32_t *)value;
else if (regid >= UC_M68K_REG_D0 && regid <= UC_M68K_REG_D7)
M68K_CPU(uc, mycpu)->env.dregs[regid - UC_M68K_REG_D0] = *(int32_t *)value;
M68K_CPU(uc, mycpu)->env.dregs[regid - UC_M68K_REG_D0] = *(uint32_t *)value;
else {
switch(regid) {
default: break;

4
qemu/target-mips/unicorn.c
View File

@ -60,12 +60,12 @@ int mips_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
CPUState *mycpu = first_cpu;
if (regid >= UC_MIPS_REG_0 && regid <= UC_MIPS_REG_31)
MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(int32_t *)value;
MIPS_CPU(uc, mycpu)->env.active_tc.gpr[regid - UC_MIPS_REG_0] = *(uint32_t *)value;
else {
switch(regid) {
default: break;
case UC_MIPS_REG_PC:
MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(int32_t *)value;
MIPS_CPU(uc, mycpu)->env.active_tc.PC = *(uint32_t *)value;
break;
}
}

2
qemu/target-sparc/unicorn.c
View File

@ -73,7 +73,7 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
CPUState *mycpu = first_cpu;
if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(int32_t *)value;
SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(uint32_t *)value;
else {
switch(regid) {
default: break;

2
qemu/target-sparc/unicorn64.c
View File

@ -56,7 +56,7 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
CPUState *mycpu = first_cpu;
if (regid >= UC_SPARC_REG_G0 && regid <= UC_SPARC_REG_G7)
SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(int32_t *)value;
SPARC_CPU(uc, mycpu)->env.gregs[regid - UC_SPARC_REG_G0] = *(uint32_t *)value;
else {
switch(regid) {
default: break;

2
regress/reg_write_sign_extension.py
View File

@ -6,7 +6,7 @@ import unicorn
ADDR = 0xffaabbcc
def hook_mem_invalid(mu, access, address, size, value, user_data):
print ">>> Expected value: 0x%x, actual value: 0x%x" % (ADDR, address)
print ">>> Access type: %u, expected value: 0x%x, actual value: 0x%x" % (access, ADDR, address)
assert(address == ADDR)
mu.mem_map(address & 0xfffff000, 4 * 1024)
mu.mem_write(address, b'\xcc')

6
uc.c
View File

@ -73,12 +73,14 @@ const char *uc_strerror(uc_err code)
return "Invalid memory read (UC_ERR_MEM_READ)";
case UC_ERR_MEM_WRITE:
return "Invalid memory write (UC_ERR_MEM_WRITE)";
case UC_ERR_MEM_FETCH:
return "Invalid memory fetch (UC_ERR_MEM_FETCH)";
case UC_ERR_CODE_INVALID:
return "Invalid code address (UC_ERR_CODE_INVALID)";
case UC_ERR_INSN_INVALID:
return "Invalid instruction (UC_ERR_INSN_INVALID)";
case UC_ERR_HOOK:
return "Invalid hook type (UC_ERR_HOOK)";
case UC_ERR_INSN_INVALID:
return "Invalid instruction (UC_ERR_INSN_INVALID)";
case UC_ERR_MAP:
return "Invalid memory mapping (UC_ERR_MAP)";
case UC_ERR_WRITE_PROT: