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@ -698,13 +698,12 @@ static void test_arm_be_cpsr_sctlr()
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static void test_arm_switch_endian()
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{
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uc_engine *uc;
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char code[] =
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"\x00\x00\x91\xe5"; // ldr r0, [r1]
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char code[] = "\x00\x00\x91\xe5"; // ldr r0, [r1]
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uint32_t r_r1 = (uint32_t)code_start;
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uint32_t r_r0, r_cpsr;
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uc_common_setup(&uc, UC_ARCH_ARM, UC_MODE_ARM, code,
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sizeof(code) - 1, UC_CPU_ARM_CORTEX_A15);
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uc_common_setup(&uc, UC_ARCH_ARM, UC_MODE_ARM, code, sizeof(code) - 1,
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UC_CPU_ARM_CORTEX_A15);
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OK(uc_reg_write(uc, UC_ARM_REG_R1, &r_r1));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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@ -713,9 +712,9 @@ static void test_arm_switch_endian()
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// Little endian
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TEST_CHECK(r_r0 == 0xe5910000);
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OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &r_cpsr));
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r_cpsr |= (1<<9);
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r_cpsr |= (1 << 9);
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OK(uc_reg_write(uc, UC_ARM_REG_CPSR, &r_cpsr));
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OK(uc_emu_start(uc, code_start, code_start + sizeof(code) - 1, 0, 0));
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