SIGABRT issue
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#!/usr/bin/python
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# By Mariano Graziano
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from unicorn import *
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from unicorn.x86_const import *
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import regress, struct
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mu = 0
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class Init(regress.RegressTest):
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def init_unicorn(self, ip, sp, counter):
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global mu
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print "[+] Emulating IP: %x SP: %x - Counter: %x" % (ip, sp, counter)
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mu = Uc(UC_ARCH_X86, UC_MODE_64)
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mu.mem_map(0x1000000, 2 * 1024 * 1024)
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mu.mem_write(0x1000000, "\x90")
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mu.mem_map(0x8000000, 8 * 1024 * 1024)
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mu.reg_write(UC_X86_REG_RSP, sp)
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content = self.generate_value(counter)
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mu.mem_write(sp, content)
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self.set_hooks()
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def generate_value(self, counter):
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start = 0xffff880026f02000
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offset = counter * 8
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address = start + offset
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return struct.pack("<Q", address)
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def set_hooks(self):
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global mu
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mu.hook_add(UC_HOOK_MEM_READ_UNMAPPED | UC_HOOK_MEM_WRITE_UNMAPPED, self.hook_mem_invalid)
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mu.hook_add(UC_HOOK_MEM_FETCH_UNMAPPED, self.hook_mem_fetch_unmapped)
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def hook_mem_invalid(self, uc, access, address, size, value, user_data):
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global mu
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print "[ HOOK_MEM_INVALID - Address: %s ]" % hex(address)
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if access == UC_MEM_WRITE_UNMAPPED:
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print ">>> Missing memory is being WRITE at 0x%x, data size = %u, data value = 0x%x" %(address, size, value)
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address_page = address & 0xFFFFFFFFFFFFF000
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mu.mem_map(address_page, 2 * 1024 * 1024)
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mu.mem_write(address, str(value))
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return True
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else:
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return False
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def hook_mem_fetch_unmapped(self, uc, access, address, size, value, user_data):
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global mu
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print "[ HOOK_MEM_FETCH - Address: %s ]" % hex(address).strip("L")
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print "[ mem_fetch_unmapped: faulting address at %s ]" % hex(address).strip("L")
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mu.mem_write(0x1000003, "\x90")
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mu.reg_write(UC_X86_REG_RIP, 0x1000001)
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return True
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def runTest(self):
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global mu
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ips = list(xrange(0x1000000, 0x1001000, 0x1))
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sps = list(xrange(0x8000000, 0x8001000, 0x1))
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j = 0
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for i in ips:
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j += 1
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index = ips.index(i)
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self.init_unicorn(i, sps[index], j)
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mu.emu_start(0x1000000, 0x1000000 + 0x1)
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if __name__ == '__main__':
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regress.main()
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