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Merge pull request #1991 from apparentlymart/b-riscv-invalidinsn-pcadj

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riscv: Invalid 32-bit instruction should not decrement pc
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lazymio 2024-09-21 18:26:59 +08:00 committed by GitHub
commit 9427f0a553
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qemu/target/riscv/translate.c
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@ -769,7 +769,6 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
translator_lduw(tcg_ctx, env, ctx->base.pc_next + 2)); translator_lduw(tcg_ctx, env, ctx->base.pc_next + 2));
ctx->pc_succ_insn = ctx->base.pc_next + 4; ctx->pc_succ_insn = ctx->base.pc_next + 4;
if (!decode_insn32(ctx, opcode32)) { if (!decode_insn32(ctx, opcode32)) {
ctx->pc_succ_insn = ctx->base.pc_next - 4;
gen_exception_illegal(ctx); gen_exception_illegal(ctx);
} }
} }