From 901034577a42592901895fdeaef37d80a4fe6a2f Mon Sep 17 00:00:00 2001 From: "Takacs, Philipp" Date: Mon, 17 Oct 2022 14:33:10 +0200 Subject: [PATCH] i386 call internal helper on special porpese register write Some registers writes have side effects. i.e. write to cr3 flush the tlb, if the PG bit is set. --- qemu/target/i386/unicorn.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qemu/target/i386/unicorn.c b/qemu/target/i386/unicorn.c index 3e83b0ba..a7a93628 100644 --- a/qemu/target/i386/unicorn.c +++ b/qemu/target/i386/unicorn.c @@ -977,10 +977,16 @@ static int reg_write(CPUX86State *env, unsigned int regid, const void *value, default: break; case UC_X86_REG_CR0: + cpu_x86_update_cr0(env, *(uint32_t *)value); + goto write_cr; case UC_X86_REG_CR1: case UC_X86_REG_CR2: case UC_X86_REG_CR3: + cpu_x86_update_cr3(env, *(uint32_t *)value); + goto write_cr; case UC_X86_REG_CR4: + cpu_x86_update_cr4(env, *(uint32_t *)value); +write_cr: env->cr[regid - UC_X86_REG_CR0] = *(uint32_t *)value; break; case UC_X86_REG_DR0: @@ -1163,10 +1169,16 @@ static int reg_write(CPUX86State *env, unsigned int regid, const void *value, default: break; case UC_X86_REG_CR0: + cpu_x86_update_cr0(env, *(uint32_t *) value); + goto write_cr64; case UC_X86_REG_CR1: case UC_X86_REG_CR2: case UC_X86_REG_CR3: + cpu_x86_update_cr3(env, *(uint32_t *) value); + goto write_cr64; case UC_X86_REG_CR4: + cpu_x86_update_cr4(env, *(uint32_t *) value); +write_cr64: env->cr[regid - UC_X86_REG_CR0] = *(uint64_t *)value; break; case UC_X86_REG_DR0: