diff --git a/include/unicorn/platform.h b/include/unicorn/platform.h
index ffdc5646..80f1a796 100644
--- a/include/unicorn/platform.h
+++ b/include/unicorn/platform.h
@@ -198,6 +198,12 @@ static void usleep(const int64_t &t)
// misc support
#if defined(_MSC_VER)
+#ifdef _WIN64
+typedef signed __int64 ssize_t;
+#else
+typedef _W64 signed int ssize_t;
+#endif
+
#define va_copy(d,s) ((d) = (s))
#define strcasecmp _stricmp
#if (_MSC_VER < MSC_VER_VS2015)
diff --git a/msvc/unicorn.sln b/msvc/unicorn.sln
index 3c533e77..c623976b 100644
--- a/msvc/unicorn.sln
+++ b/msvc/unicorn.sln
@@ -122,60 +122,93 @@ Global
{F8053D66-8267-433A-BF2C-E07E2298C338}.Release|x64.ActiveCfg = Release|x64
{F8053D66-8267-433A-BF2C-E07E2298C338}.Release|x64.Build.0 = Release|x64
{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Debug|Win32.ActiveCfg = Debug|Win32
+ {2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Debug|Win32.Build.0 = Debug|Win32
{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Debug|x64.ActiveCfg = Debug|x64
+ {2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Debug|x64.Build.0 = Debug|x64
{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Release|Win32.ActiveCfg = Release|Win32
+ {2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Release|Win32.Build.0 = Release|Win32
{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Release|x64.ActiveCfg = Release|x64
+ {2A7F483F-CD19-4F84-BBDA-B6A1865E2773}.Release|x64.Build.0 = Release|x64
{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Debug|Win32.ActiveCfg = Debug|Win32
+ {F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Debug|Win32.Build.0 = Debug|Win32
{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Debug|x64.ActiveCfg = Debug|x64
+ {F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Debug|x64.Build.0 = Debug|x64
{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Release|Win32.ActiveCfg = Release|Win32
+ {F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Release|Win32.Build.0 = Release|Win32
{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Release|x64.ActiveCfg = Release|x64
+ {F67EB1EA-DCFA-4758-A2AA-4B570BA78036}.Release|x64.Build.0 = Release|x64
{2C5AD347-6E34-463B-8289-00578E43B255}.Debug|Win32.ActiveCfg = Debug|Win32
{2C5AD347-6E34-463B-8289-00578E43B255}.Debug|Win32.Build.0 = Debug|Win32
{2C5AD347-6E34-463B-8289-00578E43B255}.Debug|x64.ActiveCfg = Debug|x64
+ {2C5AD347-6E34-463B-8289-00578E43B255}.Debug|x64.Build.0 = Debug|x64
{2C5AD347-6E34-463B-8289-00578E43B255}.Release|Win32.ActiveCfg = Release|Win32
+ {2C5AD347-6E34-463B-8289-00578E43B255}.Release|Win32.Build.0 = Release|Win32
{2C5AD347-6E34-463B-8289-00578E43B255}.Release|x64.ActiveCfg = Release|x64
+ {2C5AD347-6E34-463B-8289-00578E43B255}.Release|x64.Build.0 = Release|x64
{63050112-E486-4396-B5E4-303C3BC12D39}.Debug|Win32.ActiveCfg = Debug|Win32
{63050112-E486-4396-B5E4-303C3BC12D39}.Debug|Win32.Build.0 = Debug|Win32
{63050112-E486-4396-B5E4-303C3BC12D39}.Debug|x64.ActiveCfg = Debug|x64
+ {63050112-E486-4396-B5E4-303C3BC12D39}.Debug|x64.Build.0 = Debug|x64
{63050112-E486-4396-B5E4-303C3BC12D39}.Release|Win32.ActiveCfg = Release|Win32
+ {63050112-E486-4396-B5E4-303C3BC12D39}.Release|Win32.Build.0 = Release|Win32
{63050112-E486-4396-B5E4-303C3BC12D39}.Release|x64.ActiveCfg = Release|x64
+ {63050112-E486-4396-B5E4-303C3BC12D39}.Release|x64.Build.0 = Release|x64
{4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Debug|Win32.ActiveCfg = Debug|Win32
{4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Debug|Win32.Build.0 = Debug|Win32
{4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Debug|x64.ActiveCfg = Debug|x64
+ {4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Debug|x64.Build.0 = Debug|x64
{4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Release|Win32.ActiveCfg = Release|Win32
+ {4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Release|Win32.Build.0 = Release|Win32
{4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Release|x64.ActiveCfg = Release|x64
+ {4A9F9353-DB63-460A-BB1C-9CB519DFD414}.Release|x64.Build.0 = Release|x64
{4478909E-6983-425C-9D9F-558CF258E61E}.Debug|Win32.ActiveCfg = Debug|Win32
{4478909E-6983-425C-9D9F-558CF258E61E}.Debug|Win32.Build.0 = Debug|Win32
{4478909E-6983-425C-9D9F-558CF258E61E}.Debug|x64.ActiveCfg = Debug|x64
+ {4478909E-6983-425C-9D9F-558CF258E61E}.Debug|x64.Build.0 = Debug|x64
{4478909E-6983-425C-9D9F-558CF258E61E}.Release|Win32.ActiveCfg = Release|Win32
+ {4478909E-6983-425C-9D9F-558CF258E61E}.Release|Win32.Build.0 = Release|Win32
{4478909E-6983-425C-9D9F-558CF258E61E}.Release|x64.ActiveCfg = Release|x64
+ {4478909E-6983-425C-9D9F-558CF258E61E}.Release|x64.Build.0 = Release|x64
{006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Debug|Win32.ActiveCfg = Debug|Win32
{006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Debug|Win32.Build.0 = Debug|Win32
{006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Debug|x64.ActiveCfg = Debug|x64
+ {006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Debug|x64.Build.0 = Debug|x64
{006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Release|Win32.ActiveCfg = Release|Win32
+ {006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Release|Win32.Build.0 = Release|Win32
{006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Release|x64.ActiveCfg = Release|x64
+ {006A7908-ABF3-4D18-BC35-0A29E39B95F9}.Release|x64.Build.0 = Release|x64
{698C2D54-475C-446F-B879-F629BBEF75FE}.Debug|Win32.ActiveCfg = Debug|Win32
{698C2D54-475C-446F-B879-F629BBEF75FE}.Debug|Win32.Build.0 = Debug|Win32
{698C2D54-475C-446F-B879-F629BBEF75FE}.Debug|x64.ActiveCfg = Debug|x64
+ {698C2D54-475C-446F-B879-F629BBEF75FE}.Debug|x64.Build.0 = Debug|x64
{698C2D54-475C-446F-B879-F629BBEF75FE}.Release|Win32.ActiveCfg = Release|Win32
+ {698C2D54-475C-446F-B879-F629BBEF75FE}.Release|Win32.Build.0 = Release|Win32
{698C2D54-475C-446F-B879-F629BBEF75FE}.Release|x64.ActiveCfg = Release|x64
+ {698C2D54-475C-446F-B879-F629BBEF75FE}.Release|x64.Build.0 = Release|x64
{8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Debug|Win32.ActiveCfg = Debug|Win32
{8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Debug|Win32.Build.0 = Debug|Win32
{8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Debug|x64.ActiveCfg = Debug|x64
+ {8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Debug|x64.Build.0 = Debug|x64
{8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Release|Win32.ActiveCfg = Release|Win32
+ {8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Release|Win32.Build.0 = Release|Win32
{8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Release|x64.ActiveCfg = Release|x64
+ {8804AD29-E398-480C-AC0F-98EC1B7A51CB}.Release|x64.Build.0 = Release|x64
{9F32C692-9106-43AF-A291-779A2D8BE096}.Debug|Win32.ActiveCfg = Debug|Win32
{9F32C692-9106-43AF-A291-779A2D8BE096}.Debug|Win32.Build.0 = Debug|Win32
{9F32C692-9106-43AF-A291-779A2D8BE096}.Debug|x64.ActiveCfg = Debug|x64
+ {9F32C692-9106-43AF-A291-779A2D8BE096}.Debug|x64.Build.0 = Debug|x64
{9F32C692-9106-43AF-A291-779A2D8BE096}.Release|Win32.ActiveCfg = Release|Win32
{9F32C692-9106-43AF-A291-779A2D8BE096}.Release|Win32.Build.0 = Release|Win32
{9F32C692-9106-43AF-A291-779A2D8BE096}.Release|x64.ActiveCfg = Release|x64
+ {9F32C692-9106-43AF-A291-779A2D8BE096}.Release|x64.Build.0 = Release|x64
{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Debug|Win32.ActiveCfg = Debug|Win32
{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Debug|Win32.Build.0 = Debug|Win32
{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Debug|x64.ActiveCfg = Debug|x64
+ {9D588288-5A28-4AB3-96EA-442CAA508F8E}.Debug|x64.Build.0 = Debug|x64
{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Release|Win32.ActiveCfg = Release|Win32
{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Release|Win32.Build.0 = Release|Win32
{9D588288-5A28-4AB3-96EA-442CAA508F8E}.Release|x64.ActiveCfg = Release|x64
+ {9D588288-5A28-4AB3-96EA-442CAA508F8E}.Release|x64.Build.0 = Release|x64
{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Debug|Win32.ActiveCfg = Debug|Win32
{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Debug|Win32.Build.0 = Debug|Win32
{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Debug|x64.ActiveCfg = Debug|x64
@@ -183,42 +216,55 @@ Global
{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Release|Win32.ActiveCfg = Release|Win32
{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Release|Win32.Build.0 = Release|Win32
{04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Release|x64.ActiveCfg = Release|x64
+ {04DC0E3A-F247-45C2-AE27-8DE7493AA43B}.Release|x64.Build.0 = Release|x64
{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Debug|Win32.ActiveCfg = Debug|Win32
{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Debug|Win32.Build.0 = Debug|Win32
{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Debug|x64.ActiveCfg = Debug|x64
+ {7AA02EDF-D797-494B-929C-F628F4E4EA62}.Debug|x64.Build.0 = Debug|x64
{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Release|Win32.ActiveCfg = Release|Win32
{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Release|Win32.Build.0 = Release|Win32
{7AA02EDF-D797-494B-929C-F628F4E4EA62}.Release|x64.ActiveCfg = Release|x64
+ {7AA02EDF-D797-494B-929C-F628F4E4EA62}.Release|x64.Build.0 = Release|x64
{11727C54-463F-472A-88AF-6C3D6071BF0B}.Debug|Win32.ActiveCfg = Debug|Win32
{11727C54-463F-472A-88AF-6C3D6071BF0B}.Debug|Win32.Build.0 = Debug|Win32
{11727C54-463F-472A-88AF-6C3D6071BF0B}.Debug|x64.ActiveCfg = Debug|x64
+ {11727C54-463F-472A-88AF-6C3D6071BF0B}.Debug|x64.Build.0 = Debug|x64
{11727C54-463F-472A-88AF-6C3D6071BF0B}.Release|Win32.ActiveCfg = Release|Win32
{11727C54-463F-472A-88AF-6C3D6071BF0B}.Release|Win32.Build.0 = Release|Win32
{11727C54-463F-472A-88AF-6C3D6071BF0B}.Release|x64.ActiveCfg = Release|x64
+ {11727C54-463F-472A-88AF-6C3D6071BF0B}.Release|x64.Build.0 = Release|x64
{E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Debug|Win32.ActiveCfg = Debug|Win32
{E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Debug|Win32.Build.0 = Debug|Win32
{E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Debug|x64.ActiveCfg = Debug|x64
+ {E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Debug|x64.Build.0 = Debug|x64
{E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Release|Win32.ActiveCfg = Release|Win32
{E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Release|Win32.Build.0 = Release|Win32
{E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Release|x64.ActiveCfg = Release|x64
+ {E34ECD90-3977-4A4B-9641-4D7F1766E9FD}.Release|x64.Build.0 = Release|x64
{A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Debug|Win32.ActiveCfg = Debug|Win32
{A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Debug|Win32.Build.0 = Debug|Win32
{A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Debug|x64.ActiveCfg = Debug|x64
+ {A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Debug|x64.Build.0 = Debug|x64
{A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Release|Win32.ActiveCfg = Release|Win32
{A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Release|Win32.Build.0 = Release|Win32
{A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Release|x64.ActiveCfg = Release|x64
+ {A25CA34D-2F64-442B-A5D3-B13CB56C9957}.Release|x64.Build.0 = Release|x64
{9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Debug|Win32.ActiveCfg = Debug|Win32
{9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Debug|Win32.Build.0 = Debug|Win32
{9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Debug|x64.ActiveCfg = Debug|x64
+ {9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Debug|x64.Build.0 = Debug|x64
{9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Release|Win32.ActiveCfg = Release|Win32
{9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Release|Win32.Build.0 = Release|Win32
{9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Release|x64.ActiveCfg = Release|x64
+ {9D96D09A-DE17-4011-9247-F0009E8D6DB5}.Release|x64.Build.0 = Release|x64
{F113B460-4B21-4014-9A15-D472FAA9E3F9}.Debug|Win32.ActiveCfg = Debug|Win32
{F113B460-4B21-4014-9A15-D472FAA9E3F9}.Debug|Win32.Build.0 = Debug|Win32
{F113B460-4B21-4014-9A15-D472FAA9E3F9}.Debug|x64.ActiveCfg = Debug|x64
+ {F113B460-4B21-4014-9A15-D472FAA9E3F9}.Debug|x64.Build.0 = Debug|x64
{F113B460-4B21-4014-9A15-D472FAA9E3F9}.Release|Win32.ActiveCfg = Release|Win32
{F113B460-4B21-4014-9A15-D472FAA9E3F9}.Release|Win32.Build.0 = Release|Win32
{F113B460-4B21-4014-9A15-D472FAA9E3F9}.Release|x64.ActiveCfg = Release|x64
+ {F113B460-4B21-4014-9A15-D472FAA9E3F9}.Release|x64.Build.0 = Release|x64
EndGlobalSection
GlobalSection(SolutionProperties) = preSolution
HideSolutionNode = FALSE
diff --git a/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj b/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj
index 2d13308b..6a5c1418 100644
--- a/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj
+++ b/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj
@@ -19,8 +19,62 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ true
+ true
+ true
+
+
+
+
+
{2A7F483F-CD19-4F84-BBDA-B6A1865E2773}
Win32Proj
diff --git a/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj.filters b/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj.filters
index fe67d289..70ff0cce 100644
--- a/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj.filters
+++ b/msvc/unicorn/aarch64-softmmu/aarch64-softmmu.vcxproj.filters
@@ -2,5 +2,148 @@
+
+
+ fpu
+
+
+ fpu
+
+
+ tcg
+
+
+ tcg
+
+
+ tcg
+
+
+ tcg
+
+
+ tcg
+
+
+ tcg
+
+
+ tcg\i386
+
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+
+
+
+
+
+
+
+
+
+
+ fpu
+
+
+ tcg
+
+
+ tcg
+
+
+ tcg\i386
+
+
+ hw\arm
+
+
+ hw\arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+
+
+ {8a7d2815-3656-4ae7-8eb2-d38da6e8d480}
+
+
+ {ca50b33c-f5ce-4975-a702-c607bb2fc604}
+
+
+ {1db81436-53cf-4cb6-a474-e76327883bd2}
+
+
+ {9a7f2b42-3f31-4731-84e2-38f535304a1d}
+
+
+ {c74d3c4d-1f19-42c6-bf25-26820a53ac11}
+
+
+ {0e231806-86e4-4e05-8ef8-3e3d36860b00}
+
\ No newline at end of file
diff --git a/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj b/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj
index 8c6ddbfa..1578b24e 100644
--- a/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj
+++ b/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj
@@ -19,8 +19,58 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ true
+ true
+ true
+
+
+
+
+
{F67EB1EA-DCFA-4758-A2AA-4B570BA78036}
Win32Proj
diff --git a/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj.filters b/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj.filters
index fe67d289..21f4ff71 100644
--- a/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj.filters
+++ b/msvc/unicorn/arm-softmmu/arm-softmmu.vcxproj.filters
@@ -2,5 +2,136 @@
+
+
+ fpu
+
+
+ fpu
+
+
+ tcg
+
+
+ tcg
+
+
+ tcg
+
+
+ tcg
+
+
+ tcg
+
+
+ tcg
+
+
+ tcg\i386
+
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+
+
+
+
+
+
+
+
+
+
+ fpu
+
+
+ tcg
+
+
+ tcg
+
+
+ tcg\i386
+
+
+ hw\arm
+
+
+ hw\arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+ target-arm
+
+
+
+
+ {c29e2ed5-3ecd-426d-9245-04de2c8ce754}
+
+
+ {a9187bf5-cd27-47c7-8add-55b11a1150a9}
+
+
+ {015b3e43-eb63-4add-9f53-f3ac3033472f}
+
+
+ {89b122b1-9e4c-41b1-8670-c6d9ee3716f6}
+
+
+ {76f837ed-af45-43bf-9ee7-193dbdec1cd5}
+
+
+ {1f03d4ae-6433-4037-a347-993db1a315e6}
+
\ No newline at end of file
diff --git a/msvc/unicorn/unicorn/unicorn.vcxproj b/msvc/unicorn/unicorn/unicorn.vcxproj
index d949c10b..fe4fb932 100644
--- a/msvc/unicorn/unicorn/unicorn.vcxproj
+++ b/msvc/unicorn/unicorn/unicorn.vcxproj
@@ -237,7 +237,7 @@
Level3
Disabled
- WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86
+ WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_ARM;UNICORN_HAS_ARM64;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86
MultiThreadedDebug
.;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg
/wd4018 /wd4244 /wd4267 %(AdditionalOptions)
@@ -249,7 +249,7 @@
$(SolutionDir)$(Platform)\$(Configuration)\
- ws2_32.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib
+ ws2_32.lib;aarch64-softmmu.lib;arm-softmmu.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib
..\prebuild_script.bat
@@ -261,7 +261,7 @@
Level3
Disabled
- WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86
+ WIN32;_DEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_ARM;UNICORN_HAS_ARM64;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86
MultiThreadedDebug
.;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg
/wd4018 /wd4244 /wd4267 %(AdditionalOptions)
@@ -273,7 +273,7 @@
$(SolutionDir)$(Platform)\$(Configuration)\
- ws2_32.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib
+ ws2_32.lib;aarch64-softmmu.lib;arm-softmmu.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib
..\prebuild_script.bat
@@ -287,7 +287,7 @@
MaxSpeed
true
true
- WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86
+ WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__i386__;UNICORN_HAS_ARM;UNICORN_HAS_ARM64;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86
MultiThreaded
.;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg
/wd4018 /wd4244 /wd4267 %(AdditionalOptions)
@@ -301,7 +301,7 @@
$(SolutionDir)$(Platform)\$(Configuration)\
- ws2_32.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib
+ ws2_32.lib;aarch64-softmmu.lib;arm-softmmu.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib
..\prebuild_script.bat
@@ -315,7 +315,7 @@
MaxSpeed
true
true
- WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86
+ WIN32;NDEBUG;_LIB;%(PreprocessorDefinitions);_CRT_SECURE_NO_WARNINGS;inline=__inline;__func__=__FUNCTION__;__x86_64__;UNICORN_HAS_ARM;UNICORN_HAS_ARM64;UNICORN_HAS_M68K;UNICORN_HAS_MIPS;UNICORN_HAS_MIPS64;UNICORN_HAS_MIPSEL;UNICORN_HAS_MIPS64EL;UNICORN_HAS_SPARC;UNICORN_HAS_X86
MultiThreaded
.;..;../../../include;../../../qemu;../../../qemu/include;../../../qemu/tcg
/wd4018 /wd4244 /wd4267 %(AdditionalOptions)
@@ -329,7 +329,7 @@
$(SolutionDir)$(Platform)\$(Configuration)\
- ws2_32.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib
+ ws2_32.lib;aarch64-softmmu.lib;arm-softmmu.lib;m68k-softmmu.lib;mips-softmmu.lib;mips64-softmmu.lib;mipsel-softmmu.lib;mips64el-softmmu.lib;sparc-softmmu.lib;sparc64-softmmu.lib;x86_64-softmmu.lib
..\prebuild_script.bat
diff --git a/qemu/hw/arm/tosa.c b/qemu/hw/arm/tosa.c
index f6649f45..4a79e127 100644
--- a/qemu/hw/arm/tosa.c
+++ b/qemu/hw/arm/tosa.c
@@ -30,12 +30,11 @@ static int tosa_init(struct uc_struct *uc, MachineState *machine)
void tosa_machine_init(struct uc_struct *uc)
{
- static QEMUMachine tosapda_machine = {
- .name = "tosa",
- .init = tosa_init,
- .is_default = 1,
- .arch = UC_ARCH_ARM,
- };
+ static QEMUMachine tosapda_machine = { 0 };
+ tosapda_machine.name = "tosa",
+ tosapda_machine.init = tosa_init,
+ tosapda_machine.is_default = 1,
+ tosapda_machine.arch = UC_ARCH_ARM,
qemu_register_machine(uc, &tosapda_machine, TYPE_MACHINE, NULL);
}
diff --git a/qemu/hw/arm/virt.c b/qemu/hw/arm/virt.c
index 9e618e86..485109cc 100644
--- a/qemu/hw/arm/virt.c
+++ b/qemu/hw/arm/virt.c
@@ -64,12 +64,11 @@ static int machvirt_init(struct uc_struct *uc, MachineState *machine)
void machvirt_machine_init(struct uc_struct *uc)
{
- static QEMUMachine machvirt_a15_machine = {
- .name = "virt",
- .init = machvirt_init,
- .is_default = 1,
- .arch = UC_ARCH_ARM64,
- };
+ static QEMUMachine machvirt_a15_machine = { 0 };
+ machvirt_a15_machine.name = "virt",
+ machvirt_a15_machine.init = machvirt_init,
+ machvirt_a15_machine.is_default = 1,
+ machvirt_a15_machine.arch = UC_ARCH_ARM64,
qemu_register_machine(uc, &machvirt_a15_machine, TYPE_MACHINE, NULL);
}
diff --git a/qemu/target-arm/cpu.c b/qemu/target-arm/cpu.c
index fcfb221a..0f0bf01e 100644
--- a/qemu/target-arm/cpu.c
+++ b/qemu/target-arm/cpu.c
@@ -469,12 +469,16 @@ static void arm1026_initfn(struct uc_struct *uc, Object *obj, void *opaque)
cpu->reset_auxcr = 1;
{
/* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
- ARMCPRegInfo ifar = {
- .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW,
- .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
- .resetvalue = 0
- };
+ ARMCPRegInfo ifar = { 0 };
+ ifar.name = "IFAR";
+ ifar.cp = 15;
+ ifar.crn = 6;
+ ifar.crm = 0;
+ ifar.opc1 = 0;
+ ifar.opc2 = 1;
+ ifar.access = PL1_RW;
+ ifar.fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]);
+ ifar.resetvalue = 0;
define_one_arm_cp_reg(cpu, &ifar);
}
}
@@ -631,10 +635,10 @@ static void arm_v7m_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
}
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
- { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { "L2LOCKDOWN", 15, 9, 0, 0,1,0, 0,
+ ARM_CP_CONST, PL1_RW, NULL, 0, },
+ { "L2AUXCR", 15, 9, 0, 0,1,2, 0,
+ ARM_CP_CONST, PL1_RW, NULL, 0, },
REGINFO_SENTINEL
};
@@ -680,28 +684,28 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
/* power_control should be set to maximum latency. Again,
* default to 0 and set by private hook
*/
- { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
- { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
- { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
- .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
- { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
+ { "A9_PWRCTL", 15,15,0, 0,0,0, 0,
+ 0, PL1_RW, NULL, 0,
+ offsetof(CPUARMState, cp15.c15_power_control) },
+ { "A9_DIAG", 15,15,0, 0,0,1, 0,
+ 0, PL1_RW, NULL, 0,
+ offsetof(CPUARMState, cp15.c15_diagnostic) },
+ { "A9_PWRDIAG",15,15,0, 0,0,2, 0,
+ 0, PL1_RW, NULL, 0,
+ offsetof(CPUARMState, cp15.c15_power_diagnostic) },
+ { "NEONBUSY", 15,15,1, 0,0,0, 0,
+ ARM_CP_CONST, PL1_RW, NULL, 0, },
/* TLB lockdown control */
- { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
- .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
- { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
- .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
- { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
- .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
- { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
- .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
- { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
- .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
+ { "TLB_LOCKR", 15,15,4, 0,5,2, 0,
+ ARM_CP_NOP, PL1_W, NULL, 0 },
+ { "TLB_LOCKW", 15,15,4, 0,5,4, 0,
+ ARM_CP_NOP, PL1_W, NULL, 0, },
+ { "TLB_VA", 15,15,5, 0,5,2, 0,
+ ARM_CP_CONST, PL1_RW, NULL, 0, },
+ { "TLB_PA", 15,15,6, 0,5,2, 0,
+ ARM_CP_CONST, PL1_RW, NULL, 0 },
+ { "TLB_ATTR", 15,15,7, 0,5,2, 0,
+ ARM_CP_CONST, PL1_RW, NULL, 0, },
REGINFO_SENTINEL
};
@@ -759,12 +763,12 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY
- { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
- .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
- .writefn = arm_cp_write_ignore, },
+ { "L2CTLR", 15,9,0, 0,1,2, 0,
+ 0, PL1_RW, NULL, 0, 0, NULL, a15_l2ctlr_read,
+ arm_cp_write_ignore, },
#endif
- { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { "L2ECTLR", 15,9,0, 0,1,3, 0,
+ ARM_CP_CONST, PL1_RW, NULL, 0 },
REGINFO_SENTINEL
};
@@ -1005,43 +1009,42 @@ typedef struct ARMCPUInfo {
static const ARMCPUInfo arm_cpus[] = {
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
- { .name = "arm926", .initfn = arm926_initfn },
- { .name = "arm946", .initfn = arm946_initfn },
- { .name = "arm1026", .initfn = arm1026_initfn },
+ { "arm926", arm926_initfn },
+ { "arm946", arm946_initfn },
+ { "arm1026", arm1026_initfn },
/* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
* older core than plain "arm1136". In particular this does not
* have the v6K features.
*/
- { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
- { .name = "arm1136", .initfn = arm1136_initfn },
- { .name = "arm1176", .initfn = arm1176_initfn },
- { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
- { .name = "cortex-m3", .initfn = cortex_m3_initfn,
- .class_init = arm_v7m_class_init },
- { .name = "cortex-a8", .initfn = cortex_a8_initfn },
- { .name = "cortex-a9", .initfn = cortex_a9_initfn },
- { .name = "cortex-a15", .initfn = cortex_a15_initfn },
- { .name = "ti925t", .initfn = ti925t_initfn },
- { .name = "sa1100", .initfn = sa1100_initfn },
- { .name = "sa1110", .initfn = sa1110_initfn },
- { .name = "pxa250", .initfn = pxa250_initfn },
- { .name = "pxa255", .initfn = pxa255_initfn },
- { .name = "pxa260", .initfn = pxa260_initfn },
- { .name = "pxa261", .initfn = pxa261_initfn },
- { .name = "pxa262", .initfn = pxa262_initfn },
+ { "arm1136-r2", arm1136_r2_initfn },
+ { "arm1136", arm1136_initfn },
+ { "arm1176", arm1176_initfn },
+ { "arm11mpcore", arm11mpcore_initfn },
+ { "cortex-m3", cortex_m3_initfn, arm_v7m_class_init },
+ { "cortex-a8", cortex_a8_initfn },
+ { "cortex-a9", cortex_a9_initfn },
+ { "cortex-a15", cortex_a15_initfn },
+ { "ti925t", ti925t_initfn },
+ { "sa1100", sa1100_initfn },
+ { "sa1110", sa1110_initfn },
+ { "pxa250", pxa250_initfn },
+ { "pxa255", pxa255_initfn },
+ { "pxa260", pxa260_initfn },
+ { "pxa261", pxa261_initfn },
+ { "pxa262", pxa262_initfn },
/* "pxa270" is an alias for "pxa270-a0" */
- { .name = "pxa270", .initfn = pxa270a0_initfn },
- { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
- { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
- { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
- { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
- { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
- { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
+ { "pxa270", pxa270a0_initfn },
+ { "pxa270-a0", pxa270a0_initfn },
+ { "pxa270-a1", pxa270a1_initfn },
+ { "pxa270-b0", pxa270b0_initfn },
+ { "pxa270-b1", pxa270b1_initfn },
+ { "pxa270-c0", pxa270c0_initfn },
+ { "pxa270-c5", pxa270c5_initfn },
#ifdef CONFIG_USER_ONLY
- { .name = "any", .initfn = arm_any_initfn },
+ { "any", arm_any_initfn },
#endif
#endif
- { .name = NULL }
+ { NULL }
};
static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
@@ -1073,13 +1076,12 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
static void cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
{
- TypeInfo type_info = {
- .parent = TYPE_ARM_CPU,
- .instance_size = sizeof(ARMCPU),
- .instance_init = info->initfn,
- .class_size = sizeof(ARMCPUClass),
- .class_init = info->class_init,
- };
+ TypeInfo type_info = { 0 };
+ type_info.parent = TYPE_ARM_CPU;
+ type_info.instance_size = sizeof(ARMCPU);
+ type_info.instance_init = info->initfn;
+ type_info.class_size = sizeof(ARMCPUClass);
+ type_info.class_init = info->class_init;
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
type_register(uc, &type_info);
@@ -1088,20 +1090,19 @@ static void cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
void arm_cpu_register_types(void *opaque)
{
- const TypeInfo arm_cpu_type_info = {
- .name = TYPE_ARM_CPU,
- .parent = TYPE_CPU,
- .instance_userdata = opaque,
- .instance_size = sizeof(ARMCPU),
- .instance_init = arm_cpu_initfn,
- .instance_post_init = arm_cpu_post_init,
- .instance_finalize = arm_cpu_finalizefn,
- .abstract = true,
- .class_size = sizeof(ARMCPUClass),
- .class_init = arm_cpu_class_init,
- };
-
const ARMCPUInfo *info = arm_cpus;
+
+ TypeInfo arm_cpu_type_info = { 0 };
+ arm_cpu_type_info.name = TYPE_ARM_CPU,
+ arm_cpu_type_info.parent = TYPE_CPU,
+ arm_cpu_type_info.instance_userdata = opaque,
+ arm_cpu_type_info.instance_size = sizeof(ARMCPU),
+ arm_cpu_type_info.instance_init = arm_cpu_initfn,
+ arm_cpu_type_info.instance_post_init = arm_cpu_post_init,
+ arm_cpu_type_info.instance_finalize = arm_cpu_finalizefn,
+ arm_cpu_type_info.abstract = true,
+ arm_cpu_type_info.class_size = sizeof(ARMCPUClass),
+ arm_cpu_type_info.class_init = arm_cpu_class_init,
type_register_static(opaque, &arm_cpu_type_info);
diff --git a/qemu/target-arm/cpu.h b/qemu/target-arm/cpu.h
index aa16f7d5..5314cb4f 100644
--- a/qemu/target-arm/cpu.h
+++ b/qemu/target-arm/cpu.h
@@ -1146,7 +1146,7 @@ struct ARMCPRegInfo {
#define CPREG_FIELD64(env, ri) \
(*(uint64_t *)((char *)(env) + (ri)->fieldoffset))
-#define REGINFO_SENTINEL { .type = ARM_CP_SENTINEL }
+#define REGINFO_SENTINEL { NULL, 0,0,0,0,0,0, 0, ARM_CP_SENTINEL, 0, NULL, 0,0,0,0,0,0,0,0, }
void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
const ARMCPRegInfo *regs, void *opaque);
diff --git a/qemu/target-arm/cpu64.c b/qemu/target-arm/cpu64.c
index fcccd996..b86d9235 100644
--- a/qemu/target-arm/cpu64.c
+++ b/qemu/target-arm/cpu64.c
@@ -38,48 +38,35 @@ static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY
- { .name = "L2CTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 2,
- .access = PL1_RW, .readfn = a57_l2ctlr_read,
- .writefn = arm_cp_write_ignore },
- { .name = "L2CTLR",
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 2,
- .access = PL1_RW, .readfn = a57_l2ctlr_read,
- .writefn = arm_cp_write_ignore },
+ { "L2CTLR_EL1", 0, 11,0, 3,1,2, ARM_CP_STATE_AA64,
+ 0, PL1_RW, NULL, 0, 0,
+ NULL, a57_l2ctlr_read, arm_cp_write_ignore, },
+ { "L2CTLR", 15, 9,0, 0,1,2, 0,
+ 0, PL1_RW, NULL, 0, 0,
+ NULL, a57_l2ctlr_read, arm_cp_write_ignore, },
#endif
- { .name = "L2ECTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 11, .crm = 0, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2ECTLR",
- .cp = 15, .opc1 = 1, .crn = 9, .crm = 0, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2ACTLR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 0, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUACTLR",
- .cp = 15, .opc1 = 0, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "CPUECTLR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUECTLR",
- .cp = 15, .opc1 = 1, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "CPUMERRSR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "CPUMERRSR",
- .cp = 15, .opc1 = 2, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "L2MERRSR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 2, .opc2 = 3,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "L2MERRSR",
- .cp = 15, .opc1 = 3, .crm = 15,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 },
+ { "L2ECTLR_EL1", 0,11,0, 3,1,3, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_RW, NULL, 0, },
+ { "L2ECTLR", 15,9,0, 0,1,3, 0,
+ ARM_CP_CONST, PL1_RW, NULL, 0, },
+ { "L2ACTLR", 0,15,0, 3,1,0, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_RW, NULL, 0 },
+ { "CPUACTLR_EL1", 0,15,2, 3,1,0, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_RW, NULL, 0 },
+ { "CPUACTLR", 15,0,15, 0,0,0, 0,
+ ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0, },
+ { "CPUECTLR_EL1", 0,15,2, 3,1,1, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_RW, NULL, 0, },
+ { "CPUECTLR", 15,0,15, 0,1,0, 0,
+ ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0, },
+ { "CPUMERRSR_EL1", 0,15,2, 3,1,2, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_RW, NULL, 0 },
+ { "CPUMERRSR", 15,0,15, 0,2,0, 0,
+ ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0 },
+ { "L2MERRSR_EL1", 0,15,2, 3,1,3, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_RW, NULL, 0 },
+ { "L2MERRSR", 15,0,15, 0,3,0, 0,
+ ARM_CP_CONST | ARM_CP_64BIT, PL1_RW, NULL, 0 },
REGINFO_SENTINEL
};
@@ -159,11 +146,11 @@ typedef struct ARMCPUInfo {
} ARMCPUInfo;
static const ARMCPUInfo aarch64_cpus[] = {
- { .name = "cortex-a57", .initfn = aarch64_a57_initfn },
+ { "cortex-a57", aarch64_a57_initfn },
#ifdef CONFIG_USER_ONLY
- { .name = "any", .initfn = aarch64_any_initfn },
+ { "any", aarch64_any_initfn },
#endif
- { .name = NULL }
+ { NULL }
};
static void aarch64_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
@@ -202,13 +189,12 @@ static void aarch64_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *
static void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
{
- TypeInfo type_info = {
- .parent = TYPE_AARCH64_CPU,
- .instance_size = sizeof(ARMCPU),
- .instance_init = info->initfn,
- .class_size = sizeof(ARMCPUClass),
- .class_init = info->class_init,
- };
+ TypeInfo type_info = { 0 };
+ type_info.parent = TYPE_AARCH64_CPU;
+ type_info.instance_size = sizeof(ARMCPU);
+ type_info.instance_init = info->initfn;
+ type_info.class_size = sizeof(ARMCPUClass);
+ type_info.class_init = info->class_init;
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
type_register(uc, &type_info);
@@ -217,19 +203,18 @@ static void aarch64_cpu_register(struct uc_struct *uc, const ARMCPUInfo *info)
void aarch64_cpu_register_types(void *opaque)
{
- static const TypeInfo aarch64_cpu_type_info = {
- .name = TYPE_AARCH64_CPU,
- .parent = TYPE_ARM_CPU,
- .instance_size = sizeof(ARMCPU),
- .instance_init = aarch64_cpu_initfn,
- .instance_finalize = aarch64_cpu_finalizefn,
- .abstract = true,
- .class_size = sizeof(AArch64CPUClass),
- .class_init = aarch64_cpu_class_init,
- };
-
const ARMCPUInfo *info = aarch64_cpus;
+ static TypeInfo aarch64_cpu_type_info = { 0 };
+ aarch64_cpu_type_info.name = TYPE_AARCH64_CPU;
+ aarch64_cpu_type_info.parent = TYPE_ARM_CPU;
+ aarch64_cpu_type_info.instance_size = sizeof(ARMCPU);
+ aarch64_cpu_type_info.instance_init = aarch64_cpu_initfn;
+ aarch64_cpu_type_info.instance_finalize = aarch64_cpu_finalizefn;
+ aarch64_cpu_type_info.abstract = true;
+ aarch64_cpu_type_info.class_size = sizeof(AArch64CPUClass);
+ aarch64_cpu_type_info.class_init = aarch64_cpu_class_init;
+
type_register_static(opaque, &aarch64_cpu_type_info);
while (info->name) {
diff --git a/qemu/target-arm/crypto_helper.c b/qemu/target-arm/crypto_helper.c
index dd60d0b8..59988edd 100644
--- a/qemu/target-arm/crypto_helper.c
+++ b/qemu/target-arm/crypto_helper.c
@@ -28,15 +28,14 @@ void HELPER(crypto_aese)(CPUARMState *env, uint32_t rd, uint32_t rm,
static uint8_t const * const sbox[2] = { AES_sbox, AES_isbox };
static uint8_t const * const shift[2] = { AES_shifts, AES_ishifts };
- union CRYPTO_STATE rk = { .l = {
- float64_val(env->vfp.regs[rm]),
- float64_val(env->vfp.regs[rm + 1])
- } };
- union CRYPTO_STATE st = { .l = {
- float64_val(env->vfp.regs[rd]),
- float64_val(env->vfp.regs[rd + 1])
- } };
+ union CRYPTO_STATE rk;
+ union CRYPTO_STATE st;
int i;
+
+ rk.l[0] = float64_val(env->vfp.regs[rm]);
+ rk.l[1] = float64_val(env->vfp.regs[rm + 1]);
+ st.l[0] = float64_val(env->vfp.regs[rd]);
+ st.l[1] = float64_val(env->vfp.regs[rd + 1]);
assert(decrypt < 2);
@@ -189,11 +188,10 @@ void HELPER(crypto_aesmc)(CPUARMState *env, uint32_t rd, uint32_t rm,
0x92b479a7, 0x99b970a9, 0x84ae6bbb, 0x8fa362b5,
0xbe805d9f, 0xb58d5491, 0xa89a4f83, 0xa397468d,
} };
- union CRYPTO_STATE st = { .l = {
- float64_val(env->vfp.regs[rm]),
- float64_val(env->vfp.regs[rm + 1])
- } };
+ union CRYPTO_STATE st;
int i;
+ st.l[0] = float64_val(env->vfp.regs[rm]);
+ st.l[1] = float64_val(env->vfp.regs[rm + 1]);
assert(decrypt < 2);
@@ -231,18 +229,15 @@ static uint32_t maj(uint32_t x, uint32_t y, uint32_t z)
void HELPER(crypto_sha1_3reg)(CPUARMState *env, uint32_t rd, uint32_t rn,
uint32_t rm, uint32_t op)
{
- union CRYPTO_STATE d = { .l = {
- float64_val(env->vfp.regs[rd]),
- float64_val(env->vfp.regs[rd + 1])
- } };
- union CRYPTO_STATE n = { .l = {
- float64_val(env->vfp.regs[rn]),
- float64_val(env->vfp.regs[rn + 1])
- } };
- union CRYPTO_STATE m = { .l = {
- float64_val(env->vfp.regs[rm]),
- float64_val(env->vfp.regs[rm + 1])
- } };
+ union CRYPTO_STATE d;
+ union CRYPTO_STATE n;
+ union CRYPTO_STATE m;
+ d.l[0] = float64_val(env->vfp.regs[rd]);
+ d.l[1] = float64_val(env->vfp.regs[rd + 1]);
+ n.l[0] = float64_val(env->vfp.regs[rn]);
+ n.l[1] = float64_val(env->vfp.regs[rn + 1]);
+ m.l[0] = float64_val(env->vfp.regs[rm]);
+ m.l[1] = float64_val(env->vfp.regs[rm + 1]);
if (op == 3) { /* sha1su0 */
d.l[0] ^= d.l[1] ^ m.l[0];
@@ -281,10 +276,9 @@ void HELPER(crypto_sha1_3reg)(CPUARMState *env, uint32_t rd, uint32_t rn,
void HELPER(crypto_sha1h)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
- union CRYPTO_STATE m = { .l = {
- float64_val(env->vfp.regs[rm]),
- float64_val(env->vfp.regs[rm + 1])
- } };
+ union CRYPTO_STATE m;
+ m.l[0] = float64_val(env->vfp.regs[rm]);
+ m.l[1] = float64_val(env->vfp.regs[rm + 1]);
m.words[0] = ror32(m.words[0], 2);
m.words[1] = m.words[2] = m.words[3] = 0;
@@ -295,14 +289,12 @@ void HELPER(crypto_sha1h)(CPUARMState *env, uint32_t rd, uint32_t rm)
void HELPER(crypto_sha1su1)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
- union CRYPTO_STATE d = { .l = {
- float64_val(env->vfp.regs[rd]),
- float64_val(env->vfp.regs[rd + 1])
- } };
- union CRYPTO_STATE m = { .l = {
- float64_val(env->vfp.regs[rm]),
- float64_val(env->vfp.regs[rm + 1])
- } };
+ union CRYPTO_STATE d;
+ union CRYPTO_STATE m;
+ d.l[0] = float64_val(env->vfp.regs[rd]);
+ d.l[1] = float64_val(env->vfp.regs[rd + 1]);
+ m.l[0] = float64_val(env->vfp.regs[rm]);
+ m.l[1] = float64_val(env->vfp.regs[rm + 1]);
d.words[0] = rol32(d.words[0] ^ m.words[1], 1);
d.words[1] = rol32(d.words[1] ^ m.words[2], 1);
@@ -341,19 +333,16 @@ static uint32_t s1(uint32_t x)
void HELPER(crypto_sha256h)(CPUARMState *env, uint32_t rd, uint32_t rn,
uint32_t rm)
{
- union CRYPTO_STATE d = { .l = {
- float64_val(env->vfp.regs[rd]),
- float64_val(env->vfp.regs[rd + 1])
- } };
- union CRYPTO_STATE n = { .l = {
- float64_val(env->vfp.regs[rn]),
- float64_val(env->vfp.regs[rn + 1])
- } };
- union CRYPTO_STATE m = { .l = {
- float64_val(env->vfp.regs[rm]),
- float64_val(env->vfp.regs[rm + 1])
- } };
int i;
+ union CRYPTO_STATE d;
+ union CRYPTO_STATE n;
+ union CRYPTO_STATE m;
+ d.l[0] = float64_val(env->vfp.regs[rd]);
+ d.l[1] = float64_val(env->vfp.regs[rd + 1]);
+ n.l[0] = float64_val(env->vfp.regs[rn]);
+ n.l[1] = float64_val(env->vfp.regs[rn + 1]);
+ m.l[0] = float64_val(env->vfp.regs[rm]);
+ m.l[1] = float64_val(env->vfp.regs[rm + 1]);
for (i = 0; i < 4; i++) {
uint32_t t = cho(n.words[0], n.words[1], n.words[2]) + n.words[3]
@@ -379,19 +368,17 @@ void HELPER(crypto_sha256h)(CPUARMState *env, uint32_t rd, uint32_t rn,
void HELPER(crypto_sha256h2)(CPUARMState *env, uint32_t rd, uint32_t rn,
uint32_t rm)
{
- union CRYPTO_STATE d = { .l = {
- float64_val(env->vfp.regs[rd]),
- float64_val(env->vfp.regs[rd + 1])
- } };
- union CRYPTO_STATE n = { .l = {
- float64_val(env->vfp.regs[rn]),
- float64_val(env->vfp.regs[rn + 1])
- } };
- union CRYPTO_STATE m = { .l = {
- float64_val(env->vfp.regs[rm]),
- float64_val(env->vfp.regs[rm + 1])
- } };
+ union CRYPTO_STATE d;
+ union CRYPTO_STATE n;
+ union CRYPTO_STATE m;
int i;
+
+ d.l[0] = float64_val(env->vfp.regs[rd]);
+ d.l[1] = float64_val(env->vfp.regs[rd + 1]);
+ n.l[0] = float64_val(env->vfp.regs[rn]);
+ n.l[1] = float64_val(env->vfp.regs[rn + 1]);
+ m.l[0] = float64_val(env->vfp.regs[rm]);
+ m.l[1] = float64_val(env->vfp.regs[rm + 1]);
for (i = 0; i < 4; i++) {
uint32_t t = cho(d.words[0], d.words[1], d.words[2]) + d.words[3]
@@ -409,14 +396,12 @@ void HELPER(crypto_sha256h2)(CPUARMState *env, uint32_t rd, uint32_t rn,
void HELPER(crypto_sha256su0)(CPUARMState *env, uint32_t rd, uint32_t rm)
{
- union CRYPTO_STATE d = { .l = {
- float64_val(env->vfp.regs[rd]),
- float64_val(env->vfp.regs[rd + 1])
- } };
- union CRYPTO_STATE m = { .l = {
- float64_val(env->vfp.regs[rm]),
- float64_val(env->vfp.regs[rm + 1])
- } };
+ union CRYPTO_STATE d;
+ union CRYPTO_STATE m;
+ d.l[0] = float64_val(env->vfp.regs[rd]);
+ d.l[1] = float64_val(env->vfp.regs[rd + 1]);
+ m.l[0] = float64_val(env->vfp.regs[rm]);
+ m.l[1] = float64_val(env->vfp.regs[rm + 1]);
d.words[0] += s0(d.words[1]);
d.words[1] += s0(d.words[2]);
@@ -430,18 +415,15 @@ void HELPER(crypto_sha256su0)(CPUARMState *env, uint32_t rd, uint32_t rm)
void HELPER(crypto_sha256su1)(CPUARMState *env, uint32_t rd, uint32_t rn,
uint32_t rm)
{
- union CRYPTO_STATE d = { .l = {
- float64_val(env->vfp.regs[rd]),
- float64_val(env->vfp.regs[rd + 1])
- } };
- union CRYPTO_STATE n = { .l = {
- float64_val(env->vfp.regs[rn]),
- float64_val(env->vfp.regs[rn + 1])
- } };
- union CRYPTO_STATE m = { .l = {
- float64_val(env->vfp.regs[rm]),
- float64_val(env->vfp.regs[rm + 1])
- } };
+ union CRYPTO_STATE d;
+ union CRYPTO_STATE n;
+ union CRYPTO_STATE m;
+ d.l[0] = float64_val(env->vfp.regs[rd]);
+ d.l[1] = float64_val(env->vfp.regs[rd + 1]);
+ n.l[0] = float64_val(env->vfp.regs[rn]);
+ n.l[1] = float64_val(env->vfp.regs[rn + 1]);
+ m.l[0] = float64_val(env->vfp.regs[rm]);
+ m.l[1] = float64_val(env->vfp.regs[rm + 1]);
d.words[0] += s1(m.words[2]) + n.words[1];
d.words[1] += s1(m.words[3]) + n.words[2];
diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c
index 69f7cbea..445d2ead 100644
--- a/qemu/target-arm/helper.c
+++ b/qemu/target-arm/helper.c
@@ -314,14 +314,12 @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
static const ARMCPRegInfo cp_reginfo[] = {
- { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
- .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
- { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
- .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
+ { "FCSEIDR", 15,13,0, 0,0,0, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c13_fcse),
+ NULL, NULL, fcse_write, NULL, raw_write, NULL, },
+ { "CONTEXTIDR", 0,13,0, 3,0,1, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.contextidr_el1),
+ NULL, NULL, contextidr_write, NULL, raw_write, NULL, },
REGINFO_SENTINEL
};
@@ -330,19 +328,17 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] = {
* definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
*/
/* MMU Domain access control / MPU write buffer control */
- { .name = "DACR", .cp = 15,
- .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
- .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
+ { "DACR", 15,3,CP_ANY, 0,CP_ANY,CP_ANY, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c3),
+ NULL, NULL, dacr_write, NULL, raw_write, NULL, },
/* ??? This covers not just the impdef TLB lockdown registers but also
* some v7VMSA registers relating to TEX remap, so it is overly broad.
*/
- { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
- .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
+ { "TLB_LOCKDOWN", 15,10,CP_ANY, 0,CP_ANY,CP_ANY, 0,
+ ARM_CP_NOP, PL1_RW, },
/* Cache maintenance ops; some of this space may be overridden later. */
- { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
- .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
- .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
+ { "CACHEMAINT", 15,7,CP_ANY, 0,0,CP_ANY, 0,
+ ARM_CP_NOP | ARM_CP_OVERRIDE, PL1_W, },
REGINFO_SENTINEL
};
@@ -350,8 +346,8 @@ static const ARMCPRegInfo not_v6_cp_reginfo[] = {
/* Not all pre-v6 cores implemented this WFI, so this is slightly
* over-broad.
*/
- { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
- .access = PL1_W, .type = ARM_CP_WFI },
+ { "WFI_v5", 15,7,8, 0,0,2, 0,
+ ARM_CP_WFI, PL1_W, },
REGINFO_SENTINEL
};
@@ -359,44 +355,41 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] = {
/* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
* is UNPREDICTABLE; we choose to NOP as most implementations do).
*/
- { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
- .access = PL1_W, .type = ARM_CP_WFI },
+ { "WFI_v6", 15,7,0, 0,0,4, 0,
+ ARM_CP_WFI, PL1_W, },
/* L1 cache lockdown. Not architectural in v6 and earlier but in practice
* implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
* OMAPCP will override this space.
*/
- { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
- .resetvalue = 0 },
- { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
- .resetvalue = 0 },
+ { "DLOCKDOWN", 15,9,0, 0,0,0, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c9_data), },
+ { "ILOCKDOWN", 15,9,0, 0,0,1, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c9_insn), },
/* v6 doesn't have the cache ID registers but Linux reads them anyway */
- { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
- .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
- .resetvalue = 0 },
+ { "DUMMY", 15,0,0, 0,1,CP_ANY, 0,
+ ARM_CP_CONST | ARM_CP_NO_MIGRATE, PL1_R, NULL, 0 },
/* We don't implement pre-v7 debug but most CPUs had at least a DBGDIDR;
* implementing it as RAZ means the "debug architecture version" bits
* will read as a reserved value, which should cause Linux to not try
* to use the debug hardware.
*/
- { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { "DBGDIDR", 14,0,0, 0,0,0, 0,
+ ARM_CP_CONST, PL0_R, NULL, 0 },
/* MMU TLB control. Note that the wildcarding means we cover not just
* the unified TLB ops but also the dside/iside/inner-shareable variants.
*/
- { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
- .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
- .type = ARM_CP_NO_MIGRATE },
- { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
- .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
- .type = ARM_CP_NO_MIGRATE },
- { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
- .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
- .type = ARM_CP_NO_MIGRATE },
- { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
- .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
- .type = ARM_CP_NO_MIGRATE },
+ { "TLBIALL", 15,8,CP_ANY, 0,CP_ANY,0, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbiall_write, },
+ { "TLBIMVA", 15,8,CP_ANY, 0,CP_ANY,1, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbimva_write, },
+ { "TLBIASID", 15,8,CP_ANY, 0,CP_ANY,2, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbiasid_write, },
+ { "TLBIMVAA", 15,8,CP_ANY, 0,CP_ANY,3, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbimvaa_write, },
REGINFO_SENTINEL
};
@@ -436,28 +429,24 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static const ARMCPRegInfo v6_cp_reginfo[] = {
/* prefetch by MVA in v6, NOP in v7 */
- { .name = "MVA_prefetch",
- .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
- .access = PL1_W, .type = ARM_CP_NOP },
- { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
- .access = PL0_W, .type = ARM_CP_NOP },
- { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
- .access = PL0_W, .type = ARM_CP_NOP },
- { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
- .access = PL0_W, .type = ARM_CP_NOP },
- { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
- .access = PL1_RW,
- .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
- .resetvalue = 0, },
+ { "MVA_prefetch", 15,7,13, 0,0,1, 0,
+ ARM_CP_NOP, PL1_W, },
+ { "ISB", 15,7,5, 0,0,4, 0,
+ ARM_CP_NOP, PL0_W, },
+ { "DSB", 15,7,10, 0,0,4, 0,
+ ARM_CP_NOP, PL0_W, },
+ { "DMB", 15,7,10, 0,0,5, 0,
+ ARM_CP_NOP, PL0_W, },
+ { "IFAR", 15,6,0, 0,0,2, 0,
+ 0, PL1_RW, NULL, 0, offsetofhigh32(CPUARMState, cp15.far_el[1]), },
/* Watchpoint Fault Address Register : should actually only be present
* for 1136, 1176, 11MPCore.
*/
- { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
- { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
- .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
- .resetvalue = 0, .writefn = cpacr_write },
+ { "WFAR", 15,6,0, 0,0,1, 0,
+ ARM_CP_CONST, PL1_RW, NULL, 0, },
+ { "CPACR", 0,1,0, 3,0,2, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c1_coproc),
+ NULL, NULL, cpacr_write },
REGINFO_SENTINEL
};
@@ -697,8 +686,8 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
static const ARMCPRegInfo v7_cp_reginfo[] = {
/* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
- { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
- .access = PL1_W, .type = ARM_CP_NOP },
+ { "NOP", 15,7,0, 0,0,4, 0,
+ ARM_CP_NOP, PL1_W, },
/* Performance monitors are implementation defined in v7,
* but with an ARM recommended set of registers, which we
* follow (although we don't actually implement any counters)
@@ -710,175 +699,151 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
* For the cases controlled by PMUSERENR we must set .access to PL0_RW
* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
*/
- { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
- .access = PL0_RW, .type = ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
- .writefn = pmcntenset_write,
- .accessfn = pmreg_access,
- .raw_writefn = raw_write },
- { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
- .access = PL0_RW, .accessfn = pmreg_access,
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
- .writefn = pmcntenset_write, .raw_writefn = raw_write },
- { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
- .access = PL0_RW,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
- .accessfn = pmreg_access,
- .writefn = pmcntenclr_write,
- .type = ARM_CP_NO_MIGRATE },
- { .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
- .access = PL0_RW, .accessfn = pmreg_access,
- .type = ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
- .writefn = pmcntenclr_write },
- { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
- .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
- .accessfn = pmreg_access,
- .writefn = pmovsr_write,
- .raw_writefn = raw_write },
+ { "PMCNTENSET", 15,9,12, 0,0,1, 0,
+ ARM_CP_NO_MIGRATE, PL0_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.c9_pmcnten),
+ pmreg_access, NULL, pmcntenset_write, NULL, raw_write },
+ { "PMCNTENSET_EL0", 0,9,12, 3,3,1, ARM_CP_STATE_AA64,
+ 0, PL0_RW, NULL, 0, offsetof(CPUARMState, cp15.c9_pmcnten),
+ pmreg_access, NULL, pmcntenset_write, NULL, raw_write },
+ { "PMCNTENCLR", 15,9,12, 0,0,2, 0,
+ ARM_CP_NO_MIGRATE, PL0_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.c9_pmcnten),
+ pmreg_access, NULL, pmcntenclr_write, },
+ { "PMCNTENCLR_EL0", 0,9,12, 3,3,2, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL0_RW, NULL, 0,offsetof(CPUARMState, cp15.c9_pmcnten),
+ pmreg_access, NULL, pmcntenclr_write },
+ { "PMOVSR", 15,9,12, 0,0,3, 0,
+ 0, PL0_RW, NULL, 0, offsetof(CPUARMState, cp15.c9_pmovsr),
+ pmreg_access, NULL, pmovsr_write, NULL, raw_write },
/* Unimplemented so WI. */
- { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
- .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
+ { "PMSWINC", 15,9,12, 0,0,4, 0,
+ ARM_CP_NOP, PL0_W, NULL, 0, 0,
+ pmreg_access, },
/* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
* We choose to RAZ/WI.
*/
- { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
- .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
- .accessfn = pmreg_access },
+ { "PMSELR", 15,9,12, 0,0,5, 0,
+ ARM_CP_CONST, PL0_RW, NULL, 0, 0,
+ pmreg_access },
#ifndef CONFIG_USER_ONLY
- { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
- .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
- .readfn = pmccntr_read, .writefn = pmccntr_write32,
- .accessfn = pmreg_access },
- { .name = "PMCCNTR_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
- .access = PL0_RW, .accessfn = pmreg_access,
- .type = ARM_CP_IO,
- .readfn = pmccntr_read, .writefn = pmccntr_write, },
+ { "PMCCNTR", 15,9,13, 0,0,0, 0,
+ ARM_CP_IO, PL0_RW, NULL, 0, 0,
+ pmreg_access, pmccntr_read, pmccntr_write32, },
+ { "PMCCNTR_EL0", 0,9,13, 3,3,0, ARM_CP_STATE_AA64,
+ ARM_CP_IO, PL0_RW, NULL, 0, 0,
+ pmreg_access, pmccntr_read, pmccntr_write, },
#endif
- { .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
- .writefn = pmccfiltr_write,
- .access = PL0_RW, .accessfn = pmreg_access,
- .type = ARM_CP_IO,
- .fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
- .resetvalue = 0, },
- { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
- .access = PL0_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
- .accessfn = pmreg_access, .writefn = pmxevtyper_write,
- .raw_writefn = raw_write },
+ { "PMCCFILTR_EL0", 0,14,15, 3,3,7, ARM_CP_STATE_AA64,
+ ARM_CP_IO, PL0_RW, NULL, 0, offsetof(CPUARMState, cp15.pmccfiltr_el0),
+ pmreg_access, NULL, pmccfiltr_write, },
+ { "PMXEVTYPER", 15,9,13, 0,0,1, 0,
+ 0, PL0_RW, NULL, 0, offsetof(CPUARMState, cp15.c9_pmxevtyper),
+ pmreg_access, NULL, pmxevtyper_write, NULL, raw_write },
/* Unimplemented, RAZ/WI. */
- { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
- .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
- .accessfn = pmreg_access },
- { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
- .access = PL0_R | PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
- .resetvalue = 0,
- .writefn = pmuserenr_write, .raw_writefn = raw_write },
- { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
- .resetvalue = 0,
- .writefn = pmintenset_write, .raw_writefn = raw_write },
- { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
- .resetvalue = 0, .writefn = pmintenclr_write, },
- { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .writefn = vbar_write,
- .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[1]),
- .resetvalue = 0 },
- { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
- .resetvalue = 0, .writefn = scr_write },
- { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
- .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
- { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
- .writefn = csselr_write, .resetvalue = 0 },
+ { "PMXEVCNTR", 15,9,13, 0,0,2, 0,
+ ARM_CP_CONST, PL0_RW, NULL, 0, 0,
+ pmreg_access },
+ { "PMUSERENR", 15,9,14, 0,0,0, 0,
+ 0, PL0_R | PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c9_pmuserenr),
+ NULL, NULL, pmuserenr_write, NULL, raw_write },
+ { "PMINTENSET", 15,9,14, 0,0,1, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten),
+ NULL, NULL, pmintenset_write, NULL, raw_write },
+ { "PMINTENCLR", 15,9,14, 0,0,2, 0,
+ ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c9_pminten),
+ NULL, NULL, pmintenclr_write, },
+ { "VBAR", 0,12,0, 3,0,0, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[1]),
+ NULL, NULL, vbar_write, },
+ { "SCR", 15,1,1, 0,0,0, 0,
+ 0, PL1_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.scr_el3),
+ NULL, NULL, scr_write },
+ { "CCSIDR", 0,0,0, 3,1,0, ARM_CP_STATE_BOTH,
+ ARM_CP_NO_MIGRATE, PL1_R, NULL, 0, 0,
+ NULL, ccsidr_read, },
+ { "CSSELR", 0,0,0, 3,2,0, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c0_cssel),
+ NULL, NULL, csselr_write, },
/* Auxiliary ID register: this actually has an IMPDEF value but for now
* just RAZ for all cores:
*/
- { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { "AIDR", 0,0,0, 3,1,7, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, 0 },
/* Auxiliary fault status registers: these also are IMPDEF, and we
* choose to RAZ/WI for all cores.
*/
- { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { "AFSR0_EL1", 0,5,1, 3,0,0, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_RW, NULL, 0 },
+ { "AFSR1_EL1", 0,5,1, 3,0,1, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_RW, NULL, 0 },
/* MAIR can just read-as-written because we don't implement caches
* and so don't need to care about memory attributes.
*/
- { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
- .resetvalue = 0 },
+ { "MAIR_EL1", 0,10,2, 3,0,0, ARM_CP_STATE_AA64,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.mair_el1), },
/* For non-long-descriptor page tables these are PRRR and NMRR;
* regardless they still act as reads-as-written for QEMU.
* The override is necessary because of the overly-broad TLB_LOCKDOWN
* definition.
*/
- { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
- .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
- .resetfn = arm_cp_reset_ignore },
- { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
- .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
- .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
- .resetfn = arm_cp_reset_ignore },
- { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
+ { "MAIR0", 15,10,2, 0,0,0, ARM_CP_STATE_AA32,
+ ARM_CP_OVERRIDE, PL1_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.mair_el1),
+ NULL, NULL, NULL, NULL, NULL, arm_cp_reset_ignore },
+ { "MAIR1", 15,10,2, 0,0,1, ARM_CP_STATE_AA32,
+ ARM_CP_OVERRIDE, PL1_RW, NULL, 0, offsetofhigh32(CPUARMState, cp15.mair_el1),
+ NULL, NULL, NULL, NULL, NULL, arm_cp_reset_ignore },
+ { "ISR_EL1", 0,12,1, 3,0,0, ARM_CP_STATE_BOTH,
+ ARM_CP_NO_MIGRATE, PL1_R, NULL, 0, 0,
+ NULL, isr_read },
/* 32 bit ITLB invalidates */
- { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
- { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
- { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
+ { "ITLBIALL", 15,8,5, 0,0,0, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbiall_write },
+ { "ITLBIMVA", 15,8,5, 0,0,1, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbimva_write },
+ { "ITLBIASID", 15,8,5, 0,0,2, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbiasid_write },
/* 32 bit DTLB invalidates */
- { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
- { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
- { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
+ { "DTLBIALL", 15,8,6, 0,0,0, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbiall_write },
+ { "DTLBIMVA", 15,8,6, 0,0,1, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbimva_write },
+ { "DTLBIASID", 15,8,6, 0,0,2, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbiasid_write },
/* 32 bit TLB invalidates */
- { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
- { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
- { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
- { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
+ { "TLBIALL", 15,8,7, 0,0,0, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbiall_write },
+ { "TLBIMVA", 15,8,7, 0,0,1, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbimva_write },
+ { "TLBIASID", 15,8,7, 0,0,2, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbiasid_write },
+ { "TLBIMVAA", 15,8,7, 0,0,3, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbimvaa_write },
REGINFO_SENTINEL
};
static const ARMCPRegInfo v7mp_cp_reginfo[] = {
/* 32 bit TLB invalidates, Inner Shareable */
- { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_is_write },
- { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_is_write },
- { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
- .writefn = tlbiasid_is_write },
- { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
- .writefn = tlbimvaa_is_write },
+ { "TLBIALLIS", 15,8,3, 0,0,0, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbiall_is_write },
+ { "TLBIMVAIS", 15,8,3, 0,0,1, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbimva_is_write },
+ { "TLBIASIDIS", 15,8,3, 0,0,2, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbiasid_is_write },
+ { "TLBIMVAAIS", 15,8,3, 0,0,3, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbimvaa_is_write },
REGINFO_SENTINEL
};
@@ -898,37 +863,28 @@ static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
}
static const ARMCPRegInfo t2ee_cp_reginfo[] = {
- { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
- .resetvalue = 0,
- .writefn = teecr_write },
- { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
- .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
- .accessfn = teehbr_access, .resetvalue = 0 },
+ { "TEECR", 14,0,0, 0,6,0, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, teecr),
+ NULL, NULL, teecr_write },
+ { "TEEHBR", 14,1,0, 0,6,0, 0,
+ 0, PL0_RW, NULL, 0, offsetof(CPUARMState, teehbr),
+ teehbr_access, },
REGINFO_SENTINEL
};
static const ARMCPRegInfo v6k_cp_reginfo[] = {
- { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
- .access = PL0_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
- { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
- .access = PL0_RW,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
- .resetfn = arm_cp_reset_ignore },
- { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
- .access = PL0_R|PL1_W,
- .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
- { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
- .access = PL0_R|PL1_W,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
- .resetfn = arm_cp_reset_ignore },
- { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
+ { "TPIDR_EL0", 0,13,0, 3,3,2, ARM_CP_STATE_AA64,
+ 0, PL0_RW, NULL, 0, offsetof(CPUARMState, cp15.tpidr_el0), },
+ { "TPIDRURW", 15,13,0, 0,0,2, 0,
+ 0, PL0_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.tpidr_el0),
+ NULL, NULL, NULL, NULL, NULL, arm_cp_reset_ignore },
+ { "TPIDRRO_EL0", 0,13,0, 3,3,3, ARM_CP_STATE_AA64,
+ 0, PL0_R|PL1_W, NULL, 0, offsetof(CPUARMState, cp15.tpidrro_el0) },
+ { "TPIDRURO", 15,13,0, 0,0,3, 0,
+ 0, PL0_R|PL1_W, NULL, 0, offsetoflow32(CPUARMState, cp15.tpidrro_el0),
+ NULL, NULL, NULL, NULL, NULL, arm_cp_reset_ignore },
+ { "TPIDR_EL1", 0,13,0, 3,0,4, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.tpidr_el1), },
REGINFO_SENTINEL
};
@@ -1107,133 +1063,67 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
* of software; writing it doesn't actually change the timer frequency.
* Our reset value matches the fixed frequency we implement the timer at.
*/
- { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
- .type = ARM_CP_NO_MIGRATE,
- .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
- .resetfn = arm_cp_reset_ignore,
- },
- { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
- .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
- .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
- .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
- },
+ { "CNTFRQ", 15,14,0, 0,0,0, 0,
+ ARM_CP_NO_MIGRATE, PL1_RW | PL0_R, NULL, 0, offsetoflow32(CPUARMState, cp15.c14_cntfrq),
+ gt_cntfrq_access, NULL,NULL, NULL,NULL, arm_cp_reset_ignore, },
+ { "CNTFRQ_EL0", 0,14,0, 3,3,0, ARM_CP_STATE_AA64,
+ 0, PL1_RW | PL0_R, NULL, (1000 * 1000 * 1000) / GTIMER_SCALE, offsetof(CPUARMState, cp15.c14_cntfrq),
+ gt_cntfrq_access, },
/* overall control: mostly access permissions */
- { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
- .resetvalue = 0,
- },
+ { "CNTKCTL", 0,14,1, 3,0,0, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c14_cntkctl), },
/* per-timer control */
- { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
- .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
- .accessfn = gt_ptimer_access,
- .fieldoffset = offsetoflow32(CPUARMState,
- cp15.c14_timer[GTIMER_PHYS].ctl),
- .resetfn = arm_cp_reset_ignore,
- .writefn = gt_ctl_write, .raw_writefn = raw_write,
- },
- { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
- .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
- .accessfn = gt_ptimer_access,
- .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
- .resetvalue = 0,
- .writefn = gt_ctl_write, .raw_writefn = raw_write,
- },
- { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
- .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
- .accessfn = gt_vtimer_access,
- .fieldoffset = offsetoflow32(CPUARMState,
- cp15.c14_timer[GTIMER_VIRT].ctl),
- .resetfn = arm_cp_reset_ignore,
- .writefn = gt_ctl_write, .raw_writefn = raw_write,
- },
- { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
- .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
- .accessfn = gt_vtimer_access,
- .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
- .resetvalue = 0,
- .writefn = gt_ctl_write, .raw_writefn = raw_write,
- },
+ { "CNTP_CTL", 15,14,2, 0,0,1, 0,
+ ARM_CP_IO | ARM_CP_NO_MIGRATE, PL1_RW | PL0_R, NULL, 0, offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
+ gt_ptimer_access, NULL, gt_ctl_write, NULL,raw_write, arm_cp_reset_ignore, },
+ { "CNTP_CTL_EL0", 0,14,2, 3,3,1, ARM_CP_STATE_AA64,
+ ARM_CP_IO, PL1_RW | PL0_R, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
+ gt_ptimer_access, NULL,gt_ctl_write, NULL,raw_write, },
+ { "CNTV_CTL", 15,14,3, 0,0,1, 0,
+ ARM_CP_IO | ARM_CP_NO_MIGRATE, PL1_RW | PL0_R, NULL, 0, offsetoflow32(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
+ gt_vtimer_access, NULL,gt_ctl_write, NULL,raw_write, arm_cp_reset_ignore, },
+ { "CNTV_CTL_EL0", 0,14,3, 3,3,1, ARM_CP_STATE_AA64,
+ ARM_CP_IO, PL1_RW | PL0_R, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
+ gt_vtimer_access, NULL,gt_ctl_write, NULL,raw_write, },
/* TimerValue views: a 32 bit downcounting view of the underlying state */
- { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
- .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
- .accessfn = gt_ptimer_access,
- .readfn = gt_tval_read, .writefn = gt_tval_write,
- },
- { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
- .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
- .readfn = gt_tval_read, .writefn = gt_tval_write,
- },
- { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
- .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
- .accessfn = gt_vtimer_access,
- .readfn = gt_tval_read, .writefn = gt_tval_write,
- },
- { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
- .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
- .readfn = gt_tval_read, .writefn = gt_tval_write,
- },
+ { "CNTP_TVAL", 15,14,2, 0,0,0, 0,
+ ARM_CP_NO_MIGRATE | ARM_CP_IO, PL1_RW | PL0_R, NULL, 0, 0,
+ gt_ptimer_access, gt_tval_read, gt_tval_write, },
+ { "CNTP_TVAL_EL0", 0,14,2, 3,3,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE | ARM_CP_IO, PL1_RW | PL0_R, NULL, 0, 0,
+ NULL, gt_tval_read, gt_tval_write, },
+ { "CNTV_TVAL", 15,14,3, 0,0,0, 0,
+ ARM_CP_NO_MIGRATE | ARM_CP_IO, PL1_RW | PL0_R, NULL, 0, 0,
+ gt_vtimer_access, gt_tval_read, gt_tval_write, },
+ { "CNTV_TVAL_EL0", 0,14,3, 3,3,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE | ARM_CP_IO, PL1_RW | PL0_R, NULL, 0, 0,
+ NULL, gt_tval_read, gt_tval_write, },
/* The counter itself */
- { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
- .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
- .accessfn = gt_pct_access,
- .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
- },
- { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
- .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
- .accessfn = gt_pct_access,
- .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
- },
- { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
- .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
- .accessfn = gt_vct_access,
- .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
- },
- { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
- .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
- .accessfn = gt_vct_access,
- .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
- },
+ { "CNTPCT", 15,0,14, 0,0, 0, 0,
+ ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, PL0_R, NULL, 0, 0,
+ gt_pct_access, gt_cnt_read,NULL, NULL,NULL, arm_cp_reset_ignore, },
+ { "CNTPCT_EL0", 0,14,0, 3,3,1, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE | ARM_CP_IO, PL0_R, NULL, 0, 0,
+ gt_pct_access, gt_cnt_read, NULL, NULL, NULL, gt_cnt_reset, },
+ { "CNTVCT", 15,0,14, 0,1,0, 0,
+ ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO, PL0_R, NULL, 0, 0,
+ gt_vct_access, gt_cnt_read,NULL, NULL,NULL, arm_cp_reset_ignore, },
+ { "CNTVCT_EL0", 0,14,0, 3,3,2, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE | ARM_CP_IO, PL0_R, NULL, 0, 0,
+ gt_vct_access, gt_cnt_read, NULL, NULL,NULL, gt_cnt_reset, },
/* Comparison value, indicating when the timer goes off */
- { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
- .access = PL1_RW | PL0_R,
- .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
- .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
- .writefn = gt_cval_write, .raw_writefn = raw_write,
- },
- { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
- .access = PL1_RW | PL0_R,
- .type = ARM_CP_IO,
- .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
- .resetvalue = 0, .accessfn = gt_vtimer_access,
- .writefn = gt_cval_write, .raw_writefn = raw_write,
- },
- { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
- .access = PL1_RW | PL0_R,
- .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
- .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
- .writefn = gt_cval_write, .raw_writefn = raw_write,
- },
- { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
- .access = PL1_RW | PL0_R,
- .type = ARM_CP_IO,
- .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
- .resetvalue = 0, .accessfn = gt_vtimer_access,
- .writefn = gt_cval_write, .raw_writefn = raw_write,
- },
+ { "CNTP_CVAL", 15, 0,14, 0,2, 0, 0,
+ ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE, PL1_RW | PL0_R, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
+ gt_ptimer_access, NULL, gt_cval_write, NULL, raw_write, arm_cp_reset_ignore, },
+ { "CNTP_CVAL_EL0", 0,14,2, 3,3,2, ARM_CP_STATE_AA64,
+ ARM_CP_IO, PL1_RW | PL0_R, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
+ gt_vtimer_access, NULL, gt_cval_write, NULL, raw_write, },
+ { "CNTV_CVAL", 15, 0,14, 0,3,0, 0,
+ ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE, PL1_RW | PL0_R, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
+ gt_vtimer_access, NULL, gt_cval_write, NULL, raw_write, arm_cp_reset_ignore, },
+ { "CNTV_CVAL_EL0", 0,14,3, 3,3,2, ARM_CP_STATE_AA64,
+ ARM_CP_IO, PL1_RW | PL0_R, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
+ gt_vtimer_access, NULL, gt_cval_write, NULL, raw_write, },
REGINFO_SENTINEL
};
@@ -1326,14 +1216,13 @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
#endif
static const ARMCPRegInfo vapa_cp_reginfo[] = {
- { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1),
- .writefn = par_write },
+ { "PAR", 15,7,4, 0,0,0, 0,
+ 0, PL1_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.par_el1),
+ NULL, NULL, par_write },
#ifndef CONFIG_USER_ONLY
- { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
- .access = PL1_W, .accessfn = ats_access,
- .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
+ { "ATS", 15,7,8, 0,0,CP_ANY, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ ats_access, NULL, ats_write },
#endif
REGINFO_SENTINEL
};
@@ -1391,55 +1280,37 @@ static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
}
static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
- { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
- .resetvalue = 0,
- .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
- { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
- .resetvalue = 0,
- .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
- { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
- .resetvalue = 0, },
- { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
- .resetvalue = 0, },
- { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
- { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
+ { "DATA_AP", 15,5,0, 0,0,0, 0,
+ ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.pmsav5_data_ap),
+ NULL, pmsav5_data_ap_read, pmsav5_data_ap_write, },
+ { "INSN_AP", 15,5,0, 0,0,1, 0,
+ ARM_CP_NO_MIGRATE,PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.pmsav5_insn_ap),
+ NULL, pmsav5_insn_ap_read, pmsav5_insn_ap_write, },
+ { "DATA_EXT_AP", 15,5,0, 0,0,2, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.pmsav5_data_ap), },
+ { "INSN_EXT_AP", 15,5,0, 0,0,3, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.pmsav5_insn_ap), },
+ { "DCACHE_CFG", 15,2,0, 0,0,0, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c2_data), },
+ { "ICACHE_CFG", 15,2,0, 0,0,1, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c2_insn), },
/* Protection region base and size registers */
- { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
- .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
- { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
- .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
- { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
- .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
- { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
- .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
- { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
- .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
- { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
- .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
- { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
- .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
- { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
- .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
- .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
+ { "946_PRBS0", 15,6,0, 0,0,CP_ANY, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c6_region[0]) },
+ { "946_PRBS1", 15,6,1, 0,0,CP_ANY, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c6_region[1]) },
+ { "946_PRBS2", 15,6,2, 0,0,CP_ANY, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c6_region[2]) },
+ { "946_PRBS3", 15,6,3, 0,0,CP_ANY, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c6_region[3]) },
+ { "946_PRBS4", 15,6,4, 0,0,CP_ANY, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c6_region[4]) },
+ { "946_PRBS5", 15,6,5, 0,0,CP_ANY, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c6_region[5]) },
+ { "946_PRBS6", 15,6,6, 0,0,CP_ANY, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c6_region[6]) },
+ { "946_PRBS7", 15,6,7, 0,0,CP_ANY, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c6_region[7]) },
REGINFO_SENTINEL
};
@@ -1520,39 +1391,28 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
static const ARMCPRegInfo vmsa_cp_reginfo[] = {
- { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
- .resetfn = arm_cp_reset_ignore, },
- { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
- { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = 0, },
- { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
- .writefn = vmsa_ttbr_write, .resetvalue = 0 },
- { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
- .writefn = vmsa_ttbr_write, .resetvalue = 0 },
- { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
- .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
- .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
- .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
- { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
- .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
- .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
+ { "DFSR", 15,5,0, 0,0,0, 0,
+ ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.esr_el[1]),
+ NULL,NULL,NULL,NULL,NULL, arm_cp_reset_ignore, },
+ { "IFSR", 15,5,0, 0,0,1, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.ifsr_el2), },
+ { "ESR_EL1", 0,5,2, 3,0,0, ARM_CP_STATE_AA64,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.esr_el[1]), },
+ { "TTBR0_EL1", 0,2,0, 3,0,0, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.ttbr0_el1),
+ NULL, NULL, vmsa_ttbr_write, },
+ { "TTBR1_EL1", 0,2,0, 3,0,1, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.ttbr1_el1),
+ NULL, NULL, vmsa_ttbr_write, },
+ { "TCR_EL1", 0,2,0, 3,0,2, ARM_CP_STATE_AA64,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c2_control),
+ NULL, NULL,vmsa_tcr_el1_write, NULL,raw_write, vmsa_ttbcr_reset, },
+ { "TTBCR", 15,2,0, 0,0,2, 0,
+ ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.c2_control),
+ NULL, NULL, vmsa_ttbcr_write, NULL, vmsa_ttbcr_raw_write, arm_cp_reset_ignore, },
/* 64-bit FAR; this entry also gives us the AArch32 DFAR */
- { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]),
- .resetvalue = 0, },
+ { "FAR_EL1", 0,6,0, 3,0,0, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.far_el[1]), },
REGINFO_SENTINEL
};
@@ -1589,42 +1449,33 @@ static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
static const ARMCPRegInfo omap_cp_reginfo[] = {
- { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
- .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
- .resetvalue = 0, },
- { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_NOP },
- { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
- .writefn = omap_ticonfig_write },
- { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
- { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .resetvalue = 0xff0,
- .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
- { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
- .writefn = omap_threadid_write },
- { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
- .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
- .type = ARM_CP_NO_MIGRATE,
- .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
+ { "DFSR", 15,5,CP_ANY, 0,CP_ANY,CP_ANY, 0,
+ ARM_CP_OVERRIDE, PL1_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.esr_el[1]), },
+ { "", 15,15,0, 0,0,0, 0,
+ ARM_CP_NOP, PL1_RW, NULL, 0, 0, },
+ { "TICONFIG", 15,15,1, 0,0,0, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c15_ticonfig),
+ NULL, NULL, omap_ticonfig_write },
+ { "IMAX", 15,15,2, 0,0,0, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c15_i_max), },
+ { "IMIN", 15,15,3, 0,0,0, 0,
+ 0, PL1_RW, NULL, 0xff0, offsetof(CPUARMState, cp15.c15_i_min) },
+ { "THREADID", 15,15,4, 0,0,0, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c15_threadid),
+ NULL, NULL, omap_threadid_write },
+ { "TI925T_STATUS", 15,15,8, 0,0,0, 0,
+ ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, 0,
+ NULL, arm_cp_read_zero, omap_wfi_write, },
/* TODO: Peripheral port remap register:
* On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
* base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
* when MMU is off.
*/
- { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
- .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
- .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
- .writefn = omap_cachemaint_write },
- { .name = "C9", .cp = 15, .crn = 9,
- .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
- .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
+ { "OMAP_CACHEMAINT", 15,7,CP_ANY, 0,0,CP_ANY, 0,
+ ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, omap_cachemaint_write },
+ { "C9", 15,9,CP_ANY, 0,CP_ANY,CP_ANY, 0,
+ ARM_CP_CONST | ARM_CP_OVERRIDE, PL1_RW, NULL, 0, 0, },
REGINFO_SENTINEL
};
@@ -1635,29 +1486,22 @@ static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
static const ARMCPRegInfo xscale_cp_reginfo[] = {
- { .name = "XSCALE_CPAR",
- .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
- .writefn = xscale_cpar_write, },
- { .name = "XSCALE_AUXCR",
- .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
- .resetvalue = 0, },
+ { "XSCALE_CPAR", 15,15,1, 0,0,0, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c15_cpar),
+ NULL, NULL, xscale_cpar_write, },
+ { "XSCALE_AUXCR", 15,1,0, 0,0,1, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c1_xscaleauxcr), },
/* XScale specific cache-lockdown: since we have no cache we NOP these
* and hope the guest does not really rely on cache behaviour.
*/
- { .name = "XSCALE_LOCK_ICACHE_LINE",
- .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
- .access = PL1_W, .type = ARM_CP_NOP },
- { .name = "XSCALE_UNLOCK_ICACHE",
- .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
- .access = PL1_W, .type = ARM_CP_NOP },
- { .name = "XSCALE_DCACHE_LOCK",
- .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_NOP },
- { .name = "XSCALE_UNLOCK_DCACHE",
- .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
- .access = PL1_W, .type = ARM_CP_NOP },
+ { "XSCALE_LOCK_ICACHE_LINE", 15,9,1, 0,0,0, 0,
+ ARM_CP_NOP, PL1_W },
+ { "XSCALE_UNLOCK_ICACHE", 15,9,1, 0,0,1, 0,
+ ARM_CP_NOP, PL1_W, },
+ { "XSCALE_DCACHE_LOCK", 15,9,2, 0,0,0, 0,
+ ARM_CP_NOP, PL1_RW },
+ { "XSCALE_UNLOCK_DCACHE", 15,9,2, 0,0,1, 0,
+ ARM_CP_NOP, PL1_W, },
REGINFO_SENTINEL
};
@@ -1667,40 +1511,35 @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
* Ideally this should eventually disappear in favour of actually
* implementing the correct behaviour for all cores.
*/
- { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
- .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
- .access = PL1_RW,
- .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
- .resetvalue = 0 },
+ { "C15_IMPDEF", 15,15,CP_ANY, 0,CP_ANY,CP_ANY, 0,
+ ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE, PL1_RW, NULL, 0 },
REGINFO_SENTINEL
};
static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
/* Cache status: RAZ because we have no cache so it's always clean */
- { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
- .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
- .resetvalue = 0 },
+ { "CDSR", 15,7,10, 0,0,6, 0,
+ ARM_CP_CONST | ARM_CP_NO_MIGRATE, PL1_R, NULL, 0 },
REGINFO_SENTINEL
};
static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
/* We never have a a block transfer operation in progress */
- { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
- .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
- .resetvalue = 0 },
+ { "BXSR", 15,7,12, 0,0,4, 0,
+ ARM_CP_CONST | ARM_CP_NO_MIGRATE, PL0_R, NULL, 0 },
/* The cache ops themselves: these all NOP for QEMU */
- { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
- { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
- { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
- { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
- { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
- .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
- { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
- .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
+ { "IICR", 15, 0,5, 0,0, 0, 0,
+ ARM_CP_NOP|ARM_CP_64BIT, PL1_W },
+ { "IDCR", 15, 0,6, 0,0, 0, 0,
+ ARM_CP_NOP|ARM_CP_64BIT, PL1_W, },
+ { "CDCR", 15, 0,12, 0,0, 0, 0,
+ ARM_CP_NOP|ARM_CP_64BIT, PL0_W, },
+ { "PIR", 15, 0,12, 0,1, 0, 0,
+ ARM_CP_NOP|ARM_CP_64BIT, PL0_W, },
+ { "PDR", 15, 0,12, 0,2, 0, 0,
+ ARM_CP_NOP|ARM_CP_64BIT, PL0_W, },
+ { "CIDCR", 15, 0,14, 0,0, 0, 0,
+ ARM_CP_NOP|ARM_CP_64BIT, PL1_W, },
REGINFO_SENTINEL
};
@@ -1708,21 +1547,17 @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
/* The cache test-and-clean instructions always return (1 << 30)
* to indicate that there are no dirty cache lines.
*/
- { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
- .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
- .resetvalue = (1 << 30) },
- { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
- .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
- .resetvalue = (1 << 30) },
+ { "TC_DCACHE", 15,7,10, 0,0,3, 0,
+ ARM_CP_CONST | ARM_CP_NO_MIGRATE, PL0_R, NULL, (1 << 30) },
+ { "TCI_DCACHE", 15,7,14, 0,0,3, 0,
+ ARM_CP_CONST | ARM_CP_NO_MIGRATE, PL0_R, NULL, (1 << 30) },
REGINFO_SENTINEL
};
static const ARMCPRegInfo strongarm_cp_reginfo[] = {
/* Ignore ReadBuffer accesses */
- { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
- .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
- .access = PL1_RW, .resetvalue = 0,
- .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
+ { "C9_READBUFFER", 15,9,CP_ANY, 0,CP_ANY,CP_ANY, 0,
+ ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, },
REGINFO_SENTINEL
};
@@ -1746,9 +1581,9 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
}
static const ARMCPRegInfo mpidr_cp_reginfo[] = {
- { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
- .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
+ { "MPIDR", 0,0,0, 3,0,5, ARM_CP_STATE_BOTH,
+ ARM_CP_NO_MIGRATE, PL1_R, NULL, 0, 0,
+ NULL, mpidr_read, },
REGINFO_SENTINEL
};
@@ -1756,25 +1591,19 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = {
/* NOP AMAIR0/1: the override is because these clash with the rather
* broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
*/
- { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
- .resetvalue = 0 },
+ { "AMAIR0", 0,10,3, 3,0,0, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST | ARM_CP_OVERRIDE, PL1_RW, NULL, 0 },
/* AMAIR1 is mapped to AMAIR_EL1[63:32] */
- { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
- .resetvalue = 0 },
- { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
- .access = PL1_RW, .type = ARM_CP_64BIT,
- .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 },
- { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
- .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
- .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
- { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
- .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
- .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
+ { "AMAIR1", 15,10,3, 0,0,1, 0,
+ ARM_CP_CONST | ARM_CP_OVERRIDE, PL1_RW, NULL, 0 },
+ { "PAR", 15, 0,7, 0,0, 0, 0,
+ ARM_CP_64BIT, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.par_el1), },
+ { "TTBR0", 15, 0,2, 0,0, 0, 0,
+ ARM_CP_64BIT | ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.ttbr0_el1),
+ NULL, NULL, vmsa_ttbr_write, NULL,NULL, arm_cp_reset_ignore },
+ { "TTBR1", 15, 0,2, 0,1, 0, 0,
+ ARM_CP_64BIT | ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.ttbr1_el1),
+ NULL, NULL, vmsa_ttbr_write, NULL,NULL, arm_cp_reset_ignore },
REGINFO_SENTINEL
};
@@ -1934,213 +1763,175 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
/* Minimal set of EL0-visible registers. This will need to be expanded
* significantly for system emulation of AArch64 CPUs.
*/
- { .name = "NZCV", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
- .access = PL0_RW, .type = ARM_CP_NZCV },
- { .name = "DAIF", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
- .type = ARM_CP_NO_MIGRATE,
- .access = PL0_RW, .accessfn = aa64_daif_access,
- .fieldoffset = offsetof(CPUARMState, daif),
- .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
- { .name = "FPCR", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
- .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
- { .name = "FPSR", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
- .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
- { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
- .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
- .readfn = aa64_dczid_read },
- { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
- .access = PL0_W, .type = ARM_CP_DC_ZVA,
+ { "NZCV", 0,4,2, 3,3,0, ARM_CP_STATE_AA64,
+ ARM_CP_NZCV, PL0_RW, },
+ { "DAIF", 0,4,2, 3,3,1, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL0_RW, NULL, 0, offsetof(CPUARMState, daif),
+ aa64_daif_access, NULL, aa64_daif_write, NULL,NULL, arm_cp_reset_ignore },
+ { "FPCR", 0,4,4, 3,3,0, ARM_CP_STATE_AA64,
+ 0, PL0_RW, NULL, 0, 0,
+ NULL, aa64_fpcr_read, aa64_fpcr_write },
+ { "FPSR", 0,4,4, 3,3,1, ARM_CP_STATE_AA64,
+ 0, PL0_RW, NULL, 0, 0,
+ NULL, aa64_fpsr_read, aa64_fpsr_write },
+ { "DCZID_EL0", 0,0,0, 3,3,7, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL0_R, NULL, 0, 0,
+ NULL, aa64_dczid_read },
+ { "DC_ZVA", 0,7,4, 1,3,1, ARM_CP_STATE_AA64,
+ ARM_CP_DC_ZVA, PL0_W, NULL, 0, 0,
#ifndef CONFIG_USER_ONLY
/* Avoid overhead of an access check that always passes in user-mode */
- .accessfn = aa64_zva_access,
+ aa64_zva_access,
#endif
},
- { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
- .access = PL1_R, .type = ARM_CP_CURRENTEL },
+ { "CURRENTEL", 0,4,2, 3,0,2, ARM_CP_STATE_AA64,
+ ARM_CP_CURRENTEL, PL1_R, },
/* Cache ops: all NOPs since we don't emulate caches */
- { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
- .access = PL1_W, .type = ARM_CP_NOP },
- { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
- .access = PL1_W, .type = ARM_CP_NOP },
- { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
- .access = PL0_W, .type = ARM_CP_NOP,
- .accessfn = aa64_cacheop_access },
- { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
- .access = PL1_W, .type = ARM_CP_NOP },
- { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
- .access = PL1_W, .type = ARM_CP_NOP },
- { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
- .access = PL0_W, .type = ARM_CP_NOP,
- .accessfn = aa64_cacheop_access },
- { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
- .access = PL1_W, .type = ARM_CP_NOP },
- { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
- .access = PL0_W, .type = ARM_CP_NOP,
- .accessfn = aa64_cacheop_access },
- { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
- .access = PL0_W, .type = ARM_CP_NOP,
- .accessfn = aa64_cacheop_access },
- { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
- .access = PL1_W, .type = ARM_CP_NOP },
+ { "IC_IALLUIS", 0,7,1, 1,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_NOP, PL1_W, },
+ { "IC_IALLU", 0,7,5, 1,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_NOP, PL1_W, },
+ { "IC_IVAU", 0,7,5, 1,3,1, ARM_CP_STATE_AA64,
+ ARM_CP_NOP, PL0_W, NULL, 0, 0,
+ aa64_cacheop_access },
+ { "DC_IVAC", 0,7,6, 1,0,1, ARM_CP_STATE_AA64,
+ ARM_CP_NOP, PL1_W, },
+ { "DC_ISW", 0,7,6, 1,0,2, ARM_CP_STATE_AA64,
+ ARM_CP_NOP, PL1_W, },
+ { "DC_CVAC", 0,7,10, 1,3,1, ARM_CP_STATE_AA64,
+ ARM_CP_NOP, PL0_W, NULL, 0, 0,
+ aa64_cacheop_access },
+ { "DC_CSW", 0,7,10, 1,0,2, ARM_CP_STATE_AA64,
+ ARM_CP_NOP, PL1_W, },
+ { "DC_CVAU", 0,7,11, 1,3,1, ARM_CP_STATE_AA64,
+ ARM_CP_NOP, PL0_W, NULL, 0, 0,
+ aa64_cacheop_access },
+ { "DC_CIVAC", 0,7,14, 1,3,1, ARM_CP_STATE_AA64,
+ ARM_CP_NOP, PL0_W, NULL, 0, 0,
+ aa64_cacheop_access },
+ { "DC_CISW", 0,7,14, 1,0,2, ARM_CP_STATE_AA64,
+ ARM_CP_NOP, PL1_W, },
/* TLBI operations */
- { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
- .writefn = tlbiall_is_write },
- { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
- .writefn = tlbi_aa64_va_is_write },
- { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
- .writefn = tlbi_aa64_asid_is_write },
- { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
- .writefn = tlbi_aa64_vaa_is_write },
- { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
- .writefn = tlbi_aa64_va_is_write },
- { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
- .writefn = tlbi_aa64_vaa_is_write },
- { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
- .writefn = tlbiall_write },
- { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
- .writefn = tlbi_aa64_va_write },
- { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
- .writefn = tlbi_aa64_asid_write },
- { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
- .writefn = tlbi_aa64_vaa_write },
- { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
- .writefn = tlbi_aa64_va_write },
- { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
- .writefn = tlbi_aa64_vaa_write },
+ { "TLBI_VMALLE1IS", 0,8,3, 1,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbiall_is_write },
+ { "TLBI_VAE1IS", 0,8,3, 1,0,1, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbi_aa64_va_is_write },
+ { "TLBI_ASIDE1IS", 0,8,3, 1,0,2, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbi_aa64_asid_is_write },
+ { "TLBI_VAAE1IS", 0,8,3, 1,0,3, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbi_aa64_vaa_is_write },
+ { "TLBI_VALE1IS", 0,8,3, 1,0,5, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbi_aa64_va_is_write },
+ { "TLBI_VAALE1IS", 0,8,3, 1,0,7, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbi_aa64_vaa_is_write },
+ { "TLBI_VMALLE1", 0,8,7, 1,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbiall_write },
+ { "TLBI_VAE1", 0,8,7, 1,0,1, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbi_aa64_va_write },
+ { "TLBI_ASIDE1", 0,8,7, 1,0,2, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbi_aa64_asid_write },
+ { "TLBI_VAAE1", 0,8,7, 1,0,3, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbi_aa64_vaa_write },
+ { "TLBI_VALE1", 0,8,7, 1,0,5, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbi_aa64_va_write },
+ { "TLBI_VAALE1", 0,8,7, 1,0,7, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbi_aa64_vaa_write },
#ifndef CONFIG_USER_ONLY
/* 64 bit address translation operations */
- { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
- { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
- { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
- { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
- .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
- .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
+ { "AT_S1E1R", 0,7,8, 1,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, ats_write },
+ { "AT_S1E1W", 0,7,8, 1,0,1, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, ats_write },
+ { "AT_S1E0R", 0,7,8, 1,0,2, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, ats_write },
+ { "AT_S1E0W", 0,7,8, 1,0,3, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, ats_write },
#endif
/* TLB invalidate last level of translation table walk */
- { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_is_write },
- { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W,
- .writefn = tlbimvaa_is_write },
- { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
- { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
- .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
+ { "TLBIMVALIS", 15,8,3, 0,0,5, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbimva_is_write },
+ { "TLBIMVAALIS", 15,8,3, 0,0,7, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbimvaa_is_write },
+ { "TLBIMVAL", 15,8,7, 0,0,5, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbimva_write },
+ { "TLBIMVAAL", 15,8,7, 0,0,7, 0,
+ ARM_CP_NO_MIGRATE, PL1_W, NULL, 0, 0,
+ NULL, NULL, tlbimvaa_write },
/* 32 bit cache operations */
- { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
- .type = ARM_CP_NOP, .access = PL1_W },
- { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
- .type = ARM_CP_NOP, .access = PL1_W },
- { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
- .type = ARM_CP_NOP, .access = PL1_W },
- { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
- .type = ARM_CP_NOP, .access = PL1_W },
- { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
- .type = ARM_CP_NOP, .access = PL1_W },
- { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
- .type = ARM_CP_NOP, .access = PL1_W },
- { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
- .type = ARM_CP_NOP, .access = PL1_W },
- { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
- .type = ARM_CP_NOP, .access = PL1_W },
- { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
- .type = ARM_CP_NOP, .access = PL1_W },
- { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
- .type = ARM_CP_NOP, .access = PL1_W },
- { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
- .type = ARM_CP_NOP, .access = PL1_W },
- { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
- .type = ARM_CP_NOP, .access = PL1_W },
- { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
- .type = ARM_CP_NOP, .access = PL1_W },
+ { "ICIALLUIS", 15,7,1, 0,0,0, 0,
+ ARM_CP_NOP, PL1_W },
+ { "BPIALLUIS", 15,7,1, 0,0,6, 0,
+ ARM_CP_NOP, PL1_W },
+ { "ICIALLU", 15,7,5, 0,0,0, 0,
+ ARM_CP_NOP, PL1_W },
+ { "ICIMVAU", 15,7,5,0,1, 0,
+ ARM_CP_NOP, PL1_W },
+ { "BPIALL", 15,7,5, 0,0,6, 0,
+ ARM_CP_NOP, PL1_W },
+ { "BPIMVA", 15,7,5, 0,0,7, 0,
+ ARM_CP_NOP, PL1_W },
+ { "DCIMVAC", 15,7,6, 0,0,1, 0,
+ ARM_CP_NOP, PL1_W },
+ { "DCISW", 15,7,6, 0,0,2, 0,
+ ARM_CP_NOP, PL1_W },
+ { "DCCMVAC", 15,7,10, 0,0,1, 0,
+ ARM_CP_NOP, PL1_W },
+ { "DCCSW", 15,7,10, 0,0,2, 0,
+ ARM_CP_NOP, PL1_W },
+ { "DCCMVAU", 15,7,11, 0,0,1, 0,
+ ARM_CP_NOP, PL1_W },
+ { "DCCIMVAC", 15,7,14, 0,0,1, 0,
+ ARM_CP_NOP, PL1_W },
+ { "DCCISW", 15,7,14, 0,0,2, 0,
+ ARM_CP_NOP, PL1_W },
/* MMU Domain access control / MPU write buffer control */
- { .name = "DACR", .cp = 15,
- .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
- .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
- { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_NO_MIGRATE,
- .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, elr_el[1]) },
- { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_NO_MIGRATE,
- .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
+ { "DACR", 15,3,0, 0,0,0, 0,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c3),
+ NULL, NULL,dacr_write, NULL,raw_write, },
+ { "ELR_EL1", 0,4,0, 3,0,1, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, offsetof(CPUARMState, elr_el[1]) },
+ { "SPSR_EL1", 0,4,0, 3,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, offsetof(CPUARMState, banked_spsr[0]) },
/* We rely on the access checks not allowing the guest to write to the
* state field when SPSel indicates that it's being used as the stack
* pointer.
*/
- { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
- .access = PL1_RW, .accessfn = sp_el0_access,
- .type = ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
- { .name = "SPSel", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
- .type = ARM_CP_NO_MIGRATE,
- .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
+ { "SP_EL0", 0,4,1, 3,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, offsetof(CPUARMState, sp_el[0]),
+ sp_el0_access, },
+ { "SPSel", 0,4,2, 3,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL1_RW, NULL, 0, 0,
+ NULL, spsel_read, spsel_write },
REGINFO_SENTINEL
};
/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
static const ARMCPRegInfo v8_el3_no_el2_cp_reginfo[] = {
- { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
- .access = PL2_RW,
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
- { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_NO_MIGRATE,
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
- .access = PL2_RW,
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore },
+ { "VBAR_EL2", 0,12,0, 3,4,0, ARM_CP_STATE_AA64,
+ 0, PL2_RW, NULL, 0, 0,
+ NULL, arm_cp_read_zero, arm_cp_write_ignore },
+ { "HCR_EL2", 0,1,1, 3,4,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL2_RW, NULL, 0, 0,
+ NULL, arm_cp_read_zero, arm_cp_write_ignore },
REGINFO_SENTINEL
};
@@ -2170,61 +1961,38 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
}
static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
- { .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0,
- .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2),
- .writefn = hcr_write },
- { .name = "ELR_EL2", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_NO_MIGRATE,
- .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 1,
- .access = PL2_RW,
- .fieldoffset = offsetof(CPUARMState, elr_el[2]) },
- { .name = "ESR_EL2", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_NO_MIGRATE,
- .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
- .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
- { .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
- .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
- { .name = "SPSR_EL2", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_NO_MIGRATE,
- .opc0 = 3, .opc1 = 4, .crn = 4, .crm = 0, .opc2 = 0,
- .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[6]) },
- { .name = "VBAR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 0,
- .access = PL2_RW, .writefn = vbar_write,
- .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[2]),
- .resetvalue = 0 },
+ { "HCR_EL2", 0,1,1, 3,4,0, ARM_CP_STATE_AA64,
+ 0, PL2_RW, NULL, 0, offsetof(CPUARMState, cp15.hcr_el2),
+ NULL, NULL, hcr_write },
+ { "ELR_EL2", 0,4,0, 3,4,1, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL2_RW, NULL, 0, offsetof(CPUARMState, elr_el[2]) },
+ { "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL2_RW, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) },
+ { "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_AA64,
+ 0, PL2_RW, NULL, 0, offsetof(CPUARMState, cp15.far_el[2]) },
+ { "SPSR_EL2", 0,4,0, 3,4,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL2_RW, NULL, 0, offsetof(CPUARMState, banked_spsr[6]) },
+ { "VBAR_EL2", 0,12,0, 3,4,0, ARM_CP_STATE_AA64,
+ 0, PL2_RW, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[2]),
+ NULL, NULL, vbar_write, },
REGINFO_SENTINEL
};
static const ARMCPRegInfo v8_el3_cp_reginfo[] = {
- { .name = "ELR_EL3", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_NO_MIGRATE,
- .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 1,
- .access = PL3_RW,
- .fieldoffset = offsetof(CPUARMState, elr_el[3]) },
- { .name = "ESR_EL3", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_NO_MIGRATE,
- .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 2, .opc2 = 0,
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[3]) },
- { .name = "FAR_EL3", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 6, .crn = 6, .crm = 0, .opc2 = 0,
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[3]) },
- { .name = "SPSR_EL3", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_NO_MIGRATE,
- .opc0 = 3, .opc1 = 6, .crn = 4, .crm = 0, .opc2 = 0,
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[7]) },
- { .name = "VBAR_EL3", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 0,
- .access = PL3_RW, .writefn = vbar_write,
- .fieldoffset = offsetof(CPUARMState, cp15.vbar_el[3]),
- .resetvalue = 0 },
- { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_NO_MIGRATE,
- .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0,
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3),
- .writefn = scr_write },
+ { "ELR_EL3", 0,4,0, 3,6,1, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL3_RW, NULL, 0, offsetof(CPUARMState, elr_el[3]) },
+ { "ESR_EL3", 0,5,2, 3,6,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL3_RW, NULL, 0, offsetof(CPUARMState, cp15.esr_el[3]) },
+ { "FAR_EL3", 0,6,0, 3,6,0, ARM_CP_STATE_AA64,
+ 0, PL3_RW, NULL, 0, offsetof(CPUARMState, cp15.far_el[3]) },
+ { "SPSR_EL3", 0,4,0, 3,6,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL3_RW, NULL, 0, offsetof(CPUARMState, banked_spsr[7]) },
+ { "VBAR_EL3", 0,12,0, 3,6,0, ARM_CP_STATE_AA64,
+ 0, PL3_RW, NULL, 0, offsetof(CPUARMState, cp15.vbar_el[3]),
+ NULL, NULL, vbar_write, },
+ { "SCR_EL3", 0,1,1, 3,6,0, ARM_CP_STATE_AA64,
+ ARM_CP_NO_MIGRATE, PL3_RW, NULL, 0, offsetof(CPUARMState, cp15.scr_el3),
+ NULL, NULL, scr_write },
REGINFO_SENTINEL
};
@@ -2264,51 +2032,41 @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
* DBGDSAR is deprecated and must RAZ from v8 anyway, so it has no AArch64
* accessor.
*/
- { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "MDRAR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { "DBGDRAR", 14,1,0, 0,0,0, 0,
+ ARM_CP_CONST, PL0_R, NULL, 0 },
+ { "MDRAR_EL1", 0,1,0, 2,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, 0 },
+ { "DBGDSAR", 14,2,0, 0,0,0, 0,
+ ARM_CP_CONST, PL0_R, NULL, 0 },
/* Monitor debug system control register; the 32-bit alias is DBGDSCRext. */
- { .name = "MDSCR_EL1", .state = ARM_CP_STATE_BOTH,
- .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
- .resetvalue = 0 },
+ { "MDSCR_EL1", 14,0,2, 2,0,2, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.mdscr_el1), },
/* MDCCSR_EL0, aka DBGDSCRint. This is a read-only mirror of MDSCR_EL1.
* We don't implement the configurable EL0 access.
*/
- { .name = "MDCCSR_EL0", .state = ARM_CP_STATE_BOTH,
- .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
- .type = ARM_CP_NO_MIGRATE,
- .access = PL1_R,
- .fieldoffset = offsetof(CPUARMState, cp15.mdscr_el1),
- .resetfn = arm_cp_reset_ignore },
+ { "MDCCSR_EL0", 14,0,1, 2,0,0, ARM_CP_STATE_BOTH,
+ ARM_CP_NO_MIGRATE, PL1_R, NULL, 0, offsetof(CPUARMState, cp15.mdscr_el1),
+ NULL,NULL,NULL,NULL,NULL, arm_cp_reset_ignore },
/* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
- { .name = "OSLAR_EL1", .state = ARM_CP_STATE_BOTH,
- .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
- .access = PL1_W, .type = ARM_CP_NOP },
+ { "OSLAR_EL1", 14,1,0, 2,0,4, ARM_CP_STATE_BOTH,
+ ARM_CP_NOP, PL1_W, },
/* Dummy OSDLR_EL1: 32-bit Linux will read this */
- { .name = "OSDLR_EL1", .state = ARM_CP_STATE_BOTH,
- .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 4,
- .access = PL1_RW, .type = ARM_CP_NOP },
+ { "OSDLR_EL1", 14,1,3, 2,0,4, ARM_CP_STATE_BOTH,
+ ARM_CP_NOP, PL1_RW, },
/* Dummy DBGVCR: Linux wants to clear this on startup, but we don't
* implement vector catch debug events yet.
*/
- { .name = "DBGVCR",
- .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_NOP },
+ { "DBGVCR", 14,0,7, 0,0,0, 0,
+ ARM_CP_NOP, PL1_RW, },
REGINFO_SENTINEL
};
static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
/* 64 bit access versions of the (dummy) debug registers */
- { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
- .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
- { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
- .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
+ { "DBGDRAR", 14, 0,1, 0,0, 0, 0,
+ ARM_CP_CONST|ARM_CP_64BIT, PL0_R, NULL, 0 },
+ { "DBGDSAR", 14, 0,2, 0,0, 0, 0,
+ ARM_CP_CONST|ARM_CP_64BIT, PL0_R, NULL, 0 },
REGINFO_SENTINEL
};
@@ -2563,8 +2321,8 @@ static void define_debug_regs(ARMCPU *cpu)
int i;
int wrps, brps, ctx_cmps;
ARMCPRegInfo dbgdidr = {
- .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = cpu->dbgdidr,
+ "DBGDIDR", 14,0,0, 0,0,0, 0,
+ ARM_CP_CONST, PL0_R, NULL, cpu->dbgdidr,
};
/* Note that all these register fields hold "number of Xs minus 1". */
@@ -2593,17 +2351,13 @@ static void define_debug_regs(ARMCPU *cpu)
for (i = 0; i < brps + 1; i++) {
ARMCPRegInfo dbgregs[] = {
- { .name = "DBGBVR", .state = ARM_CP_STATE_BOTH,
- .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]),
- .writefn = dbgbvr_write, .raw_writefn = raw_write
+ { "DBGBVR", 14,0,i, 2,0,4,ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.dbgbvr[i]),
+ NULL, NULL,dbgbvr_write, NULL,raw_write
},
- { .name = "DBGBCR", .state = ARM_CP_STATE_BOTH,
- .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]),
- .writefn = dbgbcr_write, .raw_writefn = raw_write
+ { "DBGBCR", 14,0,i, 2,0,5, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.dbgbcr[i]),
+ NULL, NULL,dbgbcr_write, NULL,raw_write
},
REGINFO_SENTINEL
};
@@ -2612,17 +2366,13 @@ static void define_debug_regs(ARMCPU *cpu)
for (i = 0; i < wrps + 1; i++) {
ARMCPRegInfo dbgregs[] = {
- { .name = "DBGWVR", .state = ARM_CP_STATE_BOTH,
- .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]),
- .writefn = dbgwvr_write, .raw_writefn = raw_write
+ { "DBGWVR", 14,0,i, 2,0,6, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.dbgwvr[i]),
+ NULL, NULL,dbgwvr_write, NULL,raw_write
},
- { .name = "DBGWCR", .state = ARM_CP_STATE_BOTH,
- .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
- .access = PL1_RW,
- .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]),
- .writefn = dbgwcr_write, .raw_writefn = raw_write
+ { "DBGWCR", 14,0,i, 2,0,7, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.dbgwcr[i]),
+ NULL, NULL,dbgwcr_write, NULL,raw_write
},
REGINFO_SENTINEL
};
@@ -2650,69 +2400,39 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_V6)) {
/* The ID registers all have impdef reset values */
ARMCPRegInfo v6_idregs[] = {
- { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_pfr0 },
- { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_pfr1 },
- { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_dfr0 },
- { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_afr0 },
- { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_mmfr0 },
- { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_mmfr1 },
- { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_mmfr2 },
- { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_mmfr3 },
- { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_isar0 },
- { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_isar1 },
- { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_isar2 },
- { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_isar3 },
- { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_isar4 },
- { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_isar5 },
+ { "ID_PFR0", 0,0,1, 3,0,0, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_pfr0 },
+ { "ID_PFR1", 0,0,1, 3,0,1, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_pfr1 },
+ { "ID_DFR0", 0,0,1, 3,0,2, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_dfr0 },
+ { "ID_AFR0", 0,0,1, 3,0,3, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_afr0 },
+ { "ID_MMFR0", 0,0,1, 3,0,4, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_mmfr0 },
+ { "ID_MMFR1", 0,0,1, 3,0,5, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_mmfr1 },
+ { "ID_MMFR2", 0,0,1, 3,0,6, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_mmfr2 },
+ { "ID_MMFR3", 0,0,1, 3,0,7, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_mmfr3 },
+ { "ID_ISAR0", 0,0,2, 3,0,0, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_isar0 },
+ { "ID_ISAR1", 0,0,2, 3,0,1, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_isar1 },
+ { "ID_ISAR2", 0,0,2, 3,0,2, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_isar2 },
+ { "ID_ISAR3", 0,0,2, 3,0,3, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_isar3 },
+ { "ID_ISAR4", 0,0,2, 3,0,4, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_isar4 },
+ { "ID_ISAR5", 0,0,2, 3,0,5, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_isar5 },
/* 6..7 are as yet unallocated and must RAZ */
- { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
- .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = 0 },
- { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
- .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = 0 },
+ { "ID_ISAR6", 15,0,2, 0,0,6, 0,
+ ARM_CP_CONST, PL1_R, NULL, 0 },
+ { "ID_ISAR7", 15,0,2, 0,0,7, 0,
+ ARM_CP_CONST, PL1_R, NULL, 0 },
REGINFO_SENTINEL
};
define_arm_cp_regs(cpu, v6_idregs);
@@ -2727,36 +2447,28 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, v7mp_cp_reginfo);
}
if (arm_feature(env, ARM_FEATURE_V7)) {
+ ARMCPRegInfo clidr = {
+ "CLIDR", 0,0,0, 3,1,1, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->clidr
+ };
/* v7 performance monitor control register: same implementor
* field as main ID register, and we implement only the cycle
* count register.
*/
#ifndef CONFIG_USER_ONLY
ARMCPRegInfo pmcr = {
- .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
- .access = PL0_RW,
- .type = ARM_CP_IO | ARM_CP_NO_MIGRATE,
- .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcr),
- .accessfn = pmreg_access, .writefn = pmcr_write,
- .raw_writefn = raw_write,
+ "PMCR", 15,9,12, 0,0,0, 0,
+ ARM_CP_IO | ARM_CP_NO_MIGRATE, PL0_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.c9_pmcr),
+ pmreg_access, NULL,pmcr_write, NULL,raw_write,
};
ARMCPRegInfo pmcr64 = {
- .name = "PMCR_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 0,
- .access = PL0_RW, .accessfn = pmreg_access,
- .type = ARM_CP_IO,
- .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
- .resetvalue = cpu->midr & 0xff000000,
- .writefn = pmcr_write, .raw_writefn = raw_write,
+ "PMCR_EL0", 0,9,12, 3,3,0, ARM_CP_STATE_AA64,
+ ARM_CP_IO, PL0_RW, NULL, cpu->midr & 0xff000000, offsetof(CPUARMState, cp15.c9_pmcr),
+ pmreg_access, NULL,pmcr_write, NULL,raw_write,
};
define_one_arm_cp_reg(cpu, &pmcr);
define_one_arm_cp_reg(cpu, &pmcr64);
#endif
- ARMCPRegInfo clidr = {
- .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
- };
define_one_arm_cp_reg(cpu, &clidr);
define_arm_cp_regs(cpu, v7_cp_reginfo);
define_debug_regs(cpu);
@@ -2766,69 +2478,43 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_V8)) {
/* AArch64 ID registers, which all have impdef reset values */
ARMCPRegInfo v8_idregs[] = {
- { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_aa64pfr0 },
- { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_aa64pfr1},
- { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_CONST,
+ { "ID_AA64PFR0_EL1", 0,0,4, 3,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_aa64pfr0 },
+ { "ID_AA64PFR1_EL1", 0,0,4, 3,0,1, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_aa64pfr1},
+ { "ID_AA64DFR0_EL1", 0,0,5, 3,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL,
/* We mask out the PMUVer field, because we don't currently
* implement the PMU. Not advertising it prevents the guest
* from trying to use it and getting UNDEFs on registers we
* don't implement.
*/
- .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
- { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_aa64dfr1 },
- { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_aa64afr0 },
- { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_aa64afr1 },
- { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_aa64isar0 },
- { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_aa64isar1 },
- { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_aa64mmfr0 },
- { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->id_aa64mmfr1 },
- { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->mvfr0 },
- { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->mvfr1 },
- { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
- .access = PL1_R, .type = ARM_CP_CONST,
- .resetvalue = cpu->mvfr2 },
+ cpu->id_aa64dfr0 & ~0xf00 },
+ { "ID_AA64DFR1_EL1", 0,0,5, 3,0,1, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_aa64dfr1 },
+ { "ID_AA64AFR0_EL1", 0,0,5, 3,0,4, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_aa64afr0 },
+ { "ID_AA64AFR1_EL1", 0,0,5, 3,0,5, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_aa64afr1 },
+ { "ID_AA64ISAR0_EL1", 0,0,6, 3,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_aa64isar0 },
+ { "ID_AA64ISAR1_EL1", 0,0,6, 3,0,1, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_aa64isar1 },
+ { "ID_AA64MMFR0_EL1", 0,0,7, 3,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_aa64mmfr0 },
+ { "ID_AA64MMFR1_EL1", 0,0,7, 3,0,1, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->id_aa64mmfr1 },
+ { "MVFR0_EL1", 0,0,3, 3,0,0, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->mvfr0 },
+ { "MVFR1_EL1", 0,0,3, 3,0,1, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->mvfr1 },
+ { "MVFR2_EL1", 0,0,3, 3,0,2, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->mvfr2 },
REGINFO_SENTINEL
};
ARMCPRegInfo rvbar = {
- .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
- .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
+ "RVBAR_EL1", 0,12,0, 3,0,2, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cpu->rvbar
};
define_one_arm_cp_reg(cpu, &rvbar);
define_arm_cp_regs(cpu, v8_idregs);
@@ -2906,28 +2592,25 @@ void register_cp_regs_for_features(ARMCPU *cpu)
* MIDR. Define MIDR first as this entire space, then CTR, TCMTR
* and friends override accordingly.
*/
- { .name = "MIDR",
- .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
- .access = PL1_R, .resetvalue = cpu->midr,
- .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
- .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
- .type = ARM_CP_OVERRIDE },
+ { "MIDR", 15,0,0, 0,0,CP_ANY, 0,
+ ARM_CP_OVERRIDE, PL1_R, NULL, cpu->midr, offsetof(CPUARMState, cp15.c0_cpuid),
+ NULL, NULL,arm_cp_write_ignore, NULL,raw_write, },
/* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
- { .name = "DUMMY",
- .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "DUMMY",
- .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "DUMMY",
- .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "DUMMY",
- .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "DUMMY",
- .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { "DUMMY",
+ 15,0,3, 0,0,CP_ANY, 0,
+ ARM_CP_CONST, PL1_R, NULL, 0 },
+ { "DUMMY",
+ 15,0,4, 0,0,CP_ANY, 0,
+ ARM_CP_CONST, PL1_R, NULL, 0 },
+ { "DUMMY",
+ 15,0,5, 0,0,CP_ANY, 0,
+ ARM_CP_CONST, PL1_R, NULL, 0 },
+ { "DUMMY",
+ 15,0,6, 0,0,CP_ANY, 0,
+ ARM_CP_CONST, PL1_R, NULL, 0 },
+ { "DUMMY",
+ 15,0,7, 0,0,CP_ANY, 0,
+ ARM_CP_CONST, PL1_R, NULL, 0 },
REGINFO_SENTINEL
};
ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
@@ -2935,36 +2618,29 @@ void register_cp_regs_for_features(ARMCPU *cpu)
* variable-MIDR TI925 behaviour. Instead we have a single
* (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
*/
- { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
- { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
+ { "MIDR_EL1", 0,0,0, 3,0,0, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->midr },
+ { "REVIDR_EL1", 0,0,0, 3,0,6, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_R, NULL, cpu->midr },
REGINFO_SENTINEL
};
ARMCPRegInfo id_cp_reginfo[] = {
/* These are common to v8 and pre-v8 */
- { .name = "CTR",
- .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
- { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
- .access = PL0_R, .accessfn = ctr_el0_access,
- .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
+ { "CTR", 15,0,0, 0,0,1, 0,
+ ARM_CP_CONST, PL1_R, NULL, cpu->ctr },
+ { "CTR_EL0", 0,0,0, 3,3,1, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL0_R, NULL, cpu->ctr, 0,
+ ctr_el0_access, },
/* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
- { .name = "TCMTR",
- .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
- { .name = "TLBTR",
- .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
- .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { "TCMTR", 15,0,0, 0,0,2, 0,
+ ARM_CP_CONST, PL1_R, NULL, 0 },
+ { "TLBTR", 15,0,0, 0,0,3, 0,
+ ARM_CP_CONST, PL1_R, NULL, 0 },
REGINFO_SENTINEL
};
ARMCPRegInfo crn0_wi_reginfo = {
- .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
- .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
- .type = ARM_CP_NOP | ARM_CP_OVERRIDE
+ "CRN0_WI", 15,0,CP_ANY, 0,CP_ANY,CP_ANY, 0,
+ ARM_CP_NOP | ARM_CP_OVERRIDE, PL1_W,
};
if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
arm_feature(env, ARM_FEATURE_STRONGARM)) {
@@ -2997,10 +2673,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
if (arm_feature(env, ARM_FEATURE_AUXCR)) {
ARMCPRegInfo auxcr = {
- .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
- .access = PL1_RW, .type = ARM_CP_CONST,
- .resetvalue = cpu->reset_auxcr
+ "ACTLR_EL1", 0,1,0, 3,0,1, ARM_CP_STATE_BOTH,
+ ARM_CP_CONST, PL1_RW, NULL, cpu->reset_auxcr
};
define_one_arm_cp_reg(cpu, &auxcr);
}
@@ -3011,14 +2685,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
| extract64(cpu->reset_cbar, 32, 12);
ARMCPRegInfo cbar_reginfo[] = {
- { .name = "CBAR",
- .type = ARM_CP_CONST,
- .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
- .access = PL1_R, .resetvalue = cpu->reset_cbar },
- { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
- .type = ARM_CP_CONST,
- .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
- .access = PL1_R, .resetvalue = cbar32 },
+ { "CBAR", 15,15,0, 0,4,0, 0,
+ ARM_CP_CONST, PL1_R, NULL, cpu->reset_cbar },
+ { "CBAR_EL1", 0,15,3, 3,1,0, ARM_CP_STATE_AA64,
+ ARM_CP_CONST, PL1_R, NULL, cbar32 },
REGINFO_SENTINEL
};
/* We don't implement a r/w 64 bit CBAR currently */
@@ -3026,11 +2696,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, cbar_reginfo);
} else {
ARMCPRegInfo cbar = {
- .name = "CBAR",
- .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
- .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
- .fieldoffset = offsetof(CPUARMState,
- cp15.c15_config_base_address)
+ "CBAR", 15,15,0, 0,4,0, 0,
+ 0, PL1_R|PL3_W, NULL, cpu->reset_cbar, offsetof(CPUARMState, cp15.c15_config_base_address)
};
if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
cbar.access = PL1_R;
@@ -3044,11 +2711,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
/* Generic registers whose values depend on the implementation */
{
ARMCPRegInfo sctlr = {
- .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
- .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
- .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
- .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
- .raw_writefn = raw_write,
+ "SCTLR", 0,1,0, 3,0,0, ARM_CP_STATE_BOTH,
+ 0, PL1_RW, NULL, cpu->reset_sctlr, offsetof(CPUARMState, cp15.c1_sys),
+ NULL, NULL,sctlr_write, NULL,raw_write,
};
if (arm_feature(env, ARM_FEATURE_XSCALE)) {
/* Normally we would always end the TB on an SCTLR write, but Linux
@@ -4312,6 +3977,8 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
int32_t granule_sz = 9;
int32_t va_size = 32;
int32_t tbi = 0;
+ uint32_t t0sz;
+ uint32_t t1sz;
if (arm_el_is_aa64(env, 1)) {
va_size = 64;
@@ -4327,12 +3994,12 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
* This is a Non-secure PL0/1 stage 1 translation, so controlled by
* TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
*/
- uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6);
+ t0sz = extract32(env->cp15.c2_control, 0, 6);
if (arm_el_is_aa64(env, 1)) {
t0sz = MIN(t0sz, 39);
t0sz = MAX(t0sz, 16);
}
- uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6);
+ t1sz = extract32(env->cp15.c2_control, 16, 6);
if (arm_el_is_aa64(env, 1)) {
t1sz = MIN(t1sz, 39);
t1sz = MAX(t1sz, 16);
@@ -4836,8 +4503,19 @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
* 1K as an artefact of legacy v5 subpage support being present in the
* same QEMU executable.
*/
+
int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
+ // msvc doesnt allow non-constant array sizes, so we work out the size it would be
+ // TARGET_PAGE_SIZE is 1024
+ // blocklen is 64
+ // maxidx = (blocklen+TARGET_PAGE_SIZE-1) / TARGET_PAGE_SIZE
+ // = (64+1024-1) / 1024
+ // = 1
+#ifdef _MSC_VER
+ void *hostaddr[1];
+#else
void *hostaddr[maxidx];
+#endif
int try, i;
for (try = 0; try < 2; try++) {
@@ -5804,10 +5482,12 @@ static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
} else {
/* range 0.5 <= a < 1.0 */
+ int64_t q_int;
+
/* a in units of 1/256 rounded down */
/* q1 = (int)(a * 256.0); */
q = float64_mul(float64_256, a, s);
- int64_t q_int = float64_to_int64_round_to_zero(q, s);
+ q_int = float64_to_int64_round_to_zero(q, s);
/* reciprocal root r */
/* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
diff --git a/qemu/target-arm/internals.h b/qemu/target-arm/internals.h
index 72441218..0b401fb0 100644
--- a/qemu/target-arm/internals.h
+++ b/qemu/target-arm/internals.h
@@ -43,21 +43,22 @@ static inline bool excp_is_internal(int excp)
* precisely correspond to architectural exceptions.
*/
static const char * const excnames[] = {
- [EXCP_UDEF] = "Undefined Instruction",
- [EXCP_SWI] = "SVC",
- [EXCP_PREFETCH_ABORT] = "Prefetch Abort",
- [EXCP_DATA_ABORT] = "Data Abort",
- [EXCP_IRQ] = "IRQ",
- [EXCP_FIQ] = "FIQ",
- [EXCP_BKPT] = "Breakpoint",
- [EXCP_EXCEPTION_EXIT] = "QEMU v7M exception exit",
- [EXCP_KERNEL_TRAP] = "QEMU intercept of kernel commpage",
- [EXCP_STREX] = "QEMU intercept of STREX",
- [EXCP_HVC] = "Hypervisor Call",
- [EXCP_HYP_TRAP] = "Hypervisor Trap",
- [EXCP_SMC] = "Secure Monitor Call",
- [EXCP_VIRQ] = "Virtual IRQ",
- [EXCP_VFIQ] = "Virtual FIQ",
+ NULL,
+ "Undefined Instruction",
+ "SVC",
+ "Prefetch Abort",
+ "Data Abort",
+ "IRQ",
+ "FIQ",
+ "Breakpoint",
+ "QEMU v7M exception exit",
+ "QEMU intercept of kernel commpage",
+ "QEMU intercept of STREX",
+ "Hypervisor Call",
+ "Hypervisor Trap",
+ "Secure Monitor Call",
+ "Virtual IRQ",
+ "Virtual FIQ",
};
static inline void arm_log_exception(int idx)
@@ -86,9 +87,10 @@ static inline void arm_log_exception(int idx)
static inline unsigned int aarch64_banked_spsr_index(unsigned int el)
{
static const unsigned int map[4] = {
- [1] = 0, /* EL1. */
- [2] = 6, /* EL2. */
- [3] = 7, /* EL3. */
+ 0,
+ 0, /* EL1. */
+ 6, /* EL2. */
+ 7, /* EL3. */
};
assert(el >= 1 && el <= 3);
return map[el];
diff --git a/qemu/target-arm/neon_helper.c b/qemu/target-arm/neon_helper.c
index 47d13e90..d80276f8 100644
--- a/qemu/target-arm/neon_helper.c
+++ b/qemu/target-arm/neon_helper.c
@@ -704,7 +704,7 @@ uint32_t HELPER(neon_rshl_s32)(uint32_t valop, uint32_t shiftop)
if ((shift >= 32) || (shift <= -32)) {
dest = 0;
} else if (shift < 0) {
- int64_t big_dest = ((int64_t)val + (1 << (-1 - shift)));
+ int64_t big_dest = ((int64_t)val + (1ULL << (-1 - shift)));
dest = big_dest >> -shift;
} else {
dest = val << shift;
@@ -765,7 +765,7 @@ uint32_t HELPER(neon_rshl_u32)(uint32_t val, uint32_t shiftop)
} else if (shift == -32) {
dest = val >> 31;
} else if (shift < 0) {
- uint64_t big_dest = ((uint64_t)val + (1 << (-1 - shift)));
+ uint64_t big_dest = ((uint64_t)val + (1ULL << (-1 - shift)));
dest = big_dest >> -shift;
} else {
dest = val << shift;
@@ -998,7 +998,7 @@ uint32_t HELPER(neon_qrshl_u32)(CPUARMState *env, uint32_t val, uint32_t shiftop
} else if (shift == -32) {
dest = val >> 31;
} else if (shift < 0) {
- uint64_t big_dest = ((uint64_t)val + (1 << (-1 - shift)));
+ uint64_t big_dest = ((uint64_t)val + (1ULL << (-1 - shift)));
dest = big_dest >> -shift;
} else {
dest = val << shift;
@@ -1094,7 +1094,7 @@ uint32_t HELPER(neon_qrshl_s32)(CPUARMState *env, uint32_t valop, uint32_t shift
} else if (shift <= -32) {
dest = 0;
} else if (shift < 0) {
- int64_t big_dest = ((int64_t)val + (1 << (-1 - shift)));
+ int64_t big_dest = ((int64_t)val + (1ULL << (-1 - shift)));
dest = big_dest >> -shift;
} else {
dest = val << shift;
@@ -1824,20 +1824,20 @@ uint64_t HELPER(neon_negl_u16)(uint64_t x)
{
uint16_t tmp;
uint64_t result;
- result = (uint16_t)-x;
- tmp = -(x >> 16);
+ result = (uint16_t)(0-x);
+ tmp = 0-(x >> 16);
result |= (uint64_t)tmp << 16;
- tmp = -(x >> 32);
+ tmp = 0-(x >> 32);
result |= (uint64_t)tmp << 32;
- tmp = -(x >> 48);
+ tmp = 0-(x >> 48);
result |= (uint64_t)tmp << 48;
return result;
}
uint64_t HELPER(neon_negl_u32)(uint64_t x)
{
- uint32_t low = -x;
- uint32_t high = -(x >> 32);
+ uint32_t low = 0-x;
+ uint32_t high = 0-(x >> 32);
return low | ((uint64_t)high << 32);
}
@@ -1925,7 +1925,7 @@ uint32_t HELPER(neon_qabs_s32)(CPUARMState *env, uint32_t x)
SET_QC();
x = ~SIGNBIT;
} else if ((int32_t)x < 0) {
- x = -x;
+ x = 0-x;
}
return x;
}
@@ -1936,7 +1936,7 @@ uint32_t HELPER(neon_qneg_s32)(CPUARMState *env, uint32_t x)
SET_QC();
x = ~SIGNBIT;
} else {
- x = -x;
+ x = 0-x;
}
return x;
}
@@ -1947,7 +1947,7 @@ uint64_t HELPER(neon_qabs_s64)(CPUARMState *env, uint64_t x)
SET_QC();
x = ~SIGNBIT64;
} else if ((int64_t)x < 0) {
- x = -x;
+ x = 0-x;
}
return x;
}
@@ -1958,7 +1958,7 @@ uint64_t HELPER(neon_qneg_s64)(CPUARMState *env, uint64_t x)
SET_QC();
x = ~SIGNBIT64;
} else {
- x = -x;
+ x = 0-x;
}
return x;
}
diff --git a/qemu/target-arm/translate-a64.c b/qemu/target-arm/translate-a64.c
index 017d170e..2953165b 100644
--- a/qemu/target-arm/translate-a64.c
+++ b/qemu/target-arm/translate-a64.c
@@ -1679,7 +1679,7 @@ static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
TCGv_i64 hitmp = tcg_temp_new_i64(tcg_ctx);
g_assert(size >= 2);
- tcg_gen_addi_i64(tcg_ctx, addr2, addr, 1 << size);
+ tcg_gen_addi_i64(tcg_ctx, addr2, addr, 1ULL << size);
tcg_gen_qemu_ld_i64(s->uc, hitmp, addr2, get_mem_index(s), memop);
tcg_temp_free_i64(tcg_ctx, addr2);
tcg_gen_mov_i64(tcg_ctx, tcg_ctx->cpu_exclusive_high, hitmp);
@@ -1740,7 +1740,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
TCGv_i64 addrhi = tcg_temp_new_i64(tcg_ctx);
TCGv_i64 tmphi = tcg_temp_new_i64(tcg_ctx);
- tcg_gen_addi_i64(tcg_ctx, addrhi, addr, 1 << size);
+ tcg_gen_addi_i64(tcg_ctx, addrhi, addr, 1ULL << size);
tcg_gen_qemu_ld_i64(s->uc, tmphi, addrhi, get_mem_index(s), MO_TE + size);
tcg_gen_brcond_i64(tcg_ctx, TCG_COND_NE, tmphi, tcg_ctx->cpu_exclusive_high, fail_label);
@@ -1753,7 +1753,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
if (is_pair) {
TCGv_i64 addrhi = tcg_temp_new_i64(tcg_ctx);
- tcg_gen_addi_i64(tcg_ctx, addrhi, addr, 1 << size);
+ tcg_gen_addi_i64(tcg_ctx, addrhi, addr, 1ULL << size);
tcg_gen_qemu_st_i64(s->uc, cpu_reg(s, rt2), addrhi,
get_mem_index(s), MO_TE + size);
tcg_temp_free_i64(tcg_ctx, addrhi);
@@ -1832,7 +1832,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
}
if (is_pair) {
TCGv_i64 tcg_rt2 = cpu_reg(s, rt);
- tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1 << size);
+ tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1ULL << size);
if (is_store) {
do_gpr_st(s, tcg_rt2, tcg_addr, size);
} else {
@@ -2015,7 +2015,7 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
do_gpr_st(s, tcg_rt, tcg_addr, size);
}
}
- tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1 << size);
+ tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, 1ULL << size);
if (is_vector) {
if (is_load) {
do_fp_ld(s, rt2, tcg_addr, size);
@@ -2033,9 +2033,9 @@ static void disas_ldst_pair(DisasContext *s, uint32_t insn)
if (wback) {
if (postindex) {
- tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, offset - (1 << size));
+ tcg_gen_addi_i64(tcg_ctx, tcg_addr, tcg_addr, offset - (1ULL << size));
} else {
- tcg_gen_subi_i64(tcg_ctx, tcg_addr, tcg_addr, 1 << size);
+ tcg_gen_subi_i64(tcg_ctx, tcg_addr, tcg_addr, 1ULL << size);
}
tcg_gen_mov_i64(tcg_ctx, cpu_reg_sp(s, rn), tcg_addr);
}
@@ -4449,9 +4449,9 @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
handle_fp_fcvt(s, opcode, rd, rn, dtype, type);
break;
}
- case 0x0 ... 0x3:
- case 0x8 ... 0xc:
- case 0xe ... 0xf:
+ case 0x0: case 0x1: case 0x2: case 0x3:
+ case 0x8: case 0x9: case 0xa: case 0xb: case 0xc:
+ case 0xe: case 0xf:
/* 32-to-32 and 64-to-64 ops */
switch (type) {
case 0:
@@ -5920,7 +5920,7 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
int i;
imm = 0;
for (i = 0; i < 8; i++) {
- if ((abcdefgh) & (1 << i)) {
+ if ((abcdefgh) & (1ULL << i)) {
imm |= 0xffULL << (i * 8);
}
}
@@ -7940,8 +7940,8 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
}
handle_2misc_narrow(s, true, opcode, u, false, size, rn, rd);
return;
- case 0xc ... 0xf:
- case 0x16 ... 0x1d:
+ case 0x0c: case 0x0d: case 0x0e: case 0x0f:
+ case 0x16: case 0x17: case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d:
case 0x1f:
/* Floating point: U, size[1] and opcode indicate operation;
* size[0] indicates single or double precision.
@@ -9523,7 +9523,10 @@ static void disas_simd_three_reg_same(DisasContext *s, uint32_t insn)
handle_simd_3same_pair(s, is_q, u, opcode, size, rn, rm, rd);
break;
}
- case 0x18 ... 0x31:
+ case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: case 0x1e: case 0x1f:
+ case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: case 0x26: case 0x27:
+ case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: case 0x2e: case 0x2f:
+ case 0x30: case 0x31:
/* floating point ops, sz[1] and U are part of opcode */
disas_simd_3same_float(s, insn);
break;
@@ -9866,8 +9869,8 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
return;
}
break;
- case 0xc ... 0xf:
- case 0x16 ... 0x1d:
+ case 0x0c: case 0x0d: case 0x0e: case 0x0f:
+ case 0x16: case 0x17: case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d:
case 0x1f:
{
/* Floating point: U, size[1] and opcode indicate operation;
diff --git a/qemu/target-arm/translate.c b/qemu/target-arm/translate.c
index a66ebf65..6a198a41 100644
--- a/qemu/target-arm/translate.c
+++ b/qemu/target-arm/translate.c
@@ -1568,7 +1568,7 @@ static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn,
if (insn & (1 << 23))
tcg_gen_addi_i32(tcg_ctx, tmp, tmp, offset);
else
- tcg_gen_addi_i32(tcg_ctx, tmp, tmp, -offset);
+ tcg_gen_addi_i32(tcg_ctx, tmp, tmp, 0-offset);
tcg_gen_mov_i32(tcg_ctx, dest, tmp);
if (insn & (1 << 21))
store_reg(s, rd, tmp);
@@ -1580,7 +1580,7 @@ static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn,
if (insn & (1 << 23))
tcg_gen_addi_i32(tcg_ctx, tmp, tmp, offset);
else
- tcg_gen_addi_i32(tcg_ctx, tmp, tmp, -offset);
+ tcg_gen_addi_i32(tcg_ctx, tmp, tmp, 0-offset);
store_reg(s, rd, tmp);
} else if (!(insn & (1 << 23)))
return 1;
@@ -2688,9 +2688,20 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
return 1;
}
-#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
-#define VFP_SREG(insn, bigbit, smallbit) \
- ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
+// this causes "warning C4293: shift count negative or too big, undefined behavior"
+// on msvc, so is replaced with separate versions for the shift to perform.
+//#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
+//#define VFP_SREG(insn, bigbit, smallbit) \
+// ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
+
+#define VFP_REG_SHR_NEG(insn, n) ((insn) << -(n))
+#define VFP_SREG_NEG(insn, bigbit, smallbit) \
+ ((VFP_REG_SHR_NEG(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
+
+#define VFP_REG_SHR_POS(x, n) ((insn) >> (n))
+#define VFP_SREG_POS(insn, bigbit, smallbit) \
+ ((VFP_REG_SHR_POS(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
+
#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \
reg = (((insn) >> (bigbit)) & 0x0f) \
@@ -2701,11 +2712,11 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
reg = ((insn) >> (bigbit)) & 0x0f; \
}} while (0)
-#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
+#define VFP_SREG_D(insn) VFP_SREG_POS(insn, 12, 22)
#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
-#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
+#define VFP_SREG_N(insn) VFP_SREG_POS(insn, 16, 7)
#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
-#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
+#define VFP_SREG_M(insn) VFP_SREG_NEG(insn, 0, 5)
#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
/* Move between integer and VFP cores. */
@@ -3913,7 +3924,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
/* Single load/store */
offset = (insn & 0xff) << 2;
if ((insn & (1 << 23)) == 0)
- offset = -offset;
+ offset = 0-offset;
if (s->thumb && rn == 15) {
/* This is actually UNPREDICTABLE */
addr = tcg_temp_new_i32(tcg_ctx);
@@ -3961,7 +3972,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
addr = load_reg(s, rn);
}
if (insn & (1 << 24)) /* pre-decrement */
- tcg_gen_addi_i32(tcg_ctx, addr, addr, -((insn & 0xff) << 2));
+ tcg_gen_addi_i32(tcg_ctx, addr, addr, 0-((insn & 0xff) << 2));
if (dp)
offset = 8;
@@ -3982,7 +3993,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
if (w) {
/* writeback */
if (insn & (1 << 24))
- offset = -offset * n;
+ offset = (0-offset) * n;
else if (dp && (insn & 1))
offset = 4;
else
@@ -4976,38 +4987,38 @@ static void gen_neon_narrow_op(DisasContext *s, int op, int u, int size,
#define NEON_3R_FLOAT_MISC 31 /* float VRECPS, VRSQRTS, VMAXNM/MINNM */
static const uint8_t neon_3r_sizes[] = {
- [NEON_3R_VHADD] = 0x7,
- [NEON_3R_VQADD] = 0xf,
- [NEON_3R_VRHADD] = 0x7,
- [NEON_3R_LOGIC] = 0xf, /* size field encodes op type */
- [NEON_3R_VHSUB] = 0x7,
- [NEON_3R_VQSUB] = 0xf,
- [NEON_3R_VCGT] = 0x7,
- [NEON_3R_VCGE] = 0x7,
- [NEON_3R_VSHL] = 0xf,
- [NEON_3R_VQSHL] = 0xf,
- [NEON_3R_VRSHL] = 0xf,
- [NEON_3R_VQRSHL] = 0xf,
- [NEON_3R_VMAX] = 0x7,
- [NEON_3R_VMIN] = 0x7,
- [NEON_3R_VABD] = 0x7,
- [NEON_3R_VABA] = 0x7,
- [NEON_3R_VADD_VSUB] = 0xf,
- [NEON_3R_VTST_VCEQ] = 0x7,
- [NEON_3R_VML] = 0x7,
- [NEON_3R_VMUL] = 0x7,
- [NEON_3R_VPMAX] = 0x7,
- [NEON_3R_VPMIN] = 0x7,
- [NEON_3R_VQDMULH_VQRDMULH] = 0x6,
- [NEON_3R_VPADD] = 0x7,
- [NEON_3R_SHA] = 0xf, /* size field encodes op type */
- [NEON_3R_VFM] = 0x5, /* size bit 1 encodes op */
- [NEON_3R_FLOAT_ARITH] = 0x5, /* size bit 1 encodes op */
- [NEON_3R_FLOAT_MULTIPLY] = 0x5, /* size bit 1 encodes op */
- [NEON_3R_FLOAT_CMP] = 0x5, /* size bit 1 encodes op */
- [NEON_3R_FLOAT_ACMP] = 0x5, /* size bit 1 encodes op */
- [NEON_3R_FLOAT_MINMAX] = 0x5, /* size bit 1 encodes op */
- [NEON_3R_FLOAT_MISC] = 0x5, /* size bit 1 encodes op */
+ /*NEON_3R_VHADD*/ 0x7,
+ /*NEON_3R_VQADD*/ 0xf,
+ /*NEON_3R_VRHADD*/ 0x7,
+ /*NEON_3R_LOGIC*/ 0xf, /* size field encodes op type */
+ /*NEON_3R_VHSUB*/ 0x7,
+ /*NEON_3R_VQSUB*/ 0xf,
+ /*NEON_3R_VCGT*/ 0x7,
+ /*NEON_3R_VCGE*/ 0x7,
+ /*NEON_3R_VSHL*/ 0xf,
+ /*NEON_3R_VQSHL*/ 0xf,
+ /*NEON_3R_VRSHL*/ 0xf,
+ /*NEON_3R_VQRSHL*/ 0xf,
+ /*NEON_3R_VMAX*/ 0x7,
+ /*NEON_3R_VMIN*/ 0x7,
+ /*NEON_3R_VABD*/ 0x7,
+ /*NEON_3R_VABA*/ 0x7,
+ /*NEON_3R_VADD_VSUB*/ 0xf,
+ /*NEON_3R_VTST_VCEQ*/ 0x7,
+ /*NEON_3R_VML*/ 0x7,
+ /*NEON_3R_VMUL*/ 0x7,
+ /*NEON_3R_VPMAX*/ 0x7,
+ /*NEON_3R_VPMIN*/ 0x7,
+ /*NEON_3R_VQDMULH_VQRDMULH*/ 0x6,
+ /*NEON_3R_VPADD*/ 0x7,
+ /*NEON_3R_SHA*/ 0xf, /* size field encodes op type */
+ /*NEON_3R_VFM*/ 0x5, /* size bit 1 encodes op */
+ /*NEON_3R_FLOAT_ARITH*/ 0x5, /* size bit 1 encodes op */
+ /*NEON_3R_FLOAT_MULTIPLY*/ 0x5, /* size bit 1 encodes op */
+ /*NEON_3R_FLOAT_CMP*/ 0x5, /* size bit 1 encodes op */
+ /*NEON_3R_FLOAT_ACMP*/ 0x5, /* size bit 1 encodes op */
+ /*NEON_3R_FLOAT_MINMAX*/ 0x5, /* size bit 1 encodes op */
+ /*NEON_3R_FLOAT_MISC*/ 0x5, /* size bit 1 encodes op */
};
/* Symbolic constants for op fields for Neon 2-register miscellaneous.
@@ -5092,68 +5103,70 @@ static int neon_2rm_is_float_op(int op)
* op values will have no bits set they always UNDEF.
*/
static const uint8_t neon_2rm_sizes[] = {
- [NEON_2RM_VREV64] = 0x7,
- [NEON_2RM_VREV32] = 0x3,
- [NEON_2RM_VREV16] = 0x1,
- [NEON_2RM_VPADDL] = 0x7,
- [NEON_2RM_VPADDL_U] = 0x7,
- [NEON_2RM_AESE] = 0x1,
- [NEON_2RM_AESMC] = 0x1,
- [NEON_2RM_VCLS] = 0x7,
- [NEON_2RM_VCLZ] = 0x7,
- [NEON_2RM_VCNT] = 0x1,
- [NEON_2RM_VMVN] = 0x1,
- [NEON_2RM_VPADAL] = 0x7,
- [NEON_2RM_VPADAL_U] = 0x7,
- [NEON_2RM_VQABS] = 0x7,
- [NEON_2RM_VQNEG] = 0x7,
- [NEON_2RM_VCGT0] = 0x7,
- [NEON_2RM_VCGE0] = 0x7,
- [NEON_2RM_VCEQ0] = 0x7,
- [NEON_2RM_VCLE0] = 0x7,
- [NEON_2RM_VCLT0] = 0x7,
- [NEON_2RM_SHA1H] = 0x4,
- [NEON_2RM_VABS] = 0x7,
- [NEON_2RM_VNEG] = 0x7,
- [NEON_2RM_VCGT0_F] = 0x4,
- [NEON_2RM_VCGE0_F] = 0x4,
- [NEON_2RM_VCEQ0_F] = 0x4,
- [NEON_2RM_VCLE0_F] = 0x4,
- [NEON_2RM_VCLT0_F] = 0x4,
- [NEON_2RM_VABS_F] = 0x4,
- [NEON_2RM_VNEG_F] = 0x4,
- [NEON_2RM_VSWP] = 0x1,
- [NEON_2RM_VTRN] = 0x7,
- [NEON_2RM_VUZP] = 0x7,
- [NEON_2RM_VZIP] = 0x7,
- [NEON_2RM_VMOVN] = 0x7,
- [NEON_2RM_VQMOVN] = 0x7,
- [NEON_2RM_VSHLL] = 0x7,
- [NEON_2RM_SHA1SU1] = 0x4,
- [NEON_2RM_VRINTN] = 0x4,
- [NEON_2RM_VRINTX] = 0x4,
- [NEON_2RM_VRINTA] = 0x4,
- [NEON_2RM_VRINTZ] = 0x4,
- [NEON_2RM_VCVT_F16_F32] = 0x2,
- [NEON_2RM_VRINTM] = 0x4,
- [NEON_2RM_VCVT_F32_F16] = 0x2,
- [NEON_2RM_VRINTP] = 0x4,
- [NEON_2RM_VCVTAU] = 0x4,
- [NEON_2RM_VCVTAS] = 0x4,
- [NEON_2RM_VCVTNU] = 0x4,
- [NEON_2RM_VCVTNS] = 0x4,
- [NEON_2RM_VCVTPU] = 0x4,
- [NEON_2RM_VCVTPS] = 0x4,
- [NEON_2RM_VCVTMU] = 0x4,
- [NEON_2RM_VCVTMS] = 0x4,
- [NEON_2RM_VRECPE] = 0x4,
- [NEON_2RM_VRSQRTE] = 0x4,
- [NEON_2RM_VRECPE_F] = 0x4,
- [NEON_2RM_VRSQRTE_F] = 0x4,
- [NEON_2RM_VCVT_FS] = 0x4,
- [NEON_2RM_VCVT_FU] = 0x4,
- [NEON_2RM_VCVT_SF] = 0x4,
- [NEON_2RM_VCVT_UF] = 0x4,
+ /*NEON_2RM_VREV64*/ 0x7,
+ /*NEON_2RM_VREV32*/ 0x3,
+ /*NEON_2RM_VREV16*/ 0x1,
+ 0,
+ /*NEON_2RM_VPADDL*/ 0x7,
+ /*NEON_2RM_VPADDL_U*/ 0x7,
+ /*NEON_2RM_AESE*/ 0x1,
+ /*NEON_2RM_AESMC*/ 0x1,
+ /*NEON_2RM_VCLS*/ 0x7,
+ /*NEON_2RM_VCLZ*/ 0x7,
+ /*NEON_2RM_VCNT*/ 0x1,
+ /*NEON_2RM_VMVN*/ 0x1,
+ /*NEON_2RM_VPADAL*/ 0x7,
+ /*NEON_2RM_VPADAL_U*/ 0x7,
+ /*NEON_2RM_VQABS*/ 0x7,
+ /*NEON_2RM_VQNEG*/ 0x7,
+ /*NEON_2RM_VCGT0*/ 0x7,
+ /*NEON_2RM_VCGE0*/ 0x7,
+ /*NEON_2RM_VCEQ0*/ 0x7,
+ /*NEON_2RM_VCLE0*/ 0x7,
+ /*NEON_2RM_VCLT0*/ 0x7,
+ /*NEON_2RM_SHA1H*/ 0x4,
+ /*NEON_2RM_VABS*/ 0x7,
+ /*NEON_2RM_VNEG*/ 0x7,
+ /*NEON_2RM_VCGT0_F*/ 0x4,
+ /*NEON_2RM_VCGE0_F*/ 0x4,
+ /*NEON_2RM_VCEQ0_F*/ 0x4,
+ /*NEON_2RM_VCLE0_F*/ 0x4,
+ /*NEON_2RM_VCLT0_F*/ 0x4,
+ 0,
+ /*NEON_2RM_VABS_F*/ 0x4,
+ /*NEON_2RM_VNEG_F*/ 0x4,
+ /*NEON_2RM_VSWP*/ 0x1,
+ /*NEON_2RM_VTRN*/ 0x7,
+ /*NEON_2RM_VUZP*/ 0x7,
+ /*NEON_2RM_VZIP*/ 0x7,
+ /*NEON_2RM_VMOVN*/ 0x7,
+ /*NEON_2RM_VQMOVN*/ 0x7,
+ /*NEON_2RM_VSHLL*/ 0x7,
+ /*NEON_2RM_SHA1SU1*/ 0x4,
+ /*NEON_2RM_VRINTN*/ 0x4,
+ /*NEON_2RM_VRINTX*/ 0x4,
+ /*NEON_2RM_VRINTA*/ 0x4,
+ /*NEON_2RM_VRINTZ*/ 0x4,
+ /*NEON_2RM_VCVT_F16_F32*/ 0x2,
+ /*NEON_2RM_VRINTM*/ 0x4,
+ /*NEON_2RM_VCVT_F32_F16*/ 0x2,
+ /*NEON_2RM_VRINTP*/ 0x4,
+ /*NEON_2RM_VCVTAU*/ 0x4,
+ /*NEON_2RM_VCVTAS*/ 0x4,
+ /*NEON_2RM_VCVTNU*/ 0x4,
+ /*NEON_2RM_VCVTNS*/ 0x4,
+ /*NEON_2RM_VCVTPU*/ 0x4,
+ /*NEON_2RM_VCVTPS*/ 0x4,
+ /*NEON_2RM_VCVTMU*/ 0x4,
+ /*NEON_2RM_VCVTMS*/ 0x4,
+ /*NEON_2RM_VRECPE*/ 0x4,
+ /*NEON_2RM_VRSQRTE*/ 0x4,
+ /*NEON_2RM_VRECPE_F*/ 0x4,
+ /*NEON_2RM_VRSQRTE_F*/ 0x4,
+ /*NEON_2RM_VCVT_FS*/ 0x4,
+ /*NEON_2RM_VCVT_FU*/ 0x4,
+ /*NEON_2RM_VCVT_SF*/ 0x4,
+ /*NEON_2RM_VCVT_UF*/ 0x4,
};
/* Translate a NEON data processing instruction. Return nonzero if the
@@ -5803,8 +5816,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
tcg_gen_add_i64(tcg_ctx, tcg_ctx->cpu_V0, tcg_ctx->cpu_V0, tcg_ctx->cpu_V1);
} else if (op == 4 || (op == 5 && u)) {
/* Insert */
- neon_load_reg64(tcg_ctx, tcg_ctx->cpu_V1, rd + pass);
uint64_t mask;
+ neon_load_reg64(tcg_ctx, tcg_ctx->cpu_V1, rd + pass);
if (shift < -63 || shift > 63) {
mask = 0;
} else {
@@ -9283,7 +9296,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
}
offset = (insn & 0xff) * 4;
if ((insn & (1 << 23)) == 0)
- offset = -offset;
+ offset = 0-offset;
if (insn & (1 << 24)) {
tcg_gen_addi_i32(tcg_ctx, addr, addr, offset);
offset = 0;
@@ -9465,7 +9478,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
offset += 4;
}
if (insn & (1 << 24)) {
- tcg_gen_addi_i32(tcg_ctx, addr, addr, -offset);
+ tcg_gen_addi_i32(tcg_ctx, addr, addr, 0-offset);
}
TCGV_UNUSED_I32(loaded_var);
@@ -9498,7 +9511,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
if (insn & (1 << 21)) {
/* Base register writeback. */
if (insn & (1 << 24)) {
- tcg_gen_addi_i32(tcg_ctx, addr, addr, -offset);
+ tcg_gen_addi_i32(tcg_ctx, addr, addr, 0-offset);
}
/* Fault if writeback register is in register list. */
if (insn & (1 << rn))
@@ -10287,21 +10300,21 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
tcg_temp_free_i32(tcg_ctx, tmp);
break;
case 0xc: /* Negative offset. */
- tcg_gen_addi_i32(tcg_ctx, addr, addr, -imm);
+ tcg_gen_addi_i32(tcg_ctx, addr, addr, 0-imm);
break;
case 0xe: /* User privilege. */
tcg_gen_addi_i32(tcg_ctx, addr, addr, imm);
memidx = MMU_USER_IDX;
break;
case 0x9: /* Post-decrement. */
- imm = -imm;
+ imm = 0-imm;
/* Fall through. */
case 0xb: /* Post-increment. */
postinc = 1;
writeback = 1;
break;
case 0xd: /* Pre-decrement. */
- imm = -imm;
+ imm = 0-imm;
/* Fall through. */
case 0xf: /* Pre-increment. */
tcg_gen_addi_i32(tcg_ctx, addr, addr, imm);
diff --git a/qemu/target-arm/unicorn_aarch64.c b/qemu/target-arm/unicorn_aarch64.c
index 3a5915a5..3631e9ce 100644
--- a/qemu/target-arm/unicorn_aarch64.c
+++ b/qemu/target-arm/unicorn_aarch64.c
@@ -21,11 +21,13 @@ void arm64_release(void* ctx);
void arm64_release(void* ctx)
{
+ struct uc_struct* uc;
+ ARMCPU* cpu;
TCGContext *s = (TCGContext *) ctx;
g_free(s->tb_ctx.tbs);
- struct uc_struct* uc = s->uc;
- ARMCPU* cpu = (ARMCPU*) uc->cpu;
+ uc = s->uc;
+ cpu = (ARMCPU*) uc->cpu;
g_free(cpu->cpreg_indexes);
g_free(cpu->cpreg_values);
g_free(cpu->cpreg_vmstate_indexes);
diff --git a/qemu/target-arm/unicorn_arm.c b/qemu/target-arm/unicorn_arm.c
index 69f7363a..4aeede85 100644
--- a/qemu/target-arm/unicorn_arm.c
+++ b/qemu/target-arm/unicorn_arm.c
@@ -22,11 +22,13 @@ void arm_release(void* ctx);
void arm_release(void* ctx)
{
+ ARMCPU* cpu;
+ struct uc_struct* uc;
TCGContext *s = (TCGContext *) ctx;
g_free(s->tb_ctx.tbs);
- struct uc_struct* uc = s->uc;
- ARMCPU* cpu = (ARMCPU*) uc->cpu;
+ uc = s->uc;
+ cpu = (ARMCPU*) uc->cpu;
g_free(cpu->cpreg_indexes);
g_free(cpu->cpreg_values);
g_free(cpu->cpreg_vmstate_indexes);
@@ -37,8 +39,8 @@ void arm_release(void* ctx)
void arm_reg_reset(struct uc_struct *uc)
{
- (void)uc;
CPUArchState *env;
+ (void)uc;
env = uc->cpu->env_ptr;
memset(env->regs, 0, sizeof(env->regs));
diff --git a/qemu/util/oslib-win32.c b/qemu/util/oslib-win32.c
index 5f5eec98..cb60b98c 100644
--- a/qemu/util/oslib-win32.c
+++ b/qemu/util/oslib-win32.c
@@ -34,7 +34,11 @@
#include "sysemu/sysemu.h"
/* this must come after including "trace.h" */
+/* The pragmas are to fix this issue: https://connect.microsoft.com/VisualStudio/feedback/details/976983 */
+#pragma warning(push)
+#pragma warning(disable : 4091)
#include
+#pragma warning(pop)
void *qemu_oom_check(void *ptr)
{