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fix some oss-fuzz (#1192) 

* fix oss-fuzz 10419.

* fix oss-fuzz 10427.

* fix oss-fuzz 10421.

* fix oss-fuzz 10422.

* fix oss-fuzz 10425.

* fix oss-fuzz 10426.

* fix oss-fuzz 10426.

* fix oss-fuzz 10422.

* fix oss-fuzz  10426.

* fix oss-fuzz 10456.

* fix oss-fuzz 10428.

* fix oss-fuzz 10429.

* fix oss-fuzz 10431.

* fix oss-fuzz 10435.

* fix oss-fuzz 10430.

* fix oss-fuzz 10436.

* remove unused var.

* fix oss-fuzz 10449.

* fix oss-fuzz 10452.

* fix oss-fuzz 11792.

* fix oss-fuzz 10457.

* fix oss-fuzz 11737.

* fix oss-fuzz 10458.

* fix oss-fuzz 10565.

* fix oss-fuzz 11651.

* fix oss-fuzz 10497.

* fix oss-fuzz 10515.

* fix oss-fuzz 10586.

* fix oss-fuzz 10597.

* fiz oss-fuzz 11721.

* fix oss-fuzz 10718.

* fix oss-fuzz 15610.

* fix oss-fuzz 10512.

* fix oss-fuzz 10545.

* fix oss-fuzz 10598.

* fix oss-fuzz 11112.

* fix oss-fuzz 11589.

* fix oss-fuzz 10674.

* git fix oss-fuzz 19610.

* fix oss-fuzz 19848.

* fix oss-fuzz 19851.

* fix oss-fuzz 19852.

* fix oss-fuzz 10878.

* fix oss-fuzz 11655.

* fix oss-fuzz 19849.

* fix oss-fuzz 11765.

* fix oss-fuzz 10337.

* fix oss-fuzz 10575.

* fix oss-fuzz 19877.

* fix oss-fuzz 19895.

* fix oss-fuzz 19896.

* fix oss-fuzz 19897.

* remove verbose fprintf output.

* fix oss-fuzz 19943.

* fix oss-fuzz 20026.

* fix oss-fuzz 20027.

* fix oss-fuzz 19967.

* fix oss-fuzz 19946.

* fix oss-fuzz 20069.

* fix oss-fuzz 20071.

* fix oss-fuzz 20073.

* fix oss-fuzz 20075.

* fix oss-fuzz 20076.

* fix a operation mistake.

* fix oss-fuzz 20101.

* fix oss-fuzz 20152.

* fix oss-fuzz 20101.

* fix oss-fuzz 20154.

* fix oss-fuzz 20166.

* fix oss-fuzz 14042.
This commit is contained in:
Chen Huitao 2020-01-18 23:49:36 +08:00 committed by Nguyen Anh Quynh
parent 6398248534
commit 8b99637f77
2 changed files with 21 additions and 16 deletions
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5
qemu/target-mips/helper.c
View File

@ -341,10 +341,15 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
" prot %d\n",
__func__, address, ret, physical, prot);
if (ret == TLBRET_MATCH) {
if (mmu_idx < 0 || mmu_idx >= NB_MMU_MODES) {
raise_mmu_exception(env, address, rw, ret);
ret = 1;
} else {
tlb_set_page(cs, address & TARGET_PAGE_MASK,
physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
mmu_idx, TARGET_PAGE_SIZE);
ret = 0;
}
} else if (ret < 0)
#endif
{

32
qemu/target-mips/translate.c
View File

@ -18572,19 +18572,19 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_BLTZ:
case OPC_BGEZ:
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
gen_compute_branch(ctx, op1, 4, rs, -1, (uint16_t)imm << 2, 4);
break;
case OPC_BLTZAL:
case OPC_BGEZAL:
if (ctx->insn_flags & ISA_MIPS32R6) {
if (rs == 0) {
/* OPC_NAL, OPC_BAL */
gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4);
gen_compute_branch(ctx, op1, 4, 0, -1, (uint16_t)imm << 2, 4);
} else {
generate_exception(ctx, EXCP_RI);
}
} else {
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
gen_compute_branch(ctx, op1, 4, rs, -1, (uint16_t)imm << 2, 4);
}
break;
case OPC_TGEI: case OPC_TGEIU: case OPC_TLTI: case OPC_TLTIU: case OPC_TEQI: /* REGIMM traps */
@ -18720,7 +18720,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
case OPC_BOVC: /* OPC_BEQZALC, OPC_BEQC, OPC_ADDI */
if (ctx->insn_flags & ISA_MIPS32R6) {
/* OPC_BOVC, OPC_BEQZALC, OPC_BEQC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
gen_compute_compact_branch(ctx, op, rs, rt, (uint16_t)imm << 2);
} else {
/* OPC_ADDI */
/* Arithmetic with immediate opcode */
@ -18752,10 +18752,10 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
break;
}
/* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
gen_compute_compact_branch(ctx, op, rs, rt, (uint16_t)imm << 2);
} else {
/* OPC_BLEZL */
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
gen_compute_branch(ctx, op, 4, rs, rt, (uint16_t)imm << 2, 4);
}
break;
case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */
@ -18765,30 +18765,30 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
break;
}
/* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
gen_compute_compact_branch(ctx, op, rs, rt, (uint16_t)imm << 2);
} else {
/* OPC_BGTZL */
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
gen_compute_branch(ctx, op, 4, rs, rt, (uint16_t)imm << 2, 4);
}
break;
case OPC_BLEZALC: /* OPC_BGEZALC, OPC_BGEUC, OPC_BLEZ */
if (rt == 0) {
/* OPC_BLEZ */
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
gen_compute_branch(ctx, op, 4, rs, rt, (uint16_t)imm << 2, 4);
} else {
check_insn(ctx, ISA_MIPS32R6);
/* OPC_BLEZALC, OPC_BGEZALC, OPC_BGEUC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
gen_compute_compact_branch(ctx, op, rs, rt, (uint16_t)imm << 2);
}
break;
case OPC_BGTZALC: /* OPC_BLTZALC, OPC_BLTUC, OPC_BGTZ */
if (rt == 0) {
/* OPC_BGTZ */
gen_compute_branch(ctx, op, 4, rs, rt, imm << 2, 4);
gen_compute_branch(ctx, op, 4, rs, rt, (uint16_t)imm << 2, 4);
} else {
check_insn(ctx, ISA_MIPS32R6);
/* OPC_BGTZALC, OPC_BLTZALC, OPC_BLTUC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
gen_compute_compact_branch(ctx, op, rs, rt, (uint16_t)imm << 2);
}
break;
case OPC_BEQL:
@ -18890,7 +18890,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
check_cp1_enabled(ctx);
check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_compute_branch1(ctx, MASK_BC1(ctx->opcode),
(rt >> 2) & 0x7, imm << 2);
(rt >> 2) & 0x7, (uint16_t)imm << 2);
break;
case OPC_PS_FMT:
check_cp1_enabled(ctx);
@ -19092,7 +19092,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC, OPC_DADDI */
if (ctx->insn_flags & ISA_MIPS32R6) {
/* OPC_BNVC, OPC_BNEZALC, OPC_BNEC */
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
gen_compute_compact_branch(ctx, op, rs, rt, (uint16_t)imm << 2);
} else {
/* OPC_DADDI */
check_insn(ctx, ISA_MIPS3);
@ -19108,7 +19108,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
#else
case OPC_BNVC: /* OPC_BNEZALC, OPC_BNEC */
if (ctx->insn_flags & ISA_MIPS32R6) {
gen_compute_compact_branch(ctx, op, rs, rt, imm << 2);
gen_compute_compact_branch(ctx, op, rs, rt, (uint16_t)imm << 2);
} else {
MIPS_INVAL("major opcode");
generate_exception(ctx, EXCP_RI);
@ -19123,7 +19123,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
if (rt != 0) {
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_load_gpr(ctx, t0, rs);
tcg_gen_addi_tl(tcg_ctx, *cpu_gpr[rt], t0, imm << 16);
tcg_gen_addi_tl(tcg_ctx, *cpu_gpr[rt], t0, (uint16_t)imm << 16);
tcg_temp_free(tcg_ctx, t0);
}
MIPS_DEBUG("daui %s, %s, %04x", regnames[rt], regnames[rs], imm);