regress: convert some mips tests to use unittest
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8b4d274c34
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@ -3,6 +3,8 @@
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from unicorn import *
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from unicorn.mips_const import *
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import regress
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def code_hook(uc, addr, size, user_data):
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print 'code hook: pc=%08x sp=%08x' % (addr, uc.reg_read(UC_MIPS_REG_SP))
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@ -36,6 +38,14 @@ def run(step=False):
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print 'sp =', hex(uc.reg_read(UC_MIPS_REG_SP))
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print 'at =', hex(uc.reg_read(UC_MIPS_REG_AT))
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print
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return uc.reg_read(UC_MIPS_REG_SP)
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run(step=False)
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run(step=True)
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class MipsSingleStep(regress.RegressTest):
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def test(self):
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sp1 = run(step=False)
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sp2 = run(step=True)
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self.assertEqual(sp1, sp2)
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if __name__ == '__main__':
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regress.main()
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@ -3,16 +3,25 @@
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from unicorn import *
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from unicorn.mips_const import *
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import regress
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def intr_hook(uc, intno, data):
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print 'interrupt=%d, v0=%d, pc=0x%08x' % (intno, uc.reg_read(UC_MIPS_REG_V0), uc.reg_read(UC_MIPS_REG_PC))
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addr = 0x40000
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code = '0c000000'.decode('hex') # syscall
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class MipsSyscall(regress.RegressTest):
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def test(self):
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addr = 0x40000
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code = '0c000000'.decode('hex') # syscall
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uc = Uc(UC_ARCH_MIPS, UC_MODE_MIPS32 + UC_MODE_LITTLE_ENDIAN)
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uc.mem_map(addr, 0x1000)
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uc.mem_write(addr, code)
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uc.reg_write(UC_MIPS_REG_V0, 100)
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uc.hook_add(UC_HOOK_INTR, intr_hook)
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uc = Uc(UC_ARCH_MIPS, UC_MODE_MIPS32 + UC_MODE_LITTLE_ENDIAN)
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uc.mem_map(addr, 0x1000)
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uc.mem_write(addr, code)
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uc.reg_write(UC_MIPS_REG_V0, 100)
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uc.hook_add(UC_HOOK_INTR, intr_hook)
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uc.emu_start(addr, addr+len(code))
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uc.emu_start(addr, addr+len(code))
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self.assertEqual(0x40004, uc.reg_read(UC_MIPS_REG_PC))
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if __name__ == '__main__':
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regress.main()
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