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first atttempt at SPARC64 fixes, no longer SEGV's, set CPU model to: Sun UltraSparc IV

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This commit is contained in:
mothran 2015-09-15 23:12:03 -07:00
parent fe807952d0
commit 893e6abcbd
3 changed files with 44 additions and 7 deletions
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10
qemu/hw/sparc64/sun4u.c
View File

@ -33,19 +33,23 @@
static void sun4u_init(struct uc_struct *uc, MachineState *machine) static void sun4u_init(struct uc_struct *uc, MachineState *machine)
{ {
const char *cpu_model = machine->cpu_model; const char *cpu_model = machine->cpu_model;
SPARCCPU *cpu;
if (cpu_model == NULL) if (cpu_model == NULL)
cpu_model = "sun4uv"; cpu_model = "Sun UltraSparc IV";
if (cpu_sparc_init(uc, cpu_model) == NULL) { cpu = cpu_sparc_init(uc, cpu_model);
if (cpu == NULL) {
fprintf(stderr, "Unable to find Sparc CPU definition\n"); fprintf(stderr, "Unable to find Sparc CPU definition\n");
exit(1); exit(1);
} }
cpu_sparc_set_id(&cpu->env, 0);
} }
void sun4u_machine_init(struct uc_struct *uc) void sun4u_machine_init(struct uc_struct *uc)
{ {
QEMUMachine sun4u_machine = { static QEMUMachine sun4u_machine = {
.name = "sun4u", .name = "sun4u",
.init = sun4u_init, .init = sun4u_init,
.max_cpus = 1, // XXX for now .max_cpus = 1, // XXX for now

22
qemu/target-sparc/unicorn64.c
View File

@ -6,6 +6,7 @@
#include "sysemu/cpus.h" #include "sysemu/cpus.h"
#include "unicorn.h" #include "unicorn.h"
#include "cpu.h" #include "cpu.h"
#include "unicorn_common.h"
#define READ_QWORD(x) ((uint64)x) #define READ_QWORD(x) ((uint64)x)
@ -15,6 +16,22 @@
#define READ_BYTE_L(x) (x & 0xff) #define READ_BYTE_L(x) (x & 0xff)
static bool sparc_stop_interrupt(int intno)
{
switch(intno) {
default:
return false;
case TT_ILL_INSN:
return true;
}
}
static void sparc_set_pc(struct uc_struct *uc, uint64_t address)
{
((CPUSPARCState *)uc->current_cpu->env_ptr)->pc = address;
((CPUSPARCState *)uc->current_cpu->env_ptr)->npc = address + 4;
}
void sparc_reg_reset(struct uc_struct *uc) void sparc_reg_reset(struct uc_struct *uc)
{ {
CPUArchState *env = first_cpu->env_ptr; CPUArchState *env = first_cpu->env_ptr;
@ -75,7 +92,7 @@ int sparc_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
default: break; default: break;
case UC_SPARC_REG_PC: case UC_SPARC_REG_PC:
SPARC_CPU(uc, mycpu)->env.pc = *(uint64_t *)value; SPARC_CPU(uc, mycpu)->env.pc = *(uint64_t *)value;
SPARC_CPU(uc, mycpu)->env.npc = *(uint64_t *)value + 8; SPARC_CPU(uc, mycpu)->env.npc = *(uint64_t *)value + 4;
break; break;
} }
} }
@ -93,4 +110,7 @@ void sparc64_uc_init(struct uc_struct* uc)
uc->reg_read = sparc_reg_read; uc->reg_read = sparc_reg_read;
uc->reg_write = sparc_reg_write; uc->reg_write = sparc_reg_write;
uc->reg_reset = sparc_reg_reset; uc->reg_reset = sparc_reg_reset;
uc->set_pc = sparc_set_pc;
uc->stop_interrupt = sparc_stop_interrupt;
uc_common_init(uc);
} }

19
regress/sparc64.py
View File

@ -3,9 +3,22 @@
from unicorn import * from unicorn import *
from unicorn.sparc_const import * from unicorn.sparc_const import *
PAGE_SIZE = 1 * 1024 * 1024
uc = Uc(UC_ARCH_SPARC, UC_MODE_64) uc = Uc(UC_ARCH_SPARC, UC_MODE_64)
uc.reg_write(UC_SPARC_REG_SP, 100) uc.reg_write(UC_SPARC_REG_SP, 100)
uc.reg_write(UC_SPARC_REG_FP, 100) print 'writing sp = 100, %%i0 = 2000'
print 'writing sp = 100, fp = 100'
# 0: b0 06 20 01 inc %i0
# 4: b2 06 60 01 inc %i1
CODE = "\xb0\x06\x20\x01" \
"\xb2\x06\x60\x01"
uc.mem_map(0, PAGE_SIZE)
uc.mem_write(0, CODE)
uc.emu_start(0, len(CODE), 0, 2)
print 'sp =', uc.reg_read(UC_SPARC_REG_SP) print 'sp =', uc.reg_read(UC_SPARC_REG_SP)
print 'fp =', uc.reg_read(UC_SPARC_REG_FP) print 'i0 =', uc.reg_read(UC_SPARC_REG_I0)
print 'i1 =', uc.reg_read(UC_SPARC_REG_I1)