From 871de4ad65aa95cd0871b5b9f2748ed7322c9ae5 Mon Sep 17 00:00:00 2001
From: lazymio <mio@lazym.io>
Date: Thu, 4 Nov 2021 19:58:32 +0100
Subject: [PATCH] Split mips cpu to 32 and 64

---
 include/unicorn/mips.h | 65 ++++++++++++++++++++++--------------------
 qemu/target/mips/cpu.c |  9 ++++--
 2 files changed, 41 insertions(+), 33 deletions(-)

diff --git a/include/unicorn/mips.h b/include/unicorn/mips.h
index 977ee534..7437cf75 100644
--- a/include/unicorn/mips.h
+++ b/include/unicorn/mips.h
@@ -19,37 +19,40 @@ extern "C" {
 #pragma warning(disable : 4201)
 #endif
 
-typedef enum uc_cpu_mips {
-    UC_CPU_MIPS_4KC = 0,
-    UC_CPU_MIPS_4KM,
-    UC_CPU_MIPS_4KECR1,
-    UC_CPU_MIPS_4KEMR1,
-    UC_CPU_MIPS_4KEC,
-    UC_CPU_MIPS_4KEM,
-    UC_CPU_MIPS_24KC,
-    UC_CPU_MIPS_24KEC,
-    UC_CPU_MIPS_24KF,
-    UC_CPU_MIPS_34KF,
-    UC_CPU_MIPS_74KF,
-    UC_CPU_MIPS_M14K,
-    UC_CPU_MIPS_M14KC,
-    UC_CPU_MIPS_P5600,
-    UC_CPU_MIPS_MIPS32R6_GENERIC,
-    UC_CPU_MIPS_I7200,
-    UC_CPU_MIPS_R4000,
-    UC_CPU_MIPS_VR5432,
-    UC_CPU_MIPS_5KC,
-    UC_CPU_MIPS_5KF,
-    UC_CPU_MIPS_20KC,
-    UC_CPU_MIPS_MIPS64R2_GENERIC,
-    UC_CPU_MIPS_5KEC,
-    UC_CPU_MIPS_5KEF,
-    UC_CPU_MIPS_I6400,
-    UC_CPU_MIPS_I6500,
-    UC_CPU_MIPS_LOONGSON_2E,
-    UC_CPU_MIPS_LOONGSON_2F,
-    UC_CPU_MIPS_MIPS64DSPR2
-} uc_cpu_mips;
+typedef enum uc_cpu_mips32 {
+    UC_CPU_MIPS32_4KC = 0,
+    UC_CPU_MIPS32_4KM,
+    UC_CPU_MIPS32_4KECR1,
+    UC_CPU_MIPS32_4KEMR1,
+    UC_CPU_MIPS32_4KEC,
+    UC_CPU_MIPS32_4KEM,
+    UC_CPU_MIPS32_24KC,
+    UC_CPU_MIPS32_24KEC,
+    UC_CPU_MIPS32_24KF,
+    UC_CPU_MIPS32_34KF,
+    UC_CPU_MIPS32_74KF,
+    UC_CPU_MIPS32_M14K,
+    UC_CPU_MIPS32_M14KC,
+    UC_CPU_MIPS32_P5600,
+    UC_CPU_MIPS32_MIPS32R6_GENERIC,
+    UC_CPU_MIPS32_I7200,
+} uc_cpu_mips32;
+
+typedef enum uc_cpu_mips64 {
+    UC_CPU_MIPS64_R4000 = 0,
+    UC_CPU_MIPS64_VR5432,
+    UC_CPU_MIPS64_5KC,
+    UC_CPU_MIPS64_5KF,
+    UC_CPU_MIPS64_20KC,
+    UC_CPU_MIPS64_MIPS64R2_GENERIC,
+    UC_CPU_MIPS64_5KEC,
+    UC_CPU_MIPS64_5KEF,
+    UC_CPU_MIPS64_I6400,
+    UC_CPU_MIPS64_I6500,
+    UC_CPU_MIPS64_LOONGSON_2E,
+    UC_CPU_MIPS64_LOONGSON_2F,
+    UC_CPU_MIPS64_MIPS64DSPR2
+} uc_cpu_mips64;
 
 //> MIPS registers
 typedef enum UC_MIPS_REG {
diff --git a/qemu/target/mips/cpu.c b/qemu/target/mips/cpu.c
index e29c44f1..60fd1b93 100644
--- a/qemu/target/mips/cpu.c
+++ b/qemu/target/mips/cpu.c
@@ -162,16 +162,21 @@ MIPSCPU *cpu_mips_init(struct uc_struct *uc)
         return NULL;
     }
 
-    if (uc->cpu_model == INT_MAX) {
 #ifdef TARGET_MIPS64
+    if (uc->cpu_model == INT_MAX) {
         uc->cpu_model = 17; // R4000
+    } else if (uc->cpu_model + UC_CPU_MIPS32_I7200 + 1 >= mips_defs_number ) {
+        free(cpu);
+        return NULL;
+    }
 #else
+    if (uc->cpu_model == INT_MAX) {
         uc->cpu_model = 10; // 74kf
-#endif
     } else if (uc->cpu_model >= mips_defs_number) {
         free(cpu);
         return NULL;
     }
+#endif
 
     cs = (CPUState *)cpu;
     cc = (CPUClass *)&cpu->cc;