From 772558119af66269742fe4dcc45ec6000a5a6ea7 Mon Sep 17 00:00:00 2001 From: Bet4 <0xbet4@gmail.com> Date: Thu, 8 Jul 2021 20:43:00 +0800 Subject: [PATCH] Add missing constants in rust bindings (#1423) * Update arm64.rs * Update mips.rs --- bindings/rust/src/arm64.rs | 61 ++++++++++++++- bindings/rust/src/mips.rs | 154 +++++++++++++++++++++++++++++-------- 2 files changed, 179 insertions(+), 36 deletions(-) diff --git a/bindings/rust/src/arm64.rs b/bindings/rust/src/arm64.rs index 7c24368b..8b7c1254 100644 --- a/bindings/rust/src/arm64.rs +++ b/bindings/rust/src/arm64.rs @@ -1,10 +1,12 @@ +#![allow(non_camel_case_types)] + // ARM64 registers #[repr(C)] #[derive(PartialEq, Debug, Clone, Copy)] pub enum RegisterARM64 { INVALID = 0, - FP = 1, - LR = 2, + X29 = 1, + X30 = 2, NZCV = 3, SP = 4, WSP = 5, @@ -217,8 +219,8 @@ pub enum RegisterARM64 { X13 = 212, X14 = 213, X15 = 214, - IP1 = 215, - IP0 = 216, + X16 = 215, + X17 = 216, X18 = 217, X19 = 218, X20 = 219, @@ -265,4 +267,55 @@ pub enum RegisterARM64 { // pseudo registers PC = 260, + CPACR_EL1 = 261, + + // thread registers + TPIDR_EL0 = 262, + TPIDRRO_EL0 = 263, + TPIDR_EL1 = 264, + PSTATE = 265, + + // exception link registers + ELR_EL0 = 266, + ELR_EL1 = 267, + ELR_EL2 = 268, + ELR_EL3 = 269, + + // stack pointers registers + SP_EL0 = 270, + SP_EL1 = 271, + SP_EL2 = 272, + SP_EL3 = 273, + + // other CP15 registers + TTBR0_EL1 = 274, + TTBR1_EL1 = 275, + ESR_EL0 = 276, + ESR_EL1 = 277, + ESR_EL2 = 278, + ESR_EL3 = 279, + FAR_EL0 = 280, + FAR_EL1 = 281, + FAR_EL2 = 282, + FAR_EL3 = 283, + PAR_EL1 = 284, + MAIR_EL1 = 285, + VBAR_EL0 = 286, + VBAR_EL1 = 287, + VBAR_EL2 = 288, + VBAR_EL3 = 289, + ENDING = 290, + + // alias registers + // (assoc) IP0 = 215, + // (assoc) IP1 = 216, + // (assoc) FP = 1, + // (assoc) LR = 2, +} + +impl RegisterARM64 { + pub const IP0: RegisterARM64 = RegisterARM64::X16; + pub const IP1: RegisterARM64 = RegisterARM64::X17; + pub const FP: RegisterARM64 = RegisterARM64::X29; + pub const LR: RegisterARM64 = RegisterARM64::X30; } diff --git a/bindings/rust/src/mips.rs b/bindings/rust/src/mips.rs index e6204664..a1b590c6 100644 --- a/bindings/rust/src/mips.rs +++ b/bindings/rust/src/mips.rs @@ -8,38 +8,38 @@ pub enum RegisterMIPS { // General purpose registers PC = 1, - ZERO = 2, - AT = 3, - V0 = 4, - V1 = 5, - A0 = 6, - A1 = 7, - A2 = 8, - A3 = 9, - T0 = 10, - T1 = 11, - T2 = 12, - T3 = 13, - T4 = 14, - T5 = 15, - T6 = 16, - T7 = 17, - S0 = 18, - S1 = 19, - S2 = 20, - S3 = 21, - S4 = 22, - S5 = 23, - S6 = 24, - S7 = 25, - T8 = 26, - T9 = 27, - K0 = 28, - K1 = 29, - GP = 30, - SP = 31, - FP = 32, - RA = 33, + GPR0 = 2, + GPR1 = 3, + GPR2 = 4, + GPR3 = 5, + GPR4 = 6, + GPR5 = 7, + GPR6 = 8, + GPR7 = 9, + GPR8 = 10, + GPR9 = 11, + GPR10 = 12, + GPR11 = 13, + GPR12 = 14, + GPR13 = 15, + GPR14 = 16, + GPR15 = 17, + GPR16 = 18, + GPR17 = 19, + GPR18 = 20, + GPR19 = 21, + GPR20 = 22, + GPR21 = 23, + GPR22 = 24, + GPR23 = 25, + GPR24 = 26, + GPR25 = 27, + GPR26 = 28, + GPR27 = 29, + GPR28 = 30, + GPR29 = 31, + GPR30 = 32, + GPR31 = 33, // DSP registers DSPCCOND = 34, @@ -153,4 +153,94 @@ pub enum RegisterMIPS { MPL0 = 134, MPL1 = 135, MPL2 = 136, + CP0_CONFIG3 = 137, + CP0_USERLOCAL = 138, + ENDING = 139, + + // alias registers + // (assoc) ZERO = 2, + // (assoc) AT = 3, + // (assoc) V0 = 4, + // (assoc) V1 = 5, + // (assoc) A0 = 6, + // (assoc) A1 = 7, + // (assoc) A2 = 8, + // (assoc) A3 = 9, + // (assoc) T0 = 10, + // (assoc) T1 = 11, + // (assoc) T2 = 12, + // (assoc) T3 = 13, + // (assoc) T4 = 14, + // (assoc) T5 = 15, + // (assoc) T6 = 16, + // (assoc) T7 = 17, + // (assoc) S0 = 18, + // (assoc) S1 = 19, + // (assoc) S2 = 20, + // (assoc) S3 = 21, + // (assoc) S4 = 22, + // (assoc) S5 = 23, + // (assoc) S6 = 24, + // (assoc) S7 = 25, + // (assoc) T8 = 26, + // (assoc) T9 = 27, + // (assoc) K0 = 28, + // (assoc) K1 = 29, + // (assoc) GP = 30, + // (assoc) SP = 31, + // (assoc) FP = 32, + // (assoc) S8 = 32, + // (assoc) RA = 33, + // (assoc) HI0 = 45, + // (assoc) HI1 = 46, + // (assoc) HI2 = 47, + // (assoc) HI3 = 48, + // (assoc) LO0 = 45, + // (assoc) LO1 = 46, + // (assoc) LO2 = 47, + // (assoc) LO3 = 48, +} + +impl RegisterMIPS { + pub const ZERO: RegisterMIPS = RegisterMIPS::GPR0; + pub const AT: RegisterMIPS = RegisterMIPS::GPR1; + pub const V0: RegisterMIPS = RegisterMIPS::GPR2; + pub const V1: RegisterMIPS = RegisterMIPS::GPR3; + pub const A0: RegisterMIPS = RegisterMIPS::GPR4; + pub const A1: RegisterMIPS = RegisterMIPS::GPR5; + pub const A2: RegisterMIPS = RegisterMIPS::GPR6; + pub const A3: RegisterMIPS = RegisterMIPS::GPR7; + pub const T0: RegisterMIPS = RegisterMIPS::GPR8; + pub const T1: RegisterMIPS = RegisterMIPS::GPR9; + pub const T2: RegisterMIPS = RegisterMIPS::GPR10; + pub const T3: RegisterMIPS = RegisterMIPS::GPR11; + pub const T4: RegisterMIPS = RegisterMIPS::GPR12; + pub const T5: RegisterMIPS = RegisterMIPS::GPR13; + pub const T6: RegisterMIPS = RegisterMIPS::GPR14; + pub const T7: RegisterMIPS = RegisterMIPS::GPR15; + pub const S0: RegisterMIPS = RegisterMIPS::GPR16; + pub const S1: RegisterMIPS = RegisterMIPS::GPR17; + pub const S2: RegisterMIPS = RegisterMIPS::GPR18; + pub const S3: RegisterMIPS = RegisterMIPS::GPR19; + pub const S4: RegisterMIPS = RegisterMIPS::GPR20; + pub const S5: RegisterMIPS = RegisterMIPS::GPR21; + pub const S6: RegisterMIPS = RegisterMIPS::GPR22; + pub const S7: RegisterMIPS = RegisterMIPS::GPR23; + pub const T8: RegisterMIPS = RegisterMIPS::GPR24; + pub const T9: RegisterMIPS = RegisterMIPS::GPR25; + pub const K0: RegisterMIPS = RegisterMIPS::GPR26; + pub const K1: RegisterMIPS = RegisterMIPS::GPR27; + pub const GP: RegisterMIPS = RegisterMIPS::GPR28; + pub const SP: RegisterMIPS = RegisterMIPS::GPR29; + pub const FP: RegisterMIPS = RegisterMIPS::GPR30; + pub const S8: RegisterMIPS = RegisterMIPS::GPR30; + pub const RA: RegisterMIPS = RegisterMIPS::GPR31; + pub const HI0: RegisterMIPS = RegisterMIPS::AC0; + pub const HI1: RegisterMIPS = RegisterMIPS::AC1; + pub const HI2: RegisterMIPS = RegisterMIPS::AC2; + pub const HI3: RegisterMIPS = RegisterMIPS::AC3; + pub const LO0: RegisterMIPS = RegisterMIPS::AC0; + pub const LO1: RegisterMIPS = RegisterMIPS::AC1; + pub const LO2: RegisterMIPS = RegisterMIPS::AC2; + pub const LO3: RegisterMIPS = RegisterMIPS::AC3; }