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Add read and write support for i386 XMM16-31

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elicn 2024-09-28 22:15:00 +03:00 committed by mio
parent 0626d4799a
commit 69c5a707c8
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GPG Key ID: DFF27E34A47CB873
2 changed files with 53 additions and 17 deletions
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10
qemu/target/i386/cpu.h
View File

@ -1432,11 +1432,15 @@ typedef struct CPUX86State {
ZMMReg xmm_t0; ZMMReg xmm_t0;
MMXReg mmx_t0; MMXReg mmx_t0;
XMMReg ymmh_regs[CPU_NB_REGS]; /*
* YMM is not supported by QEMU at all
* As of qemu 5.0.1, ymmh_regs is nowhere used.
*/
XMMReg ymmh_regs[CPU_NB_REGS]; /* currently not in use */
uint64_t opmask_regs[NB_OPMASK_REGS]; uint64_t opmask_regs[NB_OPMASK_REGS];
YMMReg zmmh_regs[CPU_NB_REGS]; YMMReg zmmh_regs[CPU_NB_REGS]; /* currently not in use */
ZMMReg hi16_zmm_regs[CPU_NB_REGS]; ZMMReg hi16_zmm_regs[CPU_NB_REGS]; /* currently not in use */
/* sysenter registers */ /* sysenter registers */
uint32_t sysenter_cs; uint32_t sysenter_cs;

60
qemu/target/i386/unicorn.c
View File

@ -285,9 +285,9 @@ uc_err reg_read(void *_env, int mode, unsigned int regid, void *value,
case UC_X86_REG_XMM5: case UC_X86_REG_XMM5:
case UC_X86_REG_XMM6: case UC_X86_REG_XMM6:
case UC_X86_REG_XMM7: { case UC_X86_REG_XMM7: {
CHECK_REG_TYPE(float64[2]); CHECK_REG_TYPE(uint64_t[2]);
float64 *dst = (float64 *)value; uint64_t *dst = (uint64_t *)value;
ZMMReg *reg = (ZMMReg *)&env->xmm_regs[regid - UC_X86_REG_XMM0]; const ZMMReg* const reg = &env->xmm_regs[regid - UC_X86_REG_XMM0];
dst[0] = reg->ZMM_Q(0); dst[0] = reg->ZMM_Q(0);
dst[1] = reg->ZMM_Q(1); dst[1] = reg->ZMM_Q(1);
return ret; return ret;
@ -968,10 +968,26 @@ uc_err reg_read(void *_env, int mode, unsigned int regid, void *value,
case UC_X86_REG_XMM12: case UC_X86_REG_XMM12:
case UC_X86_REG_XMM13: case UC_X86_REG_XMM13:
case UC_X86_REG_XMM14: case UC_X86_REG_XMM14:
case UC_X86_REG_XMM15: { case UC_X86_REG_XMM15:
CHECK_REG_TYPE(float64[2]); case UC_X86_REG_XMM16:
float64 *dst = (float64 *)value; case UC_X86_REG_XMM17:
ZMMReg *reg = (ZMMReg *)&env->xmm_regs[regid - UC_X86_REG_XMM0]; case UC_X86_REG_XMM18:
case UC_X86_REG_XMM19:
case UC_X86_REG_XMM20:
case UC_X86_REG_XMM21:
case UC_X86_REG_XMM22:
case UC_X86_REG_XMM23:
case UC_X86_REG_XMM24:
case UC_X86_REG_XMM25:
case UC_X86_REG_XMM26:
case UC_X86_REG_XMM27:
case UC_X86_REG_XMM28:
case UC_X86_REG_XMM29:
case UC_X86_REG_XMM30:
case UC_X86_REG_XMM31: {
CHECK_REG_TYPE(uint64_t[2]);
uint64_t *dst = (uint64_t *)value;
const ZMMReg* const reg = &env->xmm_regs[regid - UC_X86_REG_XMM0];
dst[0] = reg->ZMM_Q(0); dst[0] = reg->ZMM_Q(0);
dst[1] = reg->ZMM_Q(1); dst[1] = reg->ZMM_Q(1);
break; break;
@ -1046,9 +1062,9 @@ uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
case UC_X86_REG_XMM5: case UC_X86_REG_XMM5:
case UC_X86_REG_XMM6: case UC_X86_REG_XMM6:
case UC_X86_REG_XMM7: { case UC_X86_REG_XMM7: {
CHECK_REG_TYPE(float64[2]); CHECK_REG_TYPE(uint64_t[2]);
float64 *src = (float64 *)value; const uint64_t *src = (const uint64_t *)value;
ZMMReg *reg = (ZMMReg *)&env->xmm_regs[regid - UC_X86_REG_XMM0]; ZMMReg *reg = &env->xmm_regs[regid - UC_X86_REG_XMM0];
reg->ZMM_Q(0) = src[0]; reg->ZMM_Q(0) = src[0];
reg->ZMM_Q(1) = src[1]; reg->ZMM_Q(1) = src[1];
return ret; return ret;
@ -1794,10 +1810,26 @@ uc_err reg_write(void *_env, int mode, unsigned int regid, const void *value,
case UC_X86_REG_XMM12: case UC_X86_REG_XMM12:
case UC_X86_REG_XMM13: case UC_X86_REG_XMM13:
case UC_X86_REG_XMM14: case UC_X86_REG_XMM14:
case UC_X86_REG_XMM15: { case UC_X86_REG_XMM15:
CHECK_REG_TYPE(float64[2]); case UC_X86_REG_XMM16:
float64 *src = (float64 *)value; case UC_X86_REG_XMM17:
ZMMReg *reg = (ZMMReg *)&env->xmm_regs[regid - UC_X86_REG_XMM0]; case UC_X86_REG_XMM18:
case UC_X86_REG_XMM19:
case UC_X86_REG_XMM20:
case UC_X86_REG_XMM21:
case UC_X86_REG_XMM22:
case UC_X86_REG_XMM23:
case UC_X86_REG_XMM24:
case UC_X86_REG_XMM25:
case UC_X86_REG_XMM26:
case UC_X86_REG_XMM27:
case UC_X86_REG_XMM28:
case UC_X86_REG_XMM29:
case UC_X86_REG_XMM30:
case UC_X86_REG_XMM31: {
CHECK_REG_TYPE(uint64_t[2]);
const uint64_t *src = (const uint64_t *)value;
ZMMReg *reg = &env->xmm_regs[regid - UC_X86_REG_XMM0];
reg->ZMM_Q(0) = src[0]; reg->ZMM_Q(0) = src[0];
reg->ZMM_Q(1) = src[1]; reg->ZMM_Q(1) = src[1];
break; break;