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Fix for MIPS issue. (#733)

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xorstream 2017-01-23 15:39:34 +11:00 committed by Nguyen Anh Quynh
parent 2ecbe89cc1
commit 69ae8f7987
9 changed files with 229 additions and 227 deletions
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6
qemu/hw/mips/mips_r4k.c
View File

@ -45,11 +45,11 @@ void mips_machine_init(struct uc_struct *uc)
{ {
static QEMUMachine mips_machine = { static QEMUMachine mips_machine = {
NULL, NULL,
"mips", "mips",
mips_r4k_init, mips_r4k_init,
NULL, NULL,
0, 0,
1, 1,
UC_ARCH_MIPS, UC_ARCH_MIPS,
}; };

2
qemu/include/exec/cpu-defs.h
View File

@ -104,7 +104,7 @@ typedef struct CPUTLBEntry {
# endif # endif
#define DUMMY_SIZE (1 << CPU_TLB_ENTRY_BITS) - \ #define DUMMY_SIZE (1 << CPU_TLB_ENTRY_BITS) - \
(TARGET_ULONG_SIZE * 3 + \ (TARGET_ULONG_SIZE * 3 + \
((-TARGET_ULONG_SIZE * 3) & (UINTPTR_SIZE - 1)) + \ ((-TARGET_ULONG_SIZE * 3) & (UINTPTR_SIZE - 1)) + \
UINTPTR_SIZE) UINTPTR_SIZE)

14
qemu/target-mips/cpu.c
View File

@ -151,15 +151,17 @@ void mips_cpu_register_types(void *opaque)
sizeof(MIPSCPUClass), sizeof(MIPSCPUClass),
sizeof(MIPSCPU), sizeof(MIPSCPU),
opaque, opaque,
mips_cpu_initfn, mips_cpu_initfn,
NULL, NULL,
NULL, NULL,
NULL,
mips_cpu_class_init, mips_cpu_class_init,
NULL, NULL,
NULL, NULL,
false, false,
}; };

2
qemu/target-mips/cpu.h
View File

@ -571,7 +571,7 @@ struct CPUMIPSState {
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */ uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
int insn_flags; /* Supported instruction set */ int insn_flags; /* Supported instruction set */
CPU_COMMON CPU_COMMON
/* Fields from here on are preserved across CPU reset. */ /* Fields from here on are preserved across CPU reset. */
CPUMIPSMVPContext *mvp; CPUMIPSMVPContext *mvp;

6
qemu/target-mips/helper.c
View File

@ -382,8 +382,8 @@ static const char * const excp_names[EXCP_LAST + 1] = {
"debug single step", "debug single step",
"debug interrupt", "debug interrupt",
"debug data break load", "debug data break load",
"debug data break store", "debug data break store",
"non-maskable interrupt", "non-maskable interrupt",
"machine check", "machine check",
"interrupt", "interrupt",
"deferred watchpoint", "deferred watchpoint",
@ -413,7 +413,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
"DSP disabled", "DSP disabled",
"MSA disabled", "MSA disabled",
"MSA floating point", "MSA floating point",
"TLB execute-inhibit", "TLB execute-inhibit",
"TLB read-inhibit", "TLB read-inhibit",
}; };

56
qemu/target-mips/translate.c
View File

@ -5458,7 +5458,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 27: case 27:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 0: case 1: case 2: case 3:
tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */ tcg_gen_movi_tl(tcg_ctx, arg, 0); /* unimplemented */
rn = "CacheErr"; rn = "CacheErr";
break; break;
@ -5524,7 +5524,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE)); gen_mfc0_load32(ctx, arg, offsetof(CPUMIPSState, CP0_DESAVE));
rn = "DESAVE"; rn = "DESAVE";
break; break;
case 2: case 3: case 4: case 5: case 6: case 7: case 2: case 3: case 4: case 5: case 6: case 7:
CP0_CHECK(ctx->kscrexist & (1 << sel)); CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2])); offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@ -5947,7 +5947,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break; break;
case 18: case 18:
switch (sel) { switch (sel) {
case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7: case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel); gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel);
rn = "WatchLo"; rn = "WatchLo";
break; break;
@ -16274,7 +16274,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
generate_exception(ctx, EXCP_RI); generate_exception(ctx, EXCP_RI);
} }
break; break;
case OPC_DMULT: case OPC_DMULTU: case OPC_DDIV: case OPC_DDIVU: case OPC_DMULT: case OPC_DMULTU: case OPC_DDIV: case OPC_DDIVU:
op2 = MASK_R6_MULDIV(ctx->opcode); op2 = MASK_R6_MULDIV(ctx->opcode);
switch (op2) { switch (op2) {
case R6_OPC_DMUL: case R6_OPC_DMUL:
@ -16422,7 +16422,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break; break;
} }
break; break;
case OPC_ADD: case OPC_ADDU: case OPC_SUB: case OPC_SUBU: case OPC_ADD: case OPC_ADDU: case OPC_SUB: case OPC_SUBU:
gen_arith(ctx, op1, rd, rs, rt); gen_arith(ctx, op1, rd, rs, rt);
break; break;
case OPC_SLLV: /* Shifts */ case OPC_SLLV: /* Shifts */
@ -16458,7 +16458,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
case OPC_JALR: case OPC_JALR:
gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4); gen_compute_branch(ctx, op1, 4, rs, rd, sa, 4);
break; break;
case OPC_TGE: case OPC_TGEU: case OPC_TLT: case OPC_TLTU: case OPC_TEQ: case OPC_TGE: case OPC_TGEU: case OPC_TLT: case OPC_TLTU: case OPC_TEQ:
case OPC_TNE: case OPC_TNE:
gen_trap(ctx, op1, rs, rt, -1); gen_trap(ctx, op1, rs, rt, -1);
break; break;
@ -16533,7 +16533,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
break; break;
} }
break; break;
case OPC_DADD: case OPC_DADDU: case OPC_DSUB: case OPC_DSUBU: case OPC_DADD: case OPC_DADDU: case OPC_DSUB: case OPC_DSUBU:
check_insn(ctx, ISA_MIPS3); check_insn(ctx, ISA_MIPS3);
check_mips_64(ctx); check_mips_64(ctx);
gen_arith(ctx, op1, rd, rs, rt); gen_arith(ctx, op1, rd, rs, rt);
@ -16591,8 +16591,8 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL2(ctx->opcode); op1 = MASK_SPECIAL2(ctx->opcode);
switch (op1) { switch (op1) {
case OPC_MADD: case OPC_MADDU: case OPC_MADD: case OPC_MADDU:
case OPC_MSUB: case OPC_MSUBU: case OPC_MSUB: case OPC_MSUBU:
check_insn(ctx, ISA_MIPS32); check_insn(ctx, ISA_MIPS32);
gen_muldiv(ctx, op1, rd & 3, rs, rt); gen_muldiv(ctx, op1, rd & 3, rs, rt);
break; break;
@ -16684,7 +16684,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
case OPC_BSHFL: case OPC_BSHFL:
{ {
TCGv t0; TCGv t0;
if (rd == 0) { if (rd == 0) {
/* Treat as NOP. */ /* Treat as NOP. */
break; break;
} }
@ -16693,7 +16693,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
op2 = MASK_BSHFL(ctx->opcode); op2 = MASK_BSHFL(ctx->opcode);
switch (op2) { switch (op2) {
case OPC_ALIGN: case OPC_ALIGN_END: case OPC_ALIGN: case OPC_ALIGN_END:
sa &= 3; sa &= 3;
if (sa == 0) { if (sa == 0) {
tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0); tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0);
@ -16730,7 +16730,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx)
check_mips_64(ctx); check_mips_64(ctx);
{ {
TCGv t0; TCGv t0;
if (rd == 0) { if (rd == 0) {
/* Treat as NOP. */ /* Treat as NOP. */
break; break;
} }
@ -16780,9 +16780,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
op1 = MASK_SPECIAL3(ctx->opcode); op1 = MASK_SPECIAL3(ctx->opcode);
switch (op1) { switch (op1) {
case OPC_DIV_G_2E: case OPC_DIVU_G_2E: case OPC_DIV_G_2E: case OPC_DIVU_G_2E:
case OPC_MOD_G_2E: case OPC_MODU_G_2E: case OPC_MOD_G_2E: case OPC_MODU_G_2E:
case OPC_MULT_G_2E: case OPC_MULTU_G_2E: case OPC_MULT_G_2E: case OPC_MULTU_G_2E:
/* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1. */ * the same mask and op1. */
if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) { if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) {
@ -17047,9 +17047,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
} }
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DDIV_G_2E: case OPC_DDIVU_G_2E: case OPC_DDIV_G_2E: case OPC_DDIVU_G_2E:
case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E: case OPC_DMULT_G_2E: case OPC_DMULTU_G_2E:
case OPC_DMOD_G_2E: case OPC_DMODU_G_2E: case OPC_DMOD_G_2E: case OPC_DMODU_G_2E:
check_insn(ctx, INSN_LOONGSON2E); check_insn(ctx, INSN_LOONGSON2E);
gen_loongson_integer(ctx, op1, rd, rs, rt); gen_loongson_integer(ctx, op1, rd, rs, rt);
break; break;
@ -17324,9 +17324,9 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
} }
break; break;
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
case OPC_DEXTM: case OPC_DEXTU: case OPC_DEXT: case OPC_DEXTM: case OPC_DEXTU: case OPC_DEXT:
case OPC_DINSM: case OPC_DINSU: case OPC_DINS: case OPC_DINSM: case OPC_DINSU: case OPC_DINS:
check_insn(ctx, ISA_MIPS64R2); check_insn(ctx, ISA_MIPS64R2);
check_mips_64(ctx); check_mips_64(ctx);
gen_bitops(ctx, op1, rt, rs, sa, rd); gen_bitops(ctx, op1, rt, rs, sa, rd);
break; break;
@ -18587,7 +18587,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4);
} }
break; break;
case OPC_TGEI: case OPC_TGEIU: case OPC_TLTI: case OPC_TLTIU: case OPC_TEQI: /* REGIMM traps */ case OPC_TGEI: case OPC_TGEIU: case OPC_TLTI: case OPC_TLTIU: case OPC_TEQI: /* REGIMM traps */
case OPC_TNEI: case OPC_TNEI:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
gen_trap(ctx, op1, rs, -1, imm); gen_trap(ctx, op1, rs, -1, imm);
@ -18645,7 +18645,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
gen_cp0(env, ctx, op1, rt, rd); gen_cp0(env, ctx, op1, rt, rd);
#endif /* !CONFIG_USER_ONLY */ #endif /* !CONFIG_USER_ONLY */
break; break;
case OPC_C0_FIRST: case OPC_C0_LAST: case OPC_C0_FIRST: case OPC_C0_LAST:
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd); gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
#endif /* !CONFIG_USER_ONLY */ #endif /* !CONFIG_USER_ONLY */
@ -18740,7 +18740,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
case OPC_XORI: case OPC_XORI:
gen_logic_imm(ctx, op, rt, rs, imm); gen_logic_imm(ctx, op, rt, rs, imm);
break; break;
case OPC_J: case OPC_JAL: /* Jump */ case OPC_J: case OPC_JAL: /* Jump */
offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2; offset = (int32_t)(ctx->opcode & 0x3FFFFFF) << 2;
gen_compute_branch(ctx, op, 4, rs, rt, offset, 4); gen_compute_branch(ctx, op, 4, rs, rt, offset, 4);
break; break;
@ -18802,14 +18802,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
case OPC_LWR: case OPC_LWR:
case OPC_LL: case OPC_LL:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_LB: case OPC_LH: case OPC_LB: case OPC_LH:
case OPC_LW: case OPC_LBU: case OPC_LHU: case OPC_LW: case OPC_LBU: case OPC_LHU:
gen_ld(ctx, op, rt, rs, imm); gen_ld(ctx, op, rt, rs, imm);
break; break;
case OPC_SWL: case OPC_SWL:
case OPC_SWR: case OPC_SWR:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_SB: case OPC_SH: case OPC_SB: case OPC_SH:
case OPC_SW: case OPC_SW:
gen_st(ctx, op, rt, rs, imm); gen_st(ctx, op, rt, rs, imm);
break; break;
@ -19067,7 +19067,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
/* MIPS64 opcodes */ /* MIPS64 opcodes */
case OPC_LDL: case OPC_LDR: case OPC_LDL: case OPC_LDR:
case OPC_LLD: case OPC_LLD:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_LWU: case OPC_LWU:
@ -19076,7 +19076,7 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pa
check_mips_64(ctx); check_mips_64(ctx);
gen_ld(ctx, op, rt, rs, imm); gen_ld(ctx, op, rt, rs, imm);
break; break;
case OPC_SDL: case OPC_SDR: case OPC_SDL: case OPC_SDR:
check_insn_opc_removed(ctx, ISA_MIPS32R6); check_insn_opc_removed(ctx, ISA_MIPS32R6);
case OPC_SD: case OPC_SD:
check_insn(ctx, ISA_MIPS3); check_insn(ctx, ISA_MIPS3);

364
qemu/target-mips/translate_init.c
View File

@ -118,22 +118,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2, MIPS_CONFIG2,
MIPS_CONFIG3, MIPS_CONFIG3,
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
4, 4,
32, 32,
2, 2,
0x1278FF17, 0x1278FF17,
0, 0,
0, 0,
0, 0,
0, 0,
32, 32,
32, 32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32, CPU_MIPS32,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -149,24 +149,24 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2, MIPS_CONFIG2,
MIPS_CONFIG3, MIPS_CONFIG3,
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
4, 4,
32, 32,
2, 2,
0x1258FF17, 0x1258FF17,
0, 0,
0, 0,
0, 0,
0, 0,
32, 32,
32, 32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32 | ASE_MIPS16, CPU_MIPS32 | ASE_MIPS16,
MMU_TYPE_FMT, MMU_TYPE_FMT,
}, },
{ {
@ -180,22 +180,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2, MIPS_CONFIG2,
MIPS_CONFIG3, MIPS_CONFIG3,
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
4, 4,
32, 32,
2, 2,
0x1278FF17, 0x1278FF17,
0, 0,
0, 0,
0, 0,
0, 0,
32, 32,
32, 32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32, CPU_MIPS32,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -209,22 +209,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2, MIPS_CONFIG2,
MIPS_CONFIG3, MIPS_CONFIG3,
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
4, 4,
32, 32,
2, 2,
0x1258FF17, 0x1258FF17,
0, 0,
0, 0,
0, 0,
0, 0,
32, 32,
32, 32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32 | ASE_MIPS16, CPU_MIPS32 | ASE_MIPS16,
MMU_TYPE_FMT, MMU_TYPE_FMT,
}, },
{ {
@ -239,22 +239,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2, MIPS_CONFIG2,
MIPS_CONFIG3 | (0 << CP0C3_VInt), MIPS_CONFIG3 | (0 << CP0C3_VInt),
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
4, 4,
32, 32,
2, 2,
0x1278FF17, 0x1278FF17,
0, 0,
0, 0,
0, 0,
0, 0,
32, 32,
32, 32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R2, CPU_MIPS32R2,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -269,22 +269,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2, MIPS_CONFIG2,
MIPS_CONFIG3, MIPS_CONFIG3,
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
4, 4,
32, 32,
2, 2,
0x1258FF17, 0x1258FF17,
0, 0,
0, 0,
0, 0,
0, 0,
32, 32,
32, 32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R2 | ASE_MIPS16, CPU_MIPS32R2 | ASE_MIPS16,
MMU_TYPE_FMT, MMU_TYPE_FMT,
}, },
{ {
@ -299,22 +299,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2, MIPS_CONFIG2,
MIPS_CONFIG3 | (0 << CP0C3_VInt), MIPS_CONFIG3 | (0 << CP0C3_VInt),
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
4, 4,
32, 32,
2, 2,
/* No DSP implemented. */ /* No DSP implemented. */
0x1278FF1F, 0x1278FF1F,
0, 0,
0, 0,
0, 0,
32, 32,
32, 32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R2 | ASE_MIPS16, CPU_MIPS32R2 | ASE_MIPS16,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -329,24 +329,24 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2, MIPS_CONFIG2,
MIPS_CONFIG3 | (0 << CP0C3_VInt), MIPS_CONFIG3 | (0 << CP0C3_VInt),
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
4, 4,
32, 32,
2, 2,
/* No DSP implemented. */ /* No DSP implemented. */
0x3678FF1F, 0x3678FF1F,
0, 0,
0, 0,
(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
0, 0,
32, 32,
32, 32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R2 | ASE_MIPS16, CPU_MIPS32R2 | ASE_MIPS16,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -376,7 +376,7 @@ static const mips_def_t mips_defs[] =
0, 0,
32, 32,
32, 32,
(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
0x3fffffff, 0x3fffffff,
(1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
@ -394,7 +394,7 @@ static const mips_def_t mips_defs[] =
(0x3fe << CP0SRSC4_SRS15) | (0x3fe << CP0SRSC4_SRS15) |
(0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13), (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
0,0, 0,0,
CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -410,23 +410,23 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
(0 << CP0C3_VInt), (0 << CP0C3_VInt),
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
4, 4,
32, 32,
2, 2,
0x3778FF1F, 0x3778FF1F,
0, 0,
0, 0,
(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
0, 0,
32, 32,
32, 32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -450,22 +450,22 @@ static const mips_def_t mips_defs[] =
(1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) | (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
(0 << CP0C5_NFExists), (0 << CP0C5_NFExists),
0, 0,
0, 0,
0, 0,
4, 4,
32, 32,
2, 2,
0x3778FF1F, 0x3778FF1F,
0, 0,
0, 0,
(1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
(1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
(0x93 << FCR0_PRID), (0x93 << FCR0_PRID),
0, 0,
32, 32,
32, 32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA, CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
@ -477,25 +477,25 @@ static const mips_def_t mips_defs[] =
/* Note: Config1 is only used internally, the R4000 has only Config0. */ /* Note: Config1 is only used internally, the R4000 has only Config0. */
(1 << CP0C1_FP) | (47 << CP0C1_MMU), (1 << CP0C1_FP) | (47 << CP0C1_MMU),
0, 0,
0, 0,
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0xFFFFFFFF, 0xFFFFFFFF,
4, 4,
16, 16,
2, 2,
0x3678FFFF, 0x3678FFFF,
0, 0,
0, 0,
/* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */ /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
(0x5 << FCR0_PRID) | (0x0 << FCR0_REV), (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
0, 0,
40, 40,
36, 36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS3, CPU_MIPS3,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -505,25 +505,25 @@ static const mips_def_t mips_defs[] =
(1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0), (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
(1 << CP0C1_FP) | (47 << CP0C1_MMU), (1 << CP0C1_FP) | (47 << CP0C1_MMU),
0, 0,
0, 0,
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0xFFFFFFFFL, 0xFFFFFFFFL,
4, 4,
16, 16,
2, 2,
0x3678FFFF, 0x3678FFFF,
0, 0,
0, 0,
/* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */ /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
(0x54 << FCR0_PRID) | (0x0 << FCR0_REV), (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
0, 0,
40, 40,
32, 32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_VR54XX, CPU_VR54XX,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -538,22 +538,22 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2, MIPS_CONFIG2,
MIPS_CONFIG3, MIPS_CONFIG3,
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
4, 4,
32, 32,
2, 2,
0x32F8FFFF, 0x32F8FFFF,
0, 0,
0, 0,
0, 0,
0, 0,
42, 42,
36, 36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS64, CPU_MIPS64,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -568,25 +568,25 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2, MIPS_CONFIG2,
MIPS_CONFIG3, MIPS_CONFIG3,
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
4, 4,
32, 32,
2, 2,
0x36F8FFFF, 0x36F8FFFF,
0, 0,
0, 0,
/* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */ /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
(1 << FCR0_D) | (1 << FCR0_S) | (1 << FCR0_D) | (1 << FCR0_S) |
(0x81 << FCR0_PRID) | (0x0 << FCR0_REV), (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
0, 0,
42, 42,
36, 36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS64, CPU_MIPS64,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -603,25 +603,25 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2, MIPS_CONFIG2,
MIPS_CONFIG3, MIPS_CONFIG3,
0,.0, 0,.0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
0, 0,
32, 32,
1, 1,
0x36FBFFFF, 0x36FBFFFF,
0, 0,
0, 0,
/* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */ /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
(1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_3D) | (1 << FCR0_PS) |
(1 << FCR0_D) | (1 << FCR0_S) | (1 << FCR0_D) | (1 << FCR0_S) |
(0x82 << FCR0_PRID) | (0x0 << FCR0_REV), (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
0, 0,
40, 40,
36, 36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS64 | ASE_MIPS3D, CPU_MIPS64 | ASE_MIPS3D,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -638,27 +638,27 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG2, MIPS_CONFIG2,
MIPS_CONFIG3 | (1 << CP0C3_LPA), MIPS_CONFIG3 | (1 << CP0C3_LPA),
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
0, 0,
32, 32,
2, 2,
0x36FBFFFF, 0x36FBFFFF,
0, 0,
0, 0,
(1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
0, 0,
42, 42,
/* The architectural limit is 59, but we have hardcoded 36 bit /* The architectural limit is 59, but we have hardcoded 36 bit
in some places... in some places...
59, */ /* the architectural limit */ 59, */ /* the architectural limit */
36, 36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS64R2 | ASE_MIPS3D, CPU_MIPS64R2 | ASE_MIPS3D,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -678,32 +678,32 @@ static const mips_def_t mips_defs[] =
(1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M), (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M),
MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) | MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
(3 << CP0C4_IE) | (1 << CP0C4_M), (3 << CP0C4_IE) | (1 << CP0C4_M),
0,
0, 0,
(1 << CP0C5_SBRI),
0, 0,
0, (1 << CP0C5_SBRI),
0, 0,
0,
0,
0, 0,
32, 32,
2, 2,
0x30D8FFFF, 0x30D8FFFF,
0, 0,
0, 0,
(1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
(1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) | (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
(0x0 << FCR0_REV), (0x0 << FCR0_REV),
0, 0,
42, 42,
/* The architectural limit is 59, but we have hardcoded 36 bit /* The architectural limit is 59, but we have hardcoded 36 bit
in some places... in some places...
59, */ /* the architectural limit */ 59, */ /* the architectural limit */
36, 36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
(1 << CP0PG_IEC) | (1 << CP0PG_XIE) | (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
(1U << CP0PG_RIE), (1U << CP0PG_RIE),
0, 0,
CPU_MIPS64R6, CPU_MIPS64R6,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -715,24 +715,24 @@ static const mips_def_t mips_defs[] =
/* Note: Config1 is only used internally, Loongson-2E has only Config0. */ /* Note: Config1 is only used internally, Loongson-2E has only Config0. */
(1 << CP0C1_FP) | (47 << CP0C1_MMU), (1 << CP0C1_FP) | (47 << CP0C1_MMU),
0, 0,
0, 0,
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
0, 0,
16, 16,
2, 2,
0x35D0FFFF, 0x35D0FFFF,
0, 0,
0,
(0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
0, 0,
40, (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
0,
40,
40, 40,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_LOONGSON2E, CPU_LOONGSON2E,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -744,24 +744,24 @@ static const mips_def_t mips_defs[] =
/* Note: Config1 is only used internally, Loongson-2F has only Config0. */ /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
(1 << CP0C1_FP) | (47 << CP0C1_MMU), (1 << CP0C1_FP) | (47 << CP0C1_MMU),
0, 0,
0, 0,
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
0, 0,
16, 16,
2, 2,
0xF5D0FF1F, /*bit5:7 not writable*/ 0xF5D0FF1F, /*bit5:7 not writable*/
0, 0,
0,
(0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
0, 0,
40, (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
0,
40,
40, 40,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_LOONGSON2F, CPU_LOONGSON2F,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{ {
@ -779,30 +779,30 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
(1 << CP0C3_DSPP) | (1 << CP0C3_LPA), (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
0,0, 0,0,
0,0, 0,0,
0, 0,
0, 0,
0, 0,
0, 0,
32, 32,
2, 2,
0x37FBFFFF, 0x37FBFFFF,
0, 0,
0, 0,
(1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
(1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
(1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
0, 0,
42, 42,
/* The architectural limit is 59, but we have hardcoded 36 bit /* The architectural limit is 59, but we have hardcoded 36 bit
in some places... in some places...
59, */ /* the architectural limit */ 59, */ /* the architectural limit */
36, 36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2, CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
#endif #endif
}; };

4
qemu/target-mips/unicorn.c
View File

@ -43,7 +43,7 @@ void mips_release(void *ctx);
void mips_release(void *ctx) void mips_release(void *ctx)
{ {
MIPSCPU* cpu; MIPSCPU* cpu;
int i; int i;
TCGContext *tcg_ctx = (TCGContext *) ctx; TCGContext *tcg_ctx = (TCGContext *) ctx;
release_common(ctx); release_common(ctx);
cpu = MIPS_CPU(tcg_ctx->uc, tcg_ctx->uc->cpu); cpu = MIPS_CPU(tcg_ctx->uc, tcg_ctx->uc->cpu);
@ -70,7 +70,7 @@ void mips_release(void *ctx)
void mips_reg_reset(struct uc_struct *uc) void mips_reg_reset(struct uc_struct *uc)
{ {
CPUArchState *env; CPUArchState *env;
(void)uc; (void)uc;
env = uc->cpu->env_ptr; env = uc->cpu->env_ptr;
memset(env->active_tc.gpr, 0, sizeof(env->active_tc.gpr)); memset(env->active_tc.gpr, 0, sizeof(env->active_tc.gpr));

2
samples/sample_x86_32_gdt_and_seg_regs.c
View File

@ -164,7 +164,7 @@ static void gdt_demo()
uc_x86_mmr gdtr; uc_x86_mmr gdtr;
int i; int i;
/* /*
bits 32 bits 32
push dword 0x01234567 push dword 0x01234567