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lazymio 2021-11-03 13:28:12 +01:00
parent 09aa0f944f
commit 58edb2abe7
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GPG Key ID: DFF27E34A47CB873
1 changed files with 98 additions and 90 deletions
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36
tests/unit/test_riscv.c
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@ -217,14 +217,16 @@ static void test_riscv64_3steps_pc_update()
OK(uc_close(uc));
}
static void test_riscv32_fp_move(void) {
static void test_riscv32_fp_move(void)
{
uc_engine *uc;
char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
uint32_t r_f1 = 0x1234;
uint32_t r_f3 = 0x5678;
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code, sizeof(code) - 1);
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV32, code,
sizeof(code) - 1);
// initialize machine registers
uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1);
@ -242,14 +244,16 @@ static void test_riscv32_fp_move(void) {
uc_close(uc);
}
static void test_riscv64_fp_move(void) {
static void test_riscv64_fp_move(void)
{
uc_engine *uc;
char code[] = "\xd3\x81\x10\x22"; // fmv.d f3, f1
uint64_t r_f1 = 0x12341234;
uint64_t r_f3 = 0x56785678;
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1);
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
sizeof(code) - 1);
// initialize machine registers
OK(uc_reg_write(uc, UC_RISCV_REG_F1, &r_f1));
@ -267,18 +271,21 @@ static void test_riscv64_fp_move(void) {
uc_close(uc);
}
static void test_riscv64_fp_move_from_int(void) {
static void test_riscv64_fp_move_from_int(void)
{
uc_engine *uc;
// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
// https://five-embeddev.com/quickref/csrs.html
// We have to enable mstatus.fs
char code[] = "\xf3\x90\x01\x30\x53\x00\x0b\xf2"; // csrrw x2, mstatus, x3; fmvd.d.x ft0, s6
char code[] = "\xf3\x90\x01\x30\x53\x00\x0b\xf2"; // csrrw x2, mstatus, x3;
// fmvd.d.x ft0, s6
uint64_t r_ft0 = 0x12341234;
uint64_t r_s6 = 0x56785678;
uint64_t r_x3 = 0x6000;
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1);
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
sizeof(code) - 1);
// initialize machine registers
OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0));
@ -299,18 +306,21 @@ static void test_riscv64_fp_move_from_int(void) {
uc_close(uc);
}
static void test_riscv64_fp_move_to_int(void) {
static void test_riscv64_fp_move_to_int(void)
{
uc_engine *uc;
// https://riscv.org/wp-content/uploads/2017/05/riscv-spec-v2.2.pdf
// https://five-embeddev.com/quickref/csrs.html
// We have to enable mstatus.fs
char code[] = "\xf3\x90\x01\x30\x53\x0b\x00\xe2"; // csrrw x2, mstatus, x3; fmv.x.d s6, ft0
char code[] = "\xf3\x90\x01\x30\x53\x0b\x00\xe2"; // csrrw x2, mstatus, x3;
// fmv.x.d s6, ft0
uint64_t r_ft0 = 0x12341234;
uint64_t r_s6 = 0x56785678;
uint64_t r_x3 = 0x6000;
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code, sizeof(code) - 1);
uc_common_setup(&uc, UC_ARCH_RISCV, UC_MODE_RISCV64, code,
sizeof(code) - 1);
// initialize machine registers
OK(uc_reg_write(uc, UC_RISCV_REG_FT0, &r_ft0));
@ -331,8 +341,7 @@ static void test_riscv64_fp_move_to_int(void) {
uc_close(uc);
}
TEST_LIST = {
{ "test_riscv32_nop", test_riscv32_nop },
TEST_LIST = {{"test_riscv32_nop", test_riscv32_nop},
{"test_riscv64_nop", test_riscv64_nop},
{"test_riscv32_3steps_pc_update", test_riscv32_3steps_pc_update},
{"test_riscv64_3steps_pc_update", test_riscv64_3steps_pc_update},
@ -342,5 +351,4 @@ TEST_LIST = {
{"test_riscv64_fp_move", test_riscv64_fp_move},
{"test_riscv64_fp_move_from_int", test_riscv64_fp_move_from_int},
{"test_riscv64_fp_move_to_int", test_riscv64_fp_move_to_int},
{ NULL, NULL }
};
{NULL, NULL}};