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fix some oss-fuzz (#1218)

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* fix oss-fuzz 18138.

* fix oss-fuzz 20079.

* fix oss-fuzz 20209.

* fix oss-fuzz 20210.

* fix oss-fuzz 20262.

* rollback.

* rollback.

* fix oss-fuzz 20079.

* fix oss-fuzz 20179.

* fix oss-fuzz 20195.

* fix oss-fuzz 20206.

* fix oss-fuzz 20207.

* fix oss-fuzz 20265.

* fix oss-fuzz 20285.

* fix oss-fuzz 20868.

* fix oss-fuzz 20908.

* fix oss-fuzz 20909.

* fix oss-fuzz 20914.

* fix oss-fuzz 20922.

* fix oss-fuzz 20928.

* remove warnigs.
This commit is contained in:
Chen Huitao 2020-03-02 09:44:53 +08:00 committed by GitHub
parent a68ef62915
commit 4ca2c7f0b0
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
7 changed files with 7 additions and 7 deletions
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2
qemu/fpu/softfloat-specialize.h
View File

@ -122,7 +122,7 @@ const float128 float128_default_nan
| should be simply `float_exception_flags |= flags;'.
*----------------------------------------------------------------------------*/
void float_raise( int8 flags STATUS_PARAM )
void float_raise( uint8_t flags STATUS_PARAM )
{
STATUS(float_exception_flags) |= flags;
}

2
qemu/fpu/softfloat.c
View File

@ -2974,7 +2974,7 @@ int32 float64_to_int32_round_to_zero( float64 a STATUS_PARAM )
savedASig = aSig;
aSig >>= shiftCount;
z = (int32_t)aSig;
if ( aSign ) z = - z;
if ( aSign && (z != 0x80000000)) z = - z;
if ( ( z < 0 ) ^ aSign ) {
invalid:
float_raise( float_flag_invalid STATUS_VAR);

2
qemu/include/fpu/softfloat.h
View File

@ -246,7 +246,7 @@ static inline flag get_default_nan_mode(float_status *status)
| Routine to raise any or all of the software IEC/IEEE floating-point
| exception flags.
*----------------------------------------------------------------------------*/
void float_raise( int8 flags STATUS_PARAM);
void float_raise( uint8_t flags STATUS_PARAM);
/*----------------------------------------------------------------------------
| If `a' is denormal and we are in flush-to-zero mode then set the

2
qemu/target-arm/neon_helper.c
View File

@ -732,7 +732,7 @@ uint64_t HELPER(neon_rshl_s64)(uint64_t valop, uint64_t shiftop)
val >>= 1;
}
} else {
val <<= shift;
val = ((uint64_t)val) << shift;
}
return val;
}

2
qemu/target-arm/translate-a64.c
View File

@ -5584,7 +5584,7 @@ static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int size = ctz32(imm5);
int esize = 8 << size;
int esize = 8 << (size & 0x1f);
int elements = (is_q ? 128 : 64) / esize;
int index, i;
TCGv_i64 tmp;

2
qemu/target-i386/ops_sse.h
View File

@ -1678,7 +1678,7 @@ SSE_HELPER_L(helper_pmaxsd, FMAXSD)
SSE_HELPER_W(helper_pmaxuw, MAX)
SSE_HELPER_L(helper_pmaxud, MAX)
#define FMULLD(d, s) ((int32_t)d * (int32_t)s)
#define FMULLD(d, s) ((int64_t)d * (int32_t)s)
SSE_HELPER_L(helper_pmulld, FMULLD)
void glue(helper_phminposuw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)

2
qemu/tcg/tcg-op.h
View File

@ -2079,7 +2079,7 @@ static inline void tcg_gen_deposit_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg
return;
}
mask = (1u << len) - 1;
mask = (1u << (len & 0x1f)) - 1;
t1 = tcg_temp_new_i32(s);
if (ofs + len < 32) {