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4ba29a4ed3
@ -159,8 +159,8 @@ class Init(regress.RegressTest):
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except UcError as e:
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print("ERROR: %s" % e)
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# now print out some registers
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print(">>> Emulation done. Below is the CPU context")
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rdx = mu.reg_read(UC_X86_REG_RDX)
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self.assertEqual(rdx, 0xbabe, "RDX contains the wrong value. Eflags modification failed.")
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if __name__ == '__main__':
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