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aarch64: Move FPCR and FPSR registers to not break compatibility

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Co-authored-by: merry <git@mary.rs>
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TSR Berry 2022-10-14 17:27:47 +02:00
parent c787fa8e64
commit 442dd437e1
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GPG Key ID: 52353C0A4CCA15E2
2 changed files with 16 additions and 16 deletions
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8
include/unicorn/arm64.h
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@ -313,10 +313,6 @@ typedef enum uc_arm64_reg {
UC_ARM64_REG_PSTATE, UC_ARM64_REG_PSTATE,
//> floating point control and status registers
UC_ARM64_REG_FPCR,
UC_ARM64_REG_FPSR,
//> exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead //> exception link registers, depreciated, use UC_ARM64_REG_CP_REG instead
UC_ARM64_REG_ELR_EL0, UC_ARM64_REG_ELR_EL0,
UC_ARM64_REG_ELR_EL1, UC_ARM64_REG_ELR_EL1,
@ -354,6 +350,10 @@ typedef enum uc_arm64_reg {
UC_ARM64_REG_CP_REG, UC_ARM64_REG_CP_REG,
//> floating point control and status registers
UC_ARM64_REG_FPCR,
UC_ARM64_REG_FPSR,
UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers
//> alias registers //> alias registers

24
qemu/target/arm/unicorn_aarch64.c
View File

@ -210,12 +210,6 @@ static uc_err reg_read(CPUARMState *env, unsigned int regid, void *value)
case UC_ARM64_REG_PSTATE: case UC_ARM64_REG_PSTATE:
*(uint32_t *)value = pstate_read(env); *(uint32_t *)value = pstate_read(env);
break; break;
case UC_ARM64_REG_FPCR:
*(uint32_t *)value = vfp_get_fpcr(env);
break;
case UC_ARM64_REG_FPSR:
*(uint32_t *)value = vfp_get_fpsr(env);
break;
case UC_ARM64_REG_TTBR0_EL1: case UC_ARM64_REG_TTBR0_EL1:
*(uint64_t *)value = env->cp15.ttbr0_el[1]; *(uint64_t *)value = env->cp15.ttbr0_el[1];
break; break;
@ -231,6 +225,12 @@ static uc_err reg_read(CPUARMState *env, unsigned int regid, void *value)
case UC_ARM64_REG_CP_REG: case UC_ARM64_REG_CP_REG:
ret = read_cp_reg(env, (uc_arm64_cp_reg *)value); ret = read_cp_reg(env, (uc_arm64_cp_reg *)value);
break; break;
case UC_ARM64_REG_FPCR:
*(uint32_t *)value = vfp_get_fpcr(env);
break;
case UC_ARM64_REG_FPSR:
*(uint32_t *)value = vfp_get_fpsr(env);
break;
} }
} }
@ -309,12 +309,6 @@ static uc_err reg_write(CPUARMState *env, unsigned int regid, const void *value)
case UC_ARM64_REG_PSTATE: case UC_ARM64_REG_PSTATE:
pstate_write(env, *(uint32_t *)value); pstate_write(env, *(uint32_t *)value);
break; break;
case UC_ARM64_REG_FPCR:
vfp_set_fpcr(env, *(uint32_t *)value);
break;
case UC_ARM64_REG_FPSR:
vfp_set_fpsr(env, *(uint32_t *)value);
break;
case UC_ARM64_REG_TTBR0_EL1: case UC_ARM64_REG_TTBR0_EL1:
env->cp15.ttbr0_el[1] = *(uint64_t *)value; env->cp15.ttbr0_el[1] = *(uint64_t *)value;
break; break;
@ -330,6 +324,12 @@ static uc_err reg_write(CPUARMState *env, unsigned int regid, const void *value)
case UC_ARM64_REG_CP_REG: case UC_ARM64_REG_CP_REG:
ret = write_cp_reg(env, (uc_arm64_cp_reg *)value); ret = write_cp_reg(env, (uc_arm64_cp_reg *)value);
break; break;
case UC_ARM64_REG_FPCR:
vfp_set_fpcr(env, *(uint32_t *)value);
break;
case UC_ARM64_REG_FPSR:
vfp_set_fpsr(env, *(uint32_t *)value);
break;
} }
} }