Fix wrong cput model check in uc_ctl

2022-07-23 20:49:00 +08:00 · 2022-07-23 20:49:00 +08:00 · 3d028882ed
parent 6db6790ec2
commit 3d028882ed
1 changed files with 1 additions and 1 deletions
--- a/uc.c
+++ b/uc.c
@ -2240,7 +2240,7 @@ uc_err uc_ctl(uc_engine *uc, uc_control_type control, ...)
        } else {
            int model = va_arg(args, int);

-            if (model <= 0 || uc->init_done) {
+            if (model < 0 || uc->init_done) {
                err = UC_ERR_ARG;
                break;
            }