From 3cc9005a471608c267b4a3f95538c9c3e92749ac Mon Sep 17 00:00:00 2001 From: Bet4 <0xbet4@gmail.com> Date: Tue, 10 May 2022 19:24:59 +0800 Subject: [PATCH] Add TriCore constants to Rust bindings --- .gitignore | 2 +- bindings/rust/README.md | 2 +- bindings/rust/src/arm64.rs | 6 +- bindings/rust/src/lib.rs | 14 +-- bindings/rust/src/tricore.rs | 137 +++++++++++++++++++++++++++++ bindings/rust/src/unicorn_const.rs | 7 +- 6 files changed, 154 insertions(+), 14 deletions(-) create mode 100644 bindings/rust/src/tricore.rs diff --git a/.gitignore b/.gitignore index 3fd9cb69..ced6f437 100644 --- a/.gitignore +++ b/.gitignore @@ -53,7 +53,7 @@ bindings/python/unicorn.egg-info/ bindings/python/unicorn/lib/ bindings/python/unicorn/include/ bindings/python/MANIFEST -target/ +/target/ Cargo.lock config.log diff --git a/bindings/rust/README.md b/bindings/rust/README.md index fb177203..35b881aa 100644 --- a/bindings/rust/README.md +++ b/bindings/rust/README.md @@ -24,7 +24,7 @@ fn main() { assert_eq!(emu.reg_read(RegisterARM::R5), Ok(1337)); } ``` -Further sample code can be found in ```tests/unicorn.rs```. +Further sample code can be found in [tests](../../tests/rust-tests/main.rs). ## Usage diff --git a/bindings/rust/src/arm64.rs b/bindings/rust/src/arm64.rs index 0745d90e..2d41f37a 100644 --- a/bindings/rust/src/arm64.rs +++ b/bindings/rust/src/arm64.rs @@ -305,14 +305,14 @@ pub enum RegisterARM64 { VBAR_EL3 = 289, CP_REG = 290, ENDING = 291, +} + +impl RegisterARM64 { // alias registers // (assoc) IP0 = 215, // (assoc) IP1 = 216, // (assoc) FP = 1, // (assoc) LR = 2, -} - -impl RegisterARM64 { pub const IP0: RegisterARM64 = RegisterARM64::X16; pub const IP1: RegisterARM64 = RegisterARM64::X17; pub const FP: RegisterARM64 = RegisterARM64::X29; diff --git a/bindings/rust/src/lib.rs b/bindings/rust/src/lib.rs index ba92523e..7959e2d5 100644 --- a/bindings/rust/src/lib.rs +++ b/bindings/rust/src/lib.rs @@ -42,11 +42,12 @@ mod ppc; mod riscv; mod s390x; mod sparc; +mod tricore; mod x86; pub use crate::{ - arm::*, arm64::*, m68k::*, mips::*, ppc::*, riscv::*, s390x::*, sparc::*, unicorn_const::*, - x86::*, + arm::*, arm64::*, m68k::*, mips::*, ppc::*, riscv::*, s390x::*, sparc::*, tricore::*, + unicorn_const::*, x86::*, }; use alloc::{boxed::Box, rc::Rc, vec::Vec}; @@ -544,7 +545,6 @@ impl<'a, D> Unicorn<'a, D> { /// /// This adds safe support for registers >64 bit (GDTR/IDTR, XMM, YMM, ZMM, ST (x86); Q, V (arm64)). pub fn reg_read_long>(&self, regid: T) -> Result, uc_error> { - let err: uc_error; let boxed: Box<[u8]>; let mut value: Vec; let curr_reg_id = regid.into(); @@ -586,7 +586,7 @@ impl<'a, D> Unicorn<'a, D> { return Err(uc_error::ARCH); } - err = unsafe { ffi::uc_reg_read(self.get_handle(), curr_reg_id, value.as_mut_ptr() as _) }; + let err: uc_error = unsafe { ffi::uc_reg_read(self.get_handle(), curr_reg_id, value.as_mut_ptr() as _) }; if err == uc_error::OK { boxed = value.into_boxed_slice(); @@ -900,15 +900,13 @@ impl<'a, D> Unicorn<'a, D> { /// /// `hook` is the value returned by `add_*_hook` functions. pub fn remove_hook(&mut self, hook: ffi::uc_hook) -> Result<(), uc_error> { - let err: uc_error; - // drop the hook let inner = self.inner_mut(); inner .hooks .retain(|(hook_ptr, _hook_impl)| hook_ptr != &hook); - err = unsafe { ffi::uc_hook_del(inner.handle, hook) }; + let err: uc_error = unsafe { ffi::uc_hook_del(inner.handle, hook) }; if err == uc_error::OK { Ok(()) @@ -1041,6 +1039,7 @@ impl<'a, D> Unicorn<'a, D> { Arch::PPC => RegisterPPC::PC as i32, Arch::RISCV => RegisterRISCV::PC as i32, Arch::S390X => RegisterS390X::PC as i32, + Arch::TRICORE => RegisterTRICORE::PC as i32, Arch::MAX => panic!("Illegal Arch specified"), }; self.reg_read(reg) @@ -1060,6 +1059,7 @@ impl<'a, D> Unicorn<'a, D> { Arch::PPC => RegisterPPC::PC as i32, Arch::RISCV => RegisterRISCV::PC as i32, Arch::S390X => RegisterS390X::PC as i32, + Arch::TRICORE => RegisterTRICORE::PC as i32, Arch::MAX => panic!("Illegal Arch specified"), }; self.reg_write(reg, value) diff --git a/bindings/rust/src/tricore.rs b/bindings/rust/src/tricore.rs new file mode 100644 index 00000000..652108f3 --- /dev/null +++ b/bindings/rust/src/tricore.rs @@ -0,0 +1,137 @@ +// TRICORE registers +#[repr(C)] +#[derive(PartialEq, Debug, Clone, Copy)] +#[allow(non_camel_case_types)] +pub enum RegisterTRICORE { + INVALID = 0, + A0 = 1, + A1 = 2, + A2 = 3, + A3 = 4, + A4 = 5, + A5 = 6, + A6 = 7, + A7 = 8, + A8 = 9, + A9 = 10, + A10 = 11, + A11 = 12, + A12 = 13, + A13 = 14, + A14 = 15, + A15 = 16, + D0 = 17, + D1 = 18, + D2 = 19, + D3 = 20, + D4 = 21, + D5 = 22, + D6 = 23, + D7 = 24, + D8 = 25, + D9 = 26, + D10 = 27, + D11 = 28, + D12 = 29, + D13 = 30, + D14 = 31, + D15 = 32, + PCXI = 33, + PSW = 34, + PSW_USB_C = 35, + PSW_USB_V = 36, + PSW_USB_SV = 37, + PSW_USB_AV = 38, + PSW_USB_SAV = 39, + PC = 40, + SYSCON = 41, + CPU_ID = 42, + BIV = 43, + BTV = 44, + ISP = 45, + ICR = 46, + FCX = 47, + LCX = 48, + COMPAT = 49, + DPR0_U = 50, + DPR1_U = 51, + DPR2_U = 52, + DPR3_U = 53, + DPR0_L = 54, + DPR1_L = 55, + DPR2_L = 56, + DPR3_L = 57, + CPR0_U = 58, + CPR1_U = 59, + CPR2_U = 60, + CPR3_U = 61, + CPR0_L = 62, + CPR1_L = 63, + CPR2_L = 64, + CPR3_L = 65, + DPM0 = 66, + DPM1 = 67, + DPM2 = 68, + DPM3 = 69, + CPM0 = 70, + CPM1 = 71, + CPM2 = 72, + CPM3 = 73, + MMU_CON = 74, + MMU_ASI = 75, + MMU_TVA = 76, + MMU_TPA = 77, + MMU_TPX = 78, + MMU_TFA = 79, + BMACON = 80, + SMACON = 81, + DIEAR = 82, + DIETR = 83, + CCDIER = 84, + MIECON = 85, + PIEAR = 86, + PIETR = 87, + CCPIER = 88, + DBGSR = 89, + EXEVT = 90, + CREVT = 91, + SWEVT = 92, + TR0EVT = 93, + TR1EVT = 94, + DMS = 95, + DCX = 96, + DBGTCR = 97, + CCTRL = 98, + CCNT = 99, + ICNT = 100, + M1CNT = 101, + M2CNT = 102, + M3CNT = 103, + ENDING = 104, +} + +impl RegisterTRICORE { + // alias registers + // (assoc) GA0 = 1, + // (assoc) GA1 = 2, + // (assoc) GA8 = 9, + // (assoc) GA9 = 10, + // (assoc) SP = 11, + // (assoc) LR = 12, + // (assoc) IA = 16, + // (assoc) ID = 32, + pub const GA0: RegisterTRICORE = RegisterTRICORE::A0; + pub const GA1: RegisterTRICORE = RegisterTRICORE::A1; + pub const GA8: RegisterTRICORE = RegisterTRICORE::A8; + pub const GA9: RegisterTRICORE = RegisterTRICORE::A9; + pub const SP: RegisterTRICORE = RegisterTRICORE::A10; + pub const LR: RegisterTRICORE = RegisterTRICORE::A11; + pub const IA: RegisterTRICORE = RegisterTRICORE::A15; + pub const ID: RegisterTRICORE = RegisterTRICORE::D15; +} + +impl From for i32 { + fn from(r: RegisterTRICORE) -> Self { + r as i32 + } +} diff --git a/bindings/rust/src/unicorn_const.rs b/bindings/rust/src/unicorn_const.rs index e6da574c..b226b8f8 100644 --- a/bindings/rust/src/unicorn_const.rs +++ b/bindings/rust/src/unicorn_const.rs @@ -5,7 +5,8 @@ pub const API_MAJOR: u64 = 2; pub const API_MINOR: u64 = 0; pub const VERSION_MAJOR: u64 = 2; pub const VERSION_MINOR: u64 = 0; -pub const VERSION_EXTRA: u64 = 6; +pub const VERSION_PATCH: u64 = 0; +pub const VERSION_EXTRA: u64 = 7; pub const SECOND_SCALE: u64 = 1_000_000; pub const MILISECOND_SCALE: u64 = 1_000; @@ -129,7 +130,8 @@ pub enum Arch { M68K = 7, RISCV = 8, S390X = 9, - MAX = 10, + TRICORE = 10, + MAX = 11, } impl TryFrom for Arch { @@ -146,6 +148,7 @@ impl TryFrom for Arch { x if x == Self::M68K as usize => Ok(Self::M68K), x if x == Self::RISCV as usize => Ok(Self::RISCV), x if x == Self::S390X as usize => Ok(Self::S390X), + x if x == Self::TRICORE as usize => Ok(Self::TRICORE), x if x == Self::MAX as usize => Ok(Self::MAX), _ => Err(uc_error::ARCH), }