cleanup RAMList & exec.c
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036306579a
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38ddaf585f
@ -42,7 +42,6 @@ typedef struct {
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typedef struct RAMList {
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RAMBlock *mru_block;
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QTAILQ_HEAD(, RAMBlock) blocks;
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uint32_t version;
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} RAMList;
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#endif
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139
qemu/exec.c
139
qemu/exec.c
@ -36,9 +36,6 @@
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#include "qemu/timer.h"
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#include "exec/memory.h"
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#include "exec/address-spaces.h"
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#if defined(CONFIG_USER_ONLY)
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#include <qemu.h>
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#endif
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#include "exec/cpu-all.h"
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#include "exec/cputlb.h"
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@ -53,20 +50,12 @@
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//#define DEBUG_SUBPAGE
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#if !defined(CONFIG_USER_ONLY)
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/* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
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#define RAM_PREALLOC (1 << 0)
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/* RAM is mmap-ed with MAP_SHARED */
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#define RAM_SHARED (1 << 1)
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#endif
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#if !defined(CONFIG_USER_ONLY)
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/* current CPU in the current thread. It is only valid inside
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cpu_exec() */
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//DEFINE_TLS(CPUState *, current_cpu);
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typedef struct PhysPageEntry PhysPageEntry;
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@ -123,10 +112,6 @@ typedef struct subpage_t {
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static void memory_map_init(struct uc_struct *uc);
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static void tcg_commit(MemoryListener *listener);
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#endif
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#if !defined(CONFIG_USER_ONLY)
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static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes)
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{
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if (map->nodes_nb + nodes > map->nodes_nb_alloc) {
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@ -366,7 +351,6 @@ address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat,
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return section;
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}
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#endif
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CPUState *qemu_get_cpu(struct uc_struct *uc, int index)
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{
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@ -377,7 +361,6 @@ CPUState *qemu_get_cpu(struct uc_struct *uc, int index)
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return NULL;
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}
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#if !defined(CONFIG_USER_ONLY)
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void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as)
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{
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/* We only support one address space per cpu at the moment. */
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@ -391,7 +374,6 @@ void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as)
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cpu->tcg_as_listener->commit = tcg_commit;
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memory_listener_register(as->uc, cpu->tcg_as_listener, as);
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}
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#endif
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void cpu_exec_init(CPUArchState *env, void *opaque)
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{
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@ -413,12 +395,6 @@ void cpu_exec_init(CPUArchState *env, void *opaque)
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}
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#if defined(TARGET_HAS_ICE)
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#if defined(CONFIG_USER_ONLY)
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static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
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{
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tb_invalidate_phys_page_range(pc, pc + 1, 0);
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}
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#else
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static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
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{
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hwaddr phys = cpu_get_phys_page_debug(cpu, pc);
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@ -427,31 +403,8 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
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phys | (pc & ~TARGET_PAGE_MASK));
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}
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}
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#endif
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#endif /* TARGET_HAS_ICE */
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#if defined(CONFIG_USER_ONLY)
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void cpu_watchpoint_remove_all(CPUState *cpu, int mask)
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{
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}
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int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, vaddr len,
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int flags)
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{
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return -ENOSYS;
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}
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void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint)
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{
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}
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int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
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int flags, CPUWatchpoint **watchpoint)
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{
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return -ENOSYS;
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}
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#else
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/* Add a watchpoint. */
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int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
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int flags, CPUWatchpoint **watchpoint)
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@ -540,8 +493,6 @@ static inline bool cpu_watchpoint_address_matches(CPUWatchpoint *wp,
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return !(addr > wpend || wp->vaddr > addrend);
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}
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#endif
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/* Add a breakpoint. */
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int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
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CPUBreakpoint **breakpoint)
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@ -616,28 +567,11 @@ void cpu_breakpoint_remove_all(CPUState *cpu, int mask)
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#endif
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}
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/* enable or disable single step mode. EXCP_DEBUG is returned by the
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CPU loop after each instruction */
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void cpu_single_step(CPUState *cpu, int enabled)
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{
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#if defined(TARGET_HAS_ICE)
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if (cpu->singlestep_enabled != enabled) {
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CPUArchState *env;
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cpu->singlestep_enabled = enabled;
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/* must flush all the translated code to avoid inconsistencies */
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/* XXX: only flush what is necessary */
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env = cpu->env_ptr;
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tb_flush(env);
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}
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#endif
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}
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void cpu_abort(CPUState *cpu, const char *fmt, ...)
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{
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abort();
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}
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#if !defined(CONFIG_USER_ONLY)
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static RAMBlock *qemu_get_ram_block(struct uc_struct *uc, ram_addr_t addr)
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{
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RAMBlock *block;
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@ -729,9 +663,7 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu,
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return iotlb;
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}
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#endif /* defined(CONFIG_USER_ONLY) */
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#if !defined(CONFIG_USER_ONLY)
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static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
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uint16_t section);
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@ -740,16 +672,6 @@ static subpage_t *subpage_init(AddressSpace *as, hwaddr base);
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static void *(*phys_mem_alloc)(size_t size, uint64_t *align) =
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qemu_anon_ram_alloc;
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/*
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* Set a custom physical guest memory alloator.
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* Accelerators with unusual needs may need this. Hopefully, we can
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* get rid of it eventually.
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*/
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void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align))
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{
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phys_mem_alloc = alloc;
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}
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static uint16_t phys_section_add(PhysPageMap *map,
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MemoryRegionSection *section)
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{
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@ -861,14 +783,6 @@ static void mem_add(MemoryListener *listener, MemoryRegionSection *section)
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}
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}
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#ifdef __linux__
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#include <sys/vfs.h>
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#define HUGETLBFS_MAGIC 0x958458f6
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#endif
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static ram_addr_t find_ram_offset(struct uc_struct *uc, ram_addr_t size)
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{
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RAMBlock *block, *next_block;
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@ -942,8 +856,6 @@ static ram_addr_t ram_block_add(struct uc_struct *uc, RAMBlock *new_block)
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}
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uc->ram_list.mru_block = NULL;
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uc->ram_list.version++;
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cpu_physical_memory_set_dirty_range(uc, new_block->offset, new_block->length);
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return new_block->offset;
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@ -985,7 +897,6 @@ void qemu_ram_free_from_ptr(struct uc_struct *uc, ram_addr_t addr)
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if (addr == block->offset) {
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QTAILQ_REMOVE(&uc->ram_list.blocks, block, next);
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uc->ram_list.mru_block = NULL;
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uc->ram_list.version++;
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g_free(block);
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break;
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}
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@ -1000,7 +911,6 @@ void qemu_ram_free(struct uc_struct *uc, ram_addr_t addr)
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if (addr == block->offset) {
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QTAILQ_REMOVE(&uc->ram_list.blocks, block, next);
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uc->ram_list.mru_block = NULL;
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uc->ram_list.version++;
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if (!block->flags) {
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qemu_anon_ram_free(block->host, block->length);
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}
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@ -1368,9 +1278,7 @@ static void memory_map_init(struct uc_struct *uc)
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void cpu_exec_init_all(struct uc_struct *uc)
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{
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#if !defined(CONFIG_USER_ONLY)
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memory_map_init(uc);
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#endif
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io_mem_init(uc);
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}
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@ -1379,51 +1287,7 @@ MemoryRegion *get_system_memory(struct uc_struct *uc)
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return uc->system_memory;
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}
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#endif /* !defined(CONFIG_USER_ONLY) */
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/* physical memory access (slow version, mainly for debug) */
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#if defined(CONFIG_USER_ONLY)
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int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
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uint8_t *buf, int len, int is_write)
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{
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int l, flags;
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target_ulong page;
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void * p;
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while (len > 0) {
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page = addr & TARGET_PAGE_MASK;
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l = (page + TARGET_PAGE_SIZE) - addr;
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if (l > len)
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l = len;
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flags = page_get_flags(page);
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if (!(flags & PAGE_VALID))
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return -1;
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if (is_write) {
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if (!(flags & PAGE_WRITE))
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return -1;
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/* XXX: this code should not depend on lock_user */
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if (!(p = lock_user(VERIFY_WRITE, addr, l, 0)))
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return -1;
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memcpy(p, buf, l);
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unlock_user(p, addr, l);
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} else {
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if (!(flags & PAGE_READ))
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return -1;
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/* XXX: this code should not depend on lock_user */
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if (!(p = lock_user(VERIFY_READ, addr, l, 1)))
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return -1;
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memcpy(buf, p, l);
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unlock_user(p, addr, 0);
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}
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len -= l;
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buf += l;
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addr += l;
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}
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return 0;
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}
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#else
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static void invalidate_and_set_dirty(struct uc_struct *uc, hwaddr addr,
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hwaddr length)
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{
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@ -2131,7 +1995,6 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
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}
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return 0;
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}
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#endif
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/*
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* A helper function for the _utterly broken_ virtio device model to find out if
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@ -2147,7 +2010,6 @@ bool target_words_bigendian(void)
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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bool cpu_physical_memory_is_io(AddressSpace *as, hwaddr phys_addr)
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{
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MemoryRegion*mr;
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@ -2166,4 +2028,3 @@ void qemu_ram_foreach_block(struct uc_struct *uc, RAMBlockIterFunc func, void *o
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func(block->host, block->offset, block->length, opaque);
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}
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}
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#endif
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@ -91,7 +91,7 @@ void tb_invalidate_phys_page_range(struct uc_struct *uc, tb_page_addr_t start, t
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int is_cpu_write_access);
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void tb_invalidate_phys_range(struct uc_struct *uc, tb_page_addr_t start, tb_page_addr_t end,
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int is_cpu_write_access);
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#if !defined(CONFIG_USER_ONLY)
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void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as);
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/* cputlb.c */
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void tlb_flush_page(CPUState *cpu, target_ulong addr);
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@ -102,16 +102,6 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
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void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
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#else
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static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
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{
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}
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static inline void tlb_flush(CPUState *cpu, int flush_global)
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{
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}
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#endif
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#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
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#define CODE_GEN_PHYS_HASH_BITS 15
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