Add tests for armeb CPSR.E and SCTLR.B
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@ -646,6 +646,55 @@ static void test_arm_read_sctlr()
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OK(uc_close(uc));
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}
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static void test_arm_be_cpsr_sctlr()
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{
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uc_engine *uc;
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uc_arm_cp_reg reg;
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uint32_t cpsr;
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OK(uc_open(UC_ARCH_ARM, UC_MODE_BIG_ENDIAN, &uc));
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OK(uc_ctl_set_cpu_model(
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uc, UC_CPU_ARM_1176)); // big endian code, big endian data
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// SCTLR. See arm reference.
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reg.cp = 15;
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reg.is64 = 0;
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reg.sec = 0;
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reg.crn = 1;
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reg.crm = 0;
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reg.opc1 = 0;
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reg.opc2 = 0;
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OK(uc_reg_read(uc, UC_ARM_REG_CP_REG, ®));
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OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &cpsr));
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TEST_CHECK((reg.val & (1 << 7)) != 0);
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TEST_CHECK((cpsr & (1 << 9)) != 0);
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OK(uc_close(uc));
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OK(uc_open(UC_ARCH_ARM, UC_MODE_ARMBE8, &uc));
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OK(uc_ctl_set_cpu_model(uc, UC_CPU_ARM_CORTEX_A15));
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// SCTLR. See arm reference.
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reg.cp = 15;
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reg.is64 = 0;
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reg.sec = 0;
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reg.crn = 1;
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reg.crm = 0;
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reg.opc1 = 0;
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reg.opc2 = 0;
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OK(uc_reg_read(uc, UC_ARM_REG_CP_REG, ®));
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OK(uc_reg_read(uc, UC_ARM_REG_CPSR, &cpsr));
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// SCTLR.B == 0
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TEST_CHECK((reg.val & (1 << 7)) == 0);
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TEST_CHECK((cpsr & (1 << 9)) != 0);
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OK(uc_close(uc));
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}
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TEST_LIST = {{"test_arm_nop", test_arm_nop},
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{"test_arm_thumb_sub", test_arm_thumb_sub},
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{"test_armeb_sub", test_armeb_sub},
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@ -665,4 +714,5 @@ TEST_LIST = {{"test_arm_nop", test_arm_nop},
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{"test_arm_hflags_rebuilt", test_arm_hflags_rebuilt},
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{"test_arm_mem_access_abort", test_arm_mem_access_abort},
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{"test_arm_read_sctlr", test_arm_read_sctlr},
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{"test_arm_be_cpsr_sctlr", test_arm_be_cpsr_sctlr},
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{NULL, NULL}};
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